package/kernel/lantiq/ltq-atm/src/ltq_atm.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 **
  23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
  24 *******************************************************************************/
  25
  26 #define IFX_ATM_VER_MAJOR               1
  27 #define IFX_ATM_VER_MID                 0
  28 #define IFX_ATM_VER_MINOR               26
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/version.h>
  33 #include <linux/types.h>
  34 #include <linux/errno.h>
  35 #include <linux/proc_fs.h>
  36 #include <linux/init.h>
  37 #include <linux/ioctl.h>
  38 #include <linux/atmdev.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/of_device.h>
  41 #include <linux/atm.h>
  42 #include <linux/clk.h>
  43 #include <linux/interrupt.h>
  44 #ifdef CONFIG_XFRM
  45   #include <net/xfrm.h>
  46 #endif
  47
  48 #include <lantiq_soc.h>
  49
  50 #include "ifxmips_atm_core.h"
  51
  52 #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
  53 #define MODULE_PARM(a, b)         module_param(a, int, 0)
  54
  55 /*!
  56   \brief QSB cell delay variation due to concurrency
  57  */
  58 static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
  59 /*!
  60   \brief QSB scheduler burst length
  61  */
  62 static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
  63 /*!
  64   \brief QSB time step, all legal values are 1, 2, 4
  65  */
  66 static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
  67
  68 /*!
  69   \brief Write descriptor delay
  70  */
  71 static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
  72
  73 /*!
  74   \brief AAL5 padding byte ('~')
  75  */
  76 static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
  77 /*!
  78   \brief Max frame size for RX
  79  */
  80 static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
  81 /*!
  82   \brief Min frame size for RX
  83  */
  84 static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
  85 /*!
  86   \brief Max frame size for TX
  87  */
  88 static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
  89 /*!
  90   \brief Min frame size for TX
  91  */
  92 static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
  93 /*!
  94   \brief Drop error packet in RX path
  95  */
  96 static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
  97
  98 /*!
  99   \brief Number of descriptors per DMA RX channel
 100  */
 101 static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
 102 /*!
 103   \brief Number of descriptors per DMA TX channel
 104  */
 105 static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
 106 /*!
 107   \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
 108  */
 109 static int dma_rx_clp1_descriptor_threshold = 38;
 110 /*@}*/
 111
 112 MODULE_PARM(qsb_tau, "i");
 113 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
 114 MODULE_PARM(qsb_srvm, "i");
 115 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
 116 MODULE_PARM(qsb_tstep, "i");
 117 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
 118
 119 MODULE_PARM(write_descriptor_delay, "i");
 120 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
 121
 122 MODULE_PARM(aal5_fill_pattern, "i");
 123 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
 124 MODULE_PARM(aal5r_max_packet_size, "i");
 125 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
 126 MODULE_PARM(aal5r_min_packet_size, "i");
 127 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
 128 MODULE_PARM(aal5s_max_packet_size, "i");
 129 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
 130 MODULE_PARM(aal5s_min_packet_size, "i");
 131 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
 132 MODULE_PARM(aal5r_drop_error_packet, "i");
 133 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
 134
 135 MODULE_PARM(dma_rx_descriptor_length, "i");
 136 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
 137 MODULE_PARM(dma_tx_descriptor_length, "i");
 138 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
 139 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
 140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
 141
 142
 143
 144 /*
 145  * ####################################
 146  *              Definition
 147  * ####################################
 148  */
 149
 150 #ifdef CONFIG_AMAZON_SE
 151   #define ENABLE_LESS_CACHE_INV                 1
 152   #define LESS_CACHE_INV_LEN                    96
 153 #endif
 154
 155 #define DUMP_SKB_LEN                            ~0
 156
 157
 158
 159 /*
 160  * ####################################
 161  *             Declaration
 162  * ####################################
 163  */
 164
 165 /*
 166  *  Network Operations
 167  */
 168 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
 169 static int ppe_open(struct atm_vcc *);
 170 static void ppe_close(struct atm_vcc *);
 171 static int ppe_send(struct atm_vcc *, struct sk_buff *);
 172 static int ppe_send_oam(struct atm_vcc *, void *, int);
 173 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
 174
 175 /*
 176  *  ADSL LED
 177  */
 178 static inline void adsl_led_flash(void);
 179
 180 /*
 181  *  64-bit operation used by MIB calculation
 182  */
 183 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
 184
 185 /*
 186  *  buffer manage functions
 187  */
 188 static inline struct sk_buff* alloc_skb_rx(void);
 189 static inline struct sk_buff* alloc_skb_tx(unsigned int);
 190 struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
 191 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
 192 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
 193 static inline int get_tx_desc(unsigned int);
 194
 195 /*
 196  *  mailbox handler and signal function
 197  */
 198 static inline void mailbox_oam_rx_handler(void);
 199 static inline void mailbox_aal_rx_handler(void);
 200 static irqreturn_t mailbox_irq_handler(int, void *);
 201 static inline void mailbox_signal(unsigned int, int);
 202 static void do_ppe_tasklet(unsigned long);
 203 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
 204
 205 /*
 206  *  QSB & HTU setting functions
 207  */
 208 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
 209 static void qsb_global_set(void);
 210 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
 211 static inline void clear_htu_entry(unsigned int);
 212 static void validate_oam_htu_entry(void);
 213 static void invalidate_oam_htu_entry(void);
 214
 215 /*
 216  *  look up for connection ID
 217  */
 218 static inline int find_vpi(unsigned int);
 219 static inline int find_vpivci(unsigned int, unsigned int);
 220 static inline int find_vcc(struct atm_vcc *);
 221
 222 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
 223
 224 /*
 225  *  Init & clean-up functions
 226  */
 227 static inline void check_parameters(void);
 228 static inline int init_priv_data(void);
 229 static inline void clear_priv_data(void);
 230 static inline void init_rx_tables(void);
 231 static inline void init_tx_tables(void);
 232
 233 /*
 234  *  Exteranl Function
 235  */
 236 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
 237 extern void ifx_push_oam(unsigned char *);
 238 #else
 239 static inline void ifx_push_oam(unsigned char *dummy) {}
 240 #endif
 241
 242 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
 243 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
 244 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
 245
 246 extern int (*ifx_mei_atm_showtime_exit)(void);
 247 extern int ifx_mei_atm_led_blink(void);
 248 #else
 249 static inline int ifx_mei_atm_led_blink(void) { return 0; }
 250 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
 251 {
 252         if ( is_showtime != NULL )
 253                 *is_showtime = 0;
 254         return 0;
 255 }
 256 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
 257 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
 258
 259 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
 260 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
 261
 262 #endif
 263
 264 static struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
 265
 266 static struct atm_priv_data g_atm_priv_data;
 267
 268 static struct atmdev_ops g_ifx_atm_ops = {
 269         .open = ppe_open,
 270         .close = ppe_close,
 271         .ioctl = ppe_ioctl,
 272         .send = ppe_send,
 273         .send_oam = ppe_send_oam,
 274         .change_qos = ppe_change_qos,
 275         .owner = THIS_MODULE,
 276 };
 277
 278 static int g_showtime = 0;
 279 static void *g_xdata_addr = NULL;
 280
 281 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
 282 {
 283         int ret = 0;
 284         atm_cell_ifEntry_t mib_cell;
 285         atm_aal5_ifEntry_t mib_aal5;
 286         atm_aal5_vcc_x_t mib_vcc;
 287         unsigned int value;
 288         int conn;
 289
 290         if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
 291                         || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
 292                 return -ENOTTY;
 293
 294         if ( _IOC_DIR(cmd) & _IOC_READ )
 295                 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 296         else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 297                 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 298         if ( ret )
 299                 return -EFAULT;
 300
 301         switch (cmd) {
 302         case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
 303                 /*  These MIB should be read at ARC side, now put zero only.    */
 304                 mib_cell.ifHCInOctets_h = 0;
 305                 mib_cell.ifHCInOctets_l = 0;
 306                 mib_cell.ifHCOutOctets_h = 0;
 307                 mib_cell.ifHCOutOctets_l = 0;
 308                 mib_cell.ifInErrors = 0;
 309                 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
 310                 mib_cell.ifOutErrors = 0;
 311
 312                 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
 313                 break;
 314
 315         case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
 316                 value = WAN_MIB_TABLE->wrx_total_byte;
 317                 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
 318                 g_atm_priv_data.prev_wrx_total_byte = value;
 319                 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
 320                 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
 321
 322                 value = WAN_MIB_TABLE->wtx_total_byte;
 323                 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
 324                 g_atm_priv_data.prev_wtx_total_byte = value;
 325                 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
 326                 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
 327
 328                 mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
 329                 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
 330                 mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
 331                 mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
 332                 mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
 333                 mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
 334
 335                 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
 336                 break;
 337
 338         case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
 339                 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
 340                 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
 341                 if (conn >= 0) {
 342                         mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
 343                         mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
 344                         mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
 345                         ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
 346                 } else
 347                         ret = -EINVAL;
 348                 break;
 349
 350         default:
 351                 ret = -ENOIOCTLCMD;
 352         }
 353
 354         return ret;
 355 }
 356
 357 static int ppe_open(struct atm_vcc *vcc)
 358 {
 359         int ret;
 360         short vpi = vcc->vpi;
 361         int   vci = vcc->vci;
 362         struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
 363         int conn;
 364         int f_enable_irq = 0;
 365
 366         if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
 367                 return -EPROTONOSUPPORT;
 368
 369 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
 370         /*  check bandwidth */
 371         if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 372                 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 373 #if 0
 374                 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 375 #endif
 376                 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
 377         {
 378                 ret = -EINVAL;
 379                 goto PPE_OPEN_EXIT;
 380         }
 381 #endif
 382
 383         /*  check existing vpi,vci  */
 384         conn = find_vpivci(vpi, vci);
 385         if ( conn >= 0 ) {
 386                 ret = -EADDRINUSE;
 387                 goto PPE_OPEN_EXIT;
 388         }
 389
 390         /*  check whether it need to enable irq */
 391         if ( g_atm_priv_data.conn_table == 0 )
 392                 f_enable_irq = 1;
 393
 394         /*  allocate connection */
 395         for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
 396                 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
 397                         g_atm_priv_data.conn[conn].vcc = vcc;
 398                         break;
 399                 }
 400         }
 401         if ( conn == MAX_PVC_NUMBER ) {
 402                 ret = -EINVAL;
 403                 goto PPE_OPEN_EXIT;
 404         }
 405
 406         /*  reserve bandwidth   */
 407         switch ( vcc->qos.txtp.traffic_class ) {
 408         case ATM_CBR:
 409         case ATM_VBR_RT:
 410                 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
 411                 break;
 412         case ATM_VBR_NRT:
 413 #if 0
 414                 port->tx_current_cell_rate += vcc->qos.txtp.scr;
 415 #endif
 416                 break;
 417         case ATM_UBR_PLUS:
 418                 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
 419                 break;
 420         }
 421
 422         /*  set qsb */
 423         set_qsb(vcc, &vcc->qos, conn);
 424
 425         /*  update atm_vcc structure    */
 426         vcc->itf = (int)vcc->dev->dev_data;
 427         vcc->vpi = vpi;
 428         vcc->vci = vci;
 429         set_bit(ATM_VF_READY, &vcc->flags);
 430
 431         /*  enable irq  */
 432         if ( f_enable_irq ) {
 433                 ifx_atm_alloc_tx = atm_alloc_tx;
 434
 435                 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 436                 *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 437
 438                 enable_irq(PPE_MAILBOX_IGU1_INT);
 439         }
 440
 441         /*  set port    */
 442         WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
 443
 444         /*  set htu entry   */
 445         set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
 446
 447         *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
 448         *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
 449
 450         ret = 0;
 451
 452 PPE_OPEN_EXIT:
 453         return ret;
 454 }
 455
 456 static void ppe_close(struct atm_vcc *vcc)
 457 {
 458         int conn;
 459         struct port *port;
 460         struct connection *connection;
 461         if ( vcc == NULL )
 462                 return;
 463
 464         /*  get connection id   */
 465         conn = find_vcc(vcc);
 466         if ( conn < 0 ) {
 467                 pr_err("can't find vcc\n");
 468                 goto PPE_CLOSE_EXIT;
 469         }
 470         connection = &g_atm_priv_data.conn[conn];
 471         port = &g_atm_priv_data.port[connection->port];
 472
 473         /*  clear htu   */
 474         clear_htu_entry(conn);
 475
 476         /*  release connection  */
 477         connection->vcc = NULL;
 478         connection->aal5_vcc_crc_err = 0;
 479         connection->aal5_vcc_oversize_sdu = 0;
 480         clear_bit(conn, &g_atm_priv_data.conn_table);
 481
 482         /*  disable irq */
 483         if ( g_atm_priv_data.conn_table == 0 ) {
 484                 disable_irq(PPE_MAILBOX_IGU1_INT);
 485                 ifx_atm_alloc_tx = NULL;
 486         }
 487
 488         /*  release bandwidth   */
 489         switch ( vcc->qos.txtp.traffic_class )
 490         {
 491         case ATM_CBR:
 492         case ATM_VBR_RT:
 493                 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
 494                 break;
 495         case ATM_VBR_NRT:
 496 #if 0
 497                 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
 498 #endif
 499                 break;
 500         case ATM_UBR_PLUS:
 501                 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
 502                 break;
 503         }
 504
 505         /* wait for incoming packets to be processed by upper layers */
 506         tasklet_unlock_wait(&g_dma_tasklet);
 507
 508 PPE_CLOSE_EXIT:
 509         return;
 510 }
 511
 512 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
 513 {
 514         int ret;
 515         int conn;
 516         int desc_base;
 517         int byteoff;
 518         int required;
 519         /* the len of the data without offset and header */
 520         int datalen;
 521         unsigned long flags;
 522         struct tx_descriptor reg_desc = {0};
 523         struct tx_inband_header *header;
 524
 525         if ( vcc == NULL || skb == NULL )
 526                 return -EINVAL;
 527
 528
 529         conn = find_vcc(vcc);
 530         if ( conn < 0 ) {
 531                 ret = -EINVAL;
 532                 goto FIND_VCC_FAIL;
 533         }
 534
 535         if ( !g_showtime ) {
 536                 pr_debug("not in showtime\n");
 537                 ret = -EIO;
 538                 goto PPE_SEND_FAIL;
 539         }
 540
 541         byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 542         required = sizeof(*header) + byteoff;
 543         if (!skb_clone_writable(skb, required)) {
 544                 int expand_by = 0;
 545                 int ret;
 546
 547                 if (skb_headroom(skb) < required)
 548                         expand_by = required - skb_headroom(skb);
 549
 550                 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
 551                 if (ret) {
 552                         printk("pskb_expand_head failed.\n");
 553                         atm_free_tx_skb_vcc(skb, vcc);
 554                         return ret;
 555                 }
 556         }
 557
 558         datalen = skb->len;
 559         header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
 560
 561
 562         if ( vcc->qos.aal == ATM_AAL5 ) {
 563                 /*  setup inband trailer    */
 564                 header->uu   = 0;
 565                 header->cpi  = 0;
 566                 header->pad  = aal5_fill_pattern;
 567                 header->res1 = 0;
 568
 569                 /*  setup cell header   */
 570                 header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
 571                 header->pti  = ATM_PTI_US0;
 572                 header->vci  = vcc->vci;
 573                 header->vpi  = vcc->vpi;
 574                 header->gfc  = 0;
 575
 576                 /*  setup descriptor    */
 577                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 578                 reg_desc.datalen = datalen;
 579                 reg_desc.byteoff = byteoff;
 580                 reg_desc.iscell  = 0;
 581         } else {
 582                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 583                 reg_desc.datalen = skb->len;
 584                 reg_desc.byteoff = byteoff;
 585                 reg_desc.iscell  = 1;
 586         }
 587
 588         reg_desc.own = 1;
 589         reg_desc.c = 1;
 590         reg_desc.sop = reg_desc.eop = 1;
 591
 592         spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
 593         desc_base = get_tx_desc(conn);
 594         if ( desc_base < 0 ) {
 595                 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 596                 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
 597                 ret = -EIO;
 598                 goto PPE_SEND_FAIL;
 599         }
 600         /*  update descriptor send pointer  */
 601         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 602                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 603         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 604
 605         spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 606
 607         if ( vcc->stats )
 608                 atomic_inc(&vcc->stats->tx);
 609         if ( vcc->qos.aal == ATM_AAL5 )
 610                 g_atm_priv_data.wtx_pdu++;
 611         /*  write discriptor to memory and write back cache */
 612         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 613         dma_cache_wback((unsigned long)skb->data, skb->len);
 614
 615         mailbox_signal(conn, 1);
 616
 617         adsl_led_flash();
 618
 619         return 0;
 620
 621 FIND_VCC_FAIL:
 622         pr_err("FIND_VCC_FAIL\n");
 623         g_atm_priv_data.wtx_err_pdu++;
 624         dev_kfree_skb_any(skb);
 625         return ret;
 626
 627 PPE_SEND_FAIL:
 628         if ( vcc->qos.aal == ATM_AAL5 )
 629                 g_atm_priv_data.wtx_drop_pdu++;
 630         if ( vcc->stats )
 631                 atomic_inc(&vcc->stats->tx_err);
 632         dev_kfree_skb_any(skb);
 633         return ret;
 634 }
 635
 636 /* operation and maintainance */
 637 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
 638 {
 639         int conn;
 640         struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
 641         int desc_base;
 642         struct sk_buff *skb;
 643         struct tx_descriptor reg_desc = {0};
 644
 645         if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
 646                         && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
 647                         || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
 648                         && find_vpi(uni_cell_header->vpi) < 0) )
 649         {
 650                 g_atm_priv_data.wtx_err_oam++;
 651                 return -EINVAL;
 652         }
 653
 654         if ( !g_showtime ) {
 655                 pr_err("not in showtime\n");
 656                 g_atm_priv_data.wtx_drop_oam++;
 657                 return -EIO;
 658         }
 659
 660         conn = find_vcc(vcc);
 661         if ( conn < 0 ) {
 662                 pr_err("FIND_VCC_FAIL\n");
 663                 g_atm_priv_data.wtx_drop_oam++;
 664                 return -EINVAL;
 665         }
 666
 667         skb = alloc_skb_tx(CELL_SIZE);
 668         if ( skb == NULL ) {
 669                 pr_err("ALLOC_SKB_TX_FAIL\n");
 670                 g_atm_priv_data.wtx_drop_oam++;
 671                 return -ENOMEM;
 672         }
 673         skb_put(skb, CELL_SIZE);
 674         memcpy(skb->data, cell, CELL_SIZE);
 675
 676         reg_desc.dataptr = (unsigned int)skb->data >> 2;
 677         reg_desc.datalen = CELL_SIZE;
 678         reg_desc.byteoff = 0;
 679         reg_desc.iscell  = 1;
 680
 681         reg_desc.own = 1;
 682         reg_desc.c = 1;
 683         reg_desc.sop = reg_desc.eop = 1;
 684
 685         desc_base = get_tx_desc(conn);
 686         if ( desc_base < 0 ) {
 687                 dev_kfree_skb_any(skb);
 688                 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
 689                 g_atm_priv_data.wtx_drop_oam++;
 690                 return -EIO;
 691         }
 692
 693         if ( vcc->stats )
 694                 atomic_inc(&vcc->stats->tx);
 695
 696         /*  update descriptor send pointer  */
 697         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 698                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 699         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 700
 701         /*  write discriptor to memory and write back cache */
 702         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 703         dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
 704
 705         mailbox_signal(conn, 1);
 706
 707         g_atm_priv_data.wtx_oam++;
 708         adsl_led_flash();
 709
 710         return 0;
 711 }
 712
 713 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
 714 {
 715         int conn;
 716
 717         if ( vcc == NULL || qos == NULL )
 718                 return -EINVAL;
 719
 720         conn = find_vcc(vcc);
 721         if ( conn < 0 )
 722                 return -EINVAL;
 723
 724         set_qsb(vcc, qos, conn);
 725
 726         return 0;
 727 }
 728
 729 static inline void adsl_led_flash(void)
 730 {
 731         ifx_mei_atm_led_blink();
 732 }
 733
 734 /*
 735 *  Description:
 736 *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
 737 *  Input:
 738 *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
 739 *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
 740 *    ret  --- ppe_u64_t, pointer to a variable to hold result
 741 *  Output:
 742 *    none
 743 */
 744 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
 745 {
 746         ret->l = opt1.l + opt2;
 747         if ( ret->l < opt1.l || ret->l < opt2 )
 748                 ret->h++;
 749 }
 750
 751 static inline struct sk_buff* alloc_skb_rx(void)
 752 {
 753         struct sk_buff *skb;
 754
 755         skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
 756         if ( skb != NULL ) {
 757                 /*  must be burst length alignment  */
 758                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
 759                         skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
 760                 /*  pub skb in reserved area "skb->data - 4"    */
 761                 *((struct sk_buff **)skb->data - 1) = skb;
 762                 /*  write back and invalidate cache */
 763                 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
 764                 /*  invalidate cache    */
 765 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 766                 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
 767 #else
 768                 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
 769 #endif
 770         }
 771         return skb;
 772 }
 773
 774 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
 775 {
 776         struct sk_buff *skb;
 777
 778         /*  allocate memory including header and padding    */
 779         size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
 780         size &= ~(DATA_BUFFER_ALIGNMENT - 1);
 781         skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
 782         /*  must be burst length alignment  */
 783         if ( skb != NULL )
 784                 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
 785         return skb;
 786 }
 787
 788 struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
 789 {
 790         int conn;
 791         struct sk_buff *skb;
 792
 793         /*  oversize packet */
 794         if ( size > aal5s_max_packet_size ) {
 795                 pr_err("atm_alloc_tx: oversize packet\n");
 796                 return NULL;
 797         }
 798         /*  send buffer overflow    */
 799         if ( sk_wmem_alloc_get(sk_atm(vcc)) && !atm_may_send(vcc, size) ) {
 800                 pr_err("atm_alloc_tx: send buffer overflow\n");
 801                 return NULL;
 802         }
 803         conn = find_vcc(vcc);
 804         if ( conn < 0 ) {
 805                 pr_err("atm_alloc_tx: unknown VCC\n");
 806                 return NULL;
 807         }
 808
 809         skb = dev_alloc_skb(size);
 810         if ( skb == NULL ) {
 811                 pr_err("atm_alloc_tx: sk buffer is used up\n");
 812                 return NULL;
 813         }
 814
 815         atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
 816
 817         return skb;
 818 }
 819
 820 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
 821 {
 822         if ( vcc->pop != NULL )
 823                 vcc->pop(vcc, skb);
 824         else
 825                 dev_kfree_skb_any(skb);
 826 }
 827
 828 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
 829 {
 830         unsigned int skb_dataptr;
 831         struct sk_buff *skb;
 832
 833         skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
 834         skb = *(struct sk_buff **)skb_dataptr;
 835
 836         ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
 837         ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
 838
 839         return skb;
 840 }
 841
 842 static inline int get_tx_desc(unsigned int conn)
 843 {
 844         int desc_base = -1;
 845         struct connection *p_conn = &g_atm_priv_data.conn[conn];
 846
 847         if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
 848                 desc_base = p_conn->tx_desc_pos;
 849                 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
 850                         p_conn->tx_desc_pos = 0;
 851         }
 852
 853         return desc_base;
 854 }
 855
 856 static void free_tx_ring(unsigned int queue)
 857 {
 858         unsigned long flags;
 859         int i;
 860         struct connection *conn = &g_atm_priv_data.conn[queue];
 861         struct sk_buff *skb;
 862
 863         if (!conn)
 864                 return;
 865
 866         spin_lock_irqsave(&conn->lock, flags);
 867
 868         for (i = 0; i < dma_tx_descriptor_length; i++) {
 869                 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
 870                         skb = conn->tx_skb[i];
 871                         conn->tx_skb[i] = NULL;
 872                         atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
 873                 }
 874         }
 875         spin_unlock_irqrestore(&conn->lock, flags);
 876 }
 877
 878 static void mailbox_tx_handler(unsigned int queue_bitmap)
 879 {
 880         int i;
 881         int bit;
 882
 883         /* only get valid queues */
 884         queue_bitmap &= g_atm_priv_data.conn_table;
 885
 886         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
 887                 if (queue_bitmap & bit)
 888                         free_tx_ring(i);
 889         }
 890 }
 891
 892 static inline void mailbox_oam_rx_handler(void)
 893 {
 894         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
 895         struct rx_descriptor reg_desc;
 896         struct uni_cell_header *header;
 897         int conn;
 898         struct atm_vcc *vcc;
 899         unsigned int i;
 900
 901         for ( i = 0; i < vlddes; i++ ) {
 902                 unsigned int loop_count = 0;
 903
 904                 do {
 905                         reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
 906                         if ( ++loop_count == 1000 )
 907                                 break;
 908                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 909                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
 910
 911                 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
 912
 913                 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
 914                         conn = find_vpivci(header->vpi, header->vci);
 915                 else if ( header->vci == 0x03 || header->vci == 0x04 )
 916                         conn = find_vpi(header->vpi);
 917                 else
 918                         conn = -1;
 919
 920                 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
 921                         vcc = g_atm_priv_data.conn[conn].vcc;
 922
 923                         if ( vcc->push_oam != NULL )
 924                                 vcc->push_oam(vcc, header);
 925                         else
 926                                 ifx_push_oam((unsigned char *)header);
 927
 928                         g_atm_priv_data.wrx_oam++;
 929
 930                         adsl_led_flash();
 931                 } else
 932                         g_atm_priv_data.wrx_drop_oam++;
 933
 934                 reg_desc.byteoff = 0;
 935                 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
 936                 reg_desc.own = 1;
 937                 reg_desc.c   = 0;
 938
 939                 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
 940                 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
 941                         g_atm_priv_data.oam_desc_pos = 0;
 942
 943                 dma_cache_inv((unsigned long)header, CELL_SIZE);
 944                 mailbox_signal(RX_DMA_CH_OAM, 0);
 945         }
 946 }
 947
 948 static inline void mailbox_aal_rx_handler(void)
 949 {
 950         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
 951         struct rx_descriptor reg_desc;
 952         int conn;
 953         struct atm_vcc *vcc;
 954         struct sk_buff *skb, *new_skb;
 955         struct rx_inband_trailer *trailer;
 956         unsigned int i;
 957
 958         for ( i = 0; i < vlddes; i++ ) {
 959                 unsigned int loop_count = 0;
 960
 961                 do {
 962                         reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
 963                         if ( ++loop_count == 1000 )
 964                                 break;
 965                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 966                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
 967
 968                 conn = reg_desc.id;
 969
 970                 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
 971                         vcc = g_atm_priv_data.conn[conn].vcc;
 972
 973                         skb = get_skb_rx_pointer(reg_desc.dataptr);
 974
 975                         if ( reg_desc.err ) {
 976                                 if ( vcc->qos.aal == ATM_AAL5 ) {
 977                                         trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
 978                                         if ( trailer->stw_crc )
 979                                                 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
 980                                         if ( trailer->stw_ovz )
 981                                                 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
 982                                         g_atm_priv_data.wrx_drop_pdu++;
 983                                 }
 984                                 if ( vcc->stats ) {
 985                                         atomic_inc(&vcc->stats->rx_drop);
 986                                         atomic_inc(&vcc->stats->rx_err);
 987                                 }
 988                                 reg_desc.err = 0;
 989                         } else if ( atm_charge(vcc, skb->truesize) ) {
 990                                 new_skb = alloc_skb_rx();
 991                                 if ( new_skb != NULL ) {
 992 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 993                                         if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
 994                                                 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
 995 #endif
 996
 997                                         skb_reserve(skb, reg_desc.byteoff);
 998                                         skb_put(skb, reg_desc.datalen);
 999                                         ATM_SKB(skb)->vcc = vcc;
1000
1001                                         vcc->push(vcc, skb);
1002
1003                                         if ( vcc->qos.aal == ATM_AAL5 )
1004                                                 g_atm_priv_data.wrx_pdu++;
1005                                         if ( vcc->stats )
1006                                                 atomic_inc(&vcc->stats->rx);
1007                                         adsl_led_flash();
1008
1009                                         reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
1010                                 } else {
1011                                         atm_return(vcc, skb->truesize);
1012                                         if ( vcc->qos.aal == ATM_AAL5 )
1013                                                 g_atm_priv_data.wrx_drop_pdu++;
1014                                         if ( vcc->stats )
1015                                                 atomic_inc(&vcc->stats->rx_drop);
1016                                 }
1017                         } else {
1018                                 if ( vcc->qos.aal == ATM_AAL5 )
1019                                         g_atm_priv_data.wrx_drop_pdu++;
1020                                 if ( vcc->stats )
1021                                         atomic_inc(&vcc->stats->rx_drop);
1022                         }
1023                 } else {
1024                         g_atm_priv_data.wrx_drop_pdu++;
1025                 }
1026
1027                 reg_desc.byteoff = 0;
1028                 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1029                 reg_desc.own = 1;
1030                 reg_desc.c   = 0;
1031
1032                 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1033                 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1034                         g_atm_priv_data.aal_desc_pos = 0;
1035
1036                 mailbox_signal(RX_DMA_CH_AAL, 0);
1037         }
1038 }
1039
1040 static void do_ppe_tasklet(unsigned long data)
1041 {
1042         unsigned int irqs = *MBOX_IGU1_ISR;
1043         *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1044
1045         if (irqs & (1 << RX_DMA_CH_AAL))
1046                 mailbox_aal_rx_handler();
1047         if (irqs & (1 << RX_DMA_CH_OAM))
1048                 mailbox_oam_rx_handler();
1049
1050         /* any valid tx irqs */
1051         if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1052                 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1053
1054         if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1055                 tasklet_schedule(&g_dma_tasklet);
1056         else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1057                 tasklet_schedule(&g_dma_tasklet);
1058         else
1059                 enable_irq(PPE_MAILBOX_IGU1_INT);
1060 }
1061
1062 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1063 {
1064         if ( !*MBOX_IGU1_ISR )
1065                 return IRQ_HANDLED;
1066
1067         disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1068         tasklet_schedule(&g_dma_tasklet);
1069
1070         return IRQ_HANDLED;
1071 }
1072
1073 static inline void mailbox_signal(unsigned int queue, int is_tx)
1074 {
1075         int count = 1000;
1076
1077         if ( is_tx ) {
1078                 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1079                         count--;
1080                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1081         } else {
1082                 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1083                         count--;
1084                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1085         }
1086
1087         ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1088 }
1089
1090 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1091 {
1092         struct clk *fpi_clk = clk_get_fpi();
1093         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1094         unsigned int qsb_qid = queue + FIRST_QSB_QID;
1095         union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1096         union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1097         unsigned int tmp;
1098
1099
1100         /*
1101          *  Peak Cell Rate (PCR) Limiter
1102          */
1103         if ( qos->txtp.max_pcr == 0 )
1104                 qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
1105         else {
1106                 /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1107                 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1108                 /*  check if overflow takes place   */
1109                 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1110         }
1111
1112 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1113         //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1114         //  Send packets to these two PVCs at same time, it trigger strange behavior.
1115         //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1116         //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1117         //  To work around, create UBR always with max_pcr.
1118         //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1119         if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1120                 int port = g_atm_priv_data.conn[queue].port;
1121                 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1122
1123                 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1124                 if ( tmp > QSB_TP_TS_MAX )
1125                         tmp = QSB_TP_TS_MAX;
1126                 else if ( tmp < 1 )
1127                         tmp = 1;
1128                 qsb_queue_parameter_table.bit.tp = tmp;
1129         }
1130 #endif
1131
1132         /*
1133          *  Weighted Fair Queueing Factor (WFQF)
1134          */
1135         switch ( qos->txtp.traffic_class ) {
1136         case ATM_CBR:
1137         case ATM_VBR_RT:
1138                 /*  real time queue gets weighted fair queueing bypass  */
1139                 qsb_queue_parameter_table.bit.wfqf = 0;
1140                 break;
1141         case ATM_VBR_NRT:
1142         case ATM_UBR_PLUS:
1143                 /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
1144                 /*  WFQF is maximum cell rate / garenteed cell rate                                             */
1145                 /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
1146                 if ( qos->txtp.min_pcr == 0 )
1147                         qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1148                 else {
1149                         tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1150                         if ( tmp == 0 )
1151                                 qsb_queue_parameter_table.bit.wfqf = 1;
1152                         else if ( tmp > QSB_WFQ_NONUBR_MAX )
1153                                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1154                         else
1155                                 qsb_queue_parameter_table.bit.wfqf = tmp;
1156                 }
1157                 break;
1158         default:
1159         case ATM_UBR:
1160                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1161         }
1162
1163         /*
1164          *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1165          */
1166         if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1167 #if 0
1168                 if ( qos->txtp.scr == 0 ) {
1169 #endif
1170                         /*  disable shaper  */
1171                         qsb_queue_vbr_parameter_table.bit.taus = 0;
1172                         qsb_queue_vbr_parameter_table.bit.ts = 0;
1173 #if 0
1174                 } else {
1175                         /*  Cell Loss Priority  (CLP)   */
1176                         if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1177                                 /*  CLP1    */
1178                                 qsb_queue_parameter_table.bit.vbr = 1;
1179                         else
1180                                 /*  CLP0    */
1181                                 qsb_queue_parameter_table.bit.vbr = 0;
1182                         /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1183                         tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1184                         qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1185                         tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1186                         if ( tmp == 0 )
1187                                 qsb_queue_vbr_parameter_table.bit.taus = 1;
1188                         else if ( tmp > QSB_TAUS_MAX )
1189                                 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1190                         else
1191                                 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1192                 }
1193 #endif
1194         } else {
1195                 qsb_queue_vbr_parameter_table.bit.taus = 0;
1196                 qsb_queue_vbr_parameter_table.bit.ts = 0;
1197         }
1198
1199         /*  Queue Parameter Table (QPT) */
1200         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1201         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1202         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1203         /*  Queue VBR Paramter Table (QVPT) */
1204         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1205         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1206         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1207
1208 }
1209
1210 static void qsb_global_set(void)
1211 {
1212         struct clk *fpi_clk = clk_get_fpi();
1213         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1214         int i;
1215         unsigned int tmp1, tmp2, tmp3;
1216
1217         *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1218         *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
1219         *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1220
1221         /*
1222          *  set SCT and SPT per port
1223          */
1224         for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1225                 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1226                         tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1227                         tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
1228                         tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
1229                         /*  carry over to integer part (?)  */
1230                         if ( tmp3 == (1 << 6) ) {
1231                                 tmp3 = 0;
1232                                 tmp2++;
1233                         }
1234                         if ( tmp2 == 0 )
1235                                 tmp2 = tmp3 = 1;
1236                         /*  1. set mask                                 */
1237                         /*  2. write value to data transfer register    */
1238                         /*  3. start the tranfer                        */
1239                         /*  SCT (FracRate)  */
1240                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1241                         *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
1242                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1243                                         QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1244                                         QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1245                                         QSB_RAMAC_TESEL_SET(i & 0x01);
1246                         /*  SPT (SBV + PN + IntRage)    */
1247                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1248                         *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1249                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1250                                 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1251                                 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1252                                 QSB_RAMAC_TESEL_SET(i & 0x01);
1253                 }
1254         }
1255 }
1256
1257 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1258 {
1259         struct htu_entry htu_entry = {
1260                 res1:       0x00,
1261                 clp:        is_retx ? 0x01 : 0x00,
1262                 pid:        g_atm_priv_data.conn[queue].port & 0x01,
1263                 vpi:        vpi,
1264                 vci:        vci,
1265                 pti:        0x00,
1266                 vld:        0x01};
1267
1268         struct htu_mask htu_mask = {
1269                 set:        0x01,
1270                 clp:        0x01,
1271                 pid_mask:   0x02,
1272                 vpi_mask:   0x00,
1273                 vci_mask:   0x0000,
1274                 pti_mask:   0x03,   //  0xx, user data
1275                 clear:      0x00};
1276
1277         struct htu_result htu_result = {
1278                 res1:       0x00,
1279                 cellid:     queue,
1280                 res2:       0x00,
1281                 type:       aal5 ? 0x00 : 0x01,
1282                 ven:        0x01,
1283                 res3:       0x00,
1284                 qid:        queue};
1285
1286         *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1287         *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1288         *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1289 }
1290
1291 static inline void clear_htu_entry(unsigned int queue)
1292 {
1293         HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1294 }
1295
1296 static void validate_oam_htu_entry(void)
1297 {
1298         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1299         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1300         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1301 }
1302
1303 static void invalidate_oam_htu_entry(void)
1304 {
1305         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1306         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1307         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1308 }
1309
1310 static inline int find_vpi(unsigned int vpi)
1311 {
1312         int i;
1313         unsigned int bit;
1314
1315         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1316                 if ( (g_atm_priv_data.conn_table & bit) != 0
1317                                 && g_atm_priv_data.conn[i].vcc != NULL
1318                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1319                         return i;
1320         }
1321
1322         return -1;
1323 }
1324
1325 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1326 {
1327         int i;
1328         unsigned int bit;
1329
1330         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1331                 if ( (g_atm_priv_data.conn_table & bit) != 0
1332                                 && g_atm_priv_data.conn[i].vcc != NULL
1333                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1334                                 && vci == g_atm_priv_data.conn[i].vcc->vci )
1335                         return i;
1336         }
1337
1338         return -1;
1339 }
1340
1341 static inline int find_vcc(struct atm_vcc *vcc)
1342 {
1343         int i;
1344         unsigned int bit;
1345
1346         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1347                 if ( (g_atm_priv_data.conn_table & bit) != 0
1348                         && g_atm_priv_data.conn[i].vcc == vcc )
1349                 return i;
1350         }
1351
1352         return -1;
1353 }
1354
1355 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1356 {
1357         int len = 0;
1358         unsigned int major, minor;
1359
1360         ops->fw_ver(&major, &minor);
1361
1362         len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1363         len += sprintf(buf + len, "    ATM (A1) firmware version %d.%d\n", major, minor);
1364
1365         return len;
1366 }
1367
1368 static inline void check_parameters(void)
1369 {
1370         /*  Please refer to Amazon spec 15.4 for setting these values.  */
1371         if ( qsb_tau < 1 )
1372                 qsb_tau = 1;
1373         if ( qsb_tstep < 1 )
1374                 qsb_tstep = 1;
1375         else if ( qsb_tstep > 4 )
1376                 qsb_tstep = 4;
1377         else if ( qsb_tstep == 3 )
1378                 qsb_tstep = 2;
1379
1380         /*  There is a delay between PPE write descriptor and descriptor is       */
1381         /*  really stored in memory. Host also has this delay when writing        */
1382         /*  descriptor. So PPE will use this value to determine if the write      */
1383         /*  operation makes effect.                                               */
1384         if ( write_descriptor_delay < 0 )
1385                 write_descriptor_delay = 0;
1386
1387         if ( aal5_fill_pattern < 0 )
1388                 aal5_fill_pattern = 0;
1389         else
1390                 aal5_fill_pattern &= 0xFF;
1391
1392         /*  Because of the limitation of length field in descriptors, the packet  */
1393         /*  size could not be larger than 64K minus overhead size.                */
1394         if ( aal5r_max_packet_size < 0 )
1395                 aal5r_max_packet_size = 0;
1396         else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1397                 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1398         if ( aal5r_min_packet_size < 0 )
1399                 aal5r_min_packet_size = 0;
1400         else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1401                 aal5r_min_packet_size = aal5r_max_packet_size;
1402         if ( aal5s_max_packet_size < 0 )
1403                 aal5s_max_packet_size = 0;
1404         else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1405                 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1406         if ( aal5s_min_packet_size < 0 )
1407                 aal5s_min_packet_size = 0;
1408         else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1409                 aal5s_min_packet_size = aal5s_max_packet_size;
1410
1411         if ( dma_rx_descriptor_length < 2 )
1412                 dma_rx_descriptor_length = 2;
1413         if ( dma_tx_descriptor_length < 2 )
1414                 dma_tx_descriptor_length = 2;
1415         if ( dma_rx_clp1_descriptor_threshold < 0 )
1416                 dma_rx_clp1_descriptor_threshold = 0;
1417         else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1418                 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1419
1420         if ( dma_tx_descriptor_length < 2 )
1421                 dma_tx_descriptor_length = 2;
1422 }
1423
1424 static inline int init_priv_data(void)
1425 {
1426         void *p;
1427         int i;
1428         struct rx_descriptor rx_desc = {0};
1429         struct sk_buff *skb;
1430         volatile struct tx_descriptor *p_tx_desc;
1431         struct sk_buff **ppskb;
1432
1433         //  clear atm private data structure
1434         memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1435
1436         //  allocate memory for RX (AAL) descriptors
1437         p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1438         if ( p == NULL )
1439                 return -1;
1440         dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1441         g_atm_priv_data.aal_desc_base = p;
1442         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1443         g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1444
1445         //  allocate memory for RX (OAM) descriptors
1446         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1447         if ( p == NULL )
1448                 return -1;
1449         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1450         g_atm_priv_data.oam_desc_base = p;
1451         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1452         g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1453
1454         //  allocate memory for RX (OAM) buffer
1455         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1456         if ( p == NULL )
1457                 return -1;
1458         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1459         g_atm_priv_data.oam_buf_base = p;
1460         p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1461         g_atm_priv_data.oam_buf = p;
1462
1463         //  allocate memory for TX descriptors
1464         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1465         if ( p == NULL )
1466                 return -1;
1467         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1468         g_atm_priv_data.tx_desc_base = p;
1469
1470         //  allocate memory for TX skb pointers
1471         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1472         if ( p == NULL )
1473                 return -1;
1474         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1475         g_atm_priv_data.tx_skb_base = p;
1476
1477         //  setup RX (AAL) descriptors
1478         rx_desc.own     = 1;
1479         rx_desc.c       = 0;
1480         rx_desc.sop     = 1;
1481         rx_desc.eop     = 1;
1482         rx_desc.byteoff = 0;
1483         rx_desc.id      = 0;
1484         rx_desc.err     = 0;
1485         rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1486         for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1487                 skb = alloc_skb_rx();
1488                 if ( skb == NULL )
1489                         return -1;
1490                 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1491                 g_atm_priv_data.aal_desc[i] = rx_desc;
1492         }
1493
1494         //  setup RX (OAM) descriptors
1495         p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1496         rx_desc.own     = 1;
1497         rx_desc.c       = 0;
1498         rx_desc.sop     = 1;
1499         rx_desc.eop     = 1;
1500         rx_desc.byteoff = 0;
1501         rx_desc.id      = 0;
1502         rx_desc.err     = 0;
1503         rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1504         for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1505                 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1506                 g_atm_priv_data.oam_desc[i] = rx_desc;
1507                 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1508         }
1509
1510         //  setup TX descriptors and skb pointers
1511         p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1512         ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1513         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1514                 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1515                 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1516                 g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
1517         }
1518
1519         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1520                 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1521
1522         return 0;
1523 }
1524
1525 static inline void clear_priv_data(void)
1526 {
1527         int i, j;
1528         struct sk_buff *skb;
1529
1530         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1531                 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1532                         for ( j = 0; j < dma_tx_descriptor_length; j++ )
1533                                 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1534                                         dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1535                 }
1536         }
1537
1538         if ( g_atm_priv_data.tx_skb_base != NULL )
1539                 kfree(g_atm_priv_data.tx_skb_base);
1540
1541         if ( g_atm_priv_data.tx_desc_base != NULL )
1542                 kfree(g_atm_priv_data.tx_desc_base);
1543
1544         if ( g_atm_priv_data.oam_buf_base != NULL )
1545                 kfree(g_atm_priv_data.oam_buf_base);
1546
1547         if ( g_atm_priv_data.oam_desc_base != NULL )
1548                 kfree(g_atm_priv_data.oam_desc_base);
1549
1550         if ( g_atm_priv_data.aal_desc_base != NULL ) {
1551                 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1552                         if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
1553                                 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1554                                 dev_kfree_skb_any(skb);
1555                         }
1556                 }
1557                 kfree(g_atm_priv_data.aal_desc_base);
1558         }
1559 }
1560
1561 static inline void init_rx_tables(void)
1562 {
1563         int i;
1564         struct wrx_queue_config wrx_queue_config = {0};
1565         struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1566         struct htu_entry htu_entry = {0};
1567         struct htu_result htu_result = {0};
1568         struct htu_mask htu_mask = {
1569                 set:        0x01,
1570                 clp:        0x01,
1571                 pid_mask:   0x00,
1572                 vpi_mask:   0x00,
1573                 vci_mask:   0x00,
1574                 pti_mask:   0x00,
1575                 clear:      0x00
1576         };
1577
1578         /*
1579          *  General Registers
1580          */
1581         *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1582 #ifndef CONFIG_AMAZON_SE
1583         *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
1584 #endif
1585         *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1586         *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
1587         *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1588
1589         /*
1590          *  WRX Queue Configuration Table
1591          */
1592         wrx_queue_config.uumask    = 0xFF;
1593         wrx_queue_config.cpimask   = 0xFF;
1594         wrx_queue_config.uuexp     = 0;
1595         wrx_queue_config.cpiexp    = 0;
1596         wrx_queue_config.mfs       = aal5r_max_packet_size;
1597         wrx_queue_config.oversize  = aal5r_max_packet_size;
1598         wrx_queue_config.undersize = aal5r_min_packet_size;
1599         wrx_queue_config.errdp     = aal5r_drop_error_packet;
1600         wrx_queue_config.dmach     = RX_DMA_CH_AAL;
1601         for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1602                 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1603         WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1604
1605         /*
1606          *  WRX DMA Channel Configuration Table
1607          */
1608         wrx_dma_channel_config.chrl   = 0;
1609         wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1610         wrx_dma_channel_config.mode   = 0;
1611         wrx_dma_channel_config.rlcfg  = 0;
1612
1613         wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1614         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1615         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1616
1617         wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1618         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1619         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1620
1621         /*
1622          *  HTU Tables
1623          */
1624         for (i = 0; i < MAX_PVC_NUMBER; i++) {
1625                 htu_result.qid = (unsigned int)i;
1626
1627                 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1628                 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1629                 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1630         }
1631
1632         /*  OAM HTU Entry   */
1633         htu_entry.vci = 0x03;
1634         htu_mask.pid_mask = 0x03;
1635         htu_mask.vpi_mask = 0xFF;
1636         htu_mask.vci_mask = 0x0000;
1637         htu_mask.pti_mask = 0x07;
1638         htu_result.cellid = OAM_RX_QUEUE;
1639         htu_result.type   = 1;
1640         htu_result.ven    = 1;
1641         htu_result.qid    = OAM_RX_QUEUE;
1642         *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1643         *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
1644         *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
1645         htu_entry.vci     = 0x04;
1646         htu_result.cellid = OAM_RX_QUEUE;
1647         htu_result.type   = 1;
1648         htu_result.ven    = 1;
1649         htu_result.qid    = OAM_RX_QUEUE;
1650         *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1651         *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
1652         *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
1653         htu_entry.vci     = 0x00;
1654         htu_entry.pti     = 0x04;
1655         htu_mask.vci_mask = 0xFFFF;
1656         htu_mask.pti_mask = 0x01;
1657         htu_result.cellid = OAM_RX_QUEUE;
1658         htu_result.type   = 1;
1659         htu_result.ven    = 1;
1660         htu_result.qid    = OAM_RX_QUEUE;
1661         *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1662         *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
1663         *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
1664 }
1665
1666 static inline void init_tx_tables(void)
1667 {
1668         int i;
1669         struct wtx_queue_config wtx_queue_config = {0};
1670         struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1671         struct wtx_port_config wtx_port_config = {
1672                 res1:   0,
1673                 qid:    0,
1674                 qsben:  1
1675         };
1676
1677         /*
1678          *  General Registers
1679          */
1680         *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
1681         *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1682         *CFG_WRDES_DELAY    = write_descriptor_delay;
1683
1684         /*
1685          *  WTX Port Configuration Table
1686          */
1687         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1688                 *WTX_PORT_CONFIG(i) = wtx_port_config;
1689
1690         /*
1691          *  WTX Queue Configuration Table
1692          */
1693         wtx_queue_config.qsben = 1;
1694         wtx_queue_config.sbid  = 0;
1695         for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1696                 wtx_queue_config.qsb_vcid = i;
1697                 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1698         }
1699
1700         /*
1701          *  WTX DMA Channel Configuration Table
1702          */
1703         wtx_dma_channel_config.mode   = 0;
1704         wtx_dma_channel_config.deslen = 0;
1705         wtx_dma_channel_config.desba  = 0;
1706         for ( i = 0; i < FIRST_QSB_QID; i++ )
1707                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1708         /*  normal connection   */
1709         wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1710         for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1711                 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1712                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1713         }
1714 }
1715
1716 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1717 {
1718         int i, j, port_num;
1719
1720         ASSERT(port_cell != NULL, "port_cell is NULL");
1721         ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1722
1723         for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1724                 if ( port_cell->tx_link_rate[j] > 0 )
1725                         break;
1726         for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1727                 g_atm_priv_data.port[i].tx_max_cell_rate =
1728                         port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1729
1730         qsb_global_set();
1731
1732         for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1733                 if ( g_atm_priv_data.conn[i].vcc != NULL )
1734                         set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1735
1736         //  TODO: ReTX set xdata_addr
1737         g_xdata_addr = xdata_addr;
1738
1739         g_showtime = 1;
1740
1741         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1742                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1743
1744 #if defined(CONFIG_VR9)
1745         IFX_REG_W32(0x0F, UTP_CFG);
1746 #endif
1747
1748         printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1749                 g_atm_priv_data.port[0].tx_max_cell_rate,
1750                 g_atm_priv_data.port[1].tx_max_cell_rate,
1751                 (unsigned int)g_xdata_addr);
1752
1753         return 0;
1754 }
1755
1756 static int atm_showtime_exit(void)
1757 {
1758         int port_num;
1759
1760         if ( !g_showtime )
1761                 return -1;
1762
1763 #if defined(CONFIG_VR9)
1764         IFX_REG_W32(0x00, UTP_CFG);
1765 #endif
1766
1767         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1768                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1769
1770         g_showtime = 0;
1771         g_xdata_addr = NULL;
1772         printk("leave showtime\n");
1773         return 0;
1774 }
1775
1776 extern struct ltq_atm_ops ar9_ops;
1777 extern struct ltq_atm_ops vr9_ops;
1778 extern struct ltq_atm_ops danube_ops;
1779 extern struct ltq_atm_ops ase_ops;
1780
1781 static const struct of_device_id ltq_atm_match[] = {
1782 #ifdef CONFIG_DANUBE
1783         { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1784 #elif defined CONFIG_AMAZON_SE
1785         { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1786 #elif defined CONFIG_AR9
1787         { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1788 #elif defined CONFIG_VR9
1789         { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1790 #endif
1791         {},
1792 };
1793 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1794
1795 static int ltq_atm_probe(struct platform_device *pdev)
1796 {
1797         const struct of_device_id *match;
1798         struct ltq_atm_ops *ops = NULL;
1799         int ret;
1800         int port_num;
1801         struct port_cell_info port_cell = {0};
1802         char ver_str[256];
1803
1804         match = of_match_device(ltq_atm_match, &pdev->dev);
1805         if (!match) {
1806                 dev_err(&pdev->dev, "failed to find matching device\n");
1807                 return -ENOENT;
1808         }
1809         ops = (struct ltq_atm_ops *) match->data;
1810
1811         check_parameters();
1812
1813         ret = init_priv_data();
1814         if ( ret != 0 ) {
1815                 pr_err("INIT_PRIV_DATA_FAIL\n");
1816                 goto INIT_PRIV_DATA_FAIL;
1817         }
1818
1819         ops->init();
1820         init_rx_tables();
1821         init_tx_tables();
1822
1823         /*  create devices  */
1824         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1825                 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1826                 if ( !g_atm_priv_data.port[port_num].dev ) {
1827                         pr_err("failed to register atm device %d!\n", port_num);
1828                         ret = -EIO;
1829                         goto ATM_DEV_REGISTER_FAIL;
1830                 } else {
1831                         g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1832                         g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1833                         g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1834                         g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1835
1836 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1837                         atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1838 #endif
1839                 }
1840         }
1841
1842         /*  register interrupt handler  */
1843 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1844         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1845 #else
1846         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1847 #endif
1848         if ( ret ) {
1849                 if ( ret == -EBUSY ) {
1850                         pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1851                 } else {
1852                         pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1853                 }
1854                 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1855         }
1856         disable_irq(PPE_MAILBOX_IGU1_INT);
1857
1858
1859         ret = ops->start(0);
1860         if ( ret ) {
1861                 pr_err("ifx_pp32_start fail!\n");
1862                 goto PP32_START_FAIL;
1863         }
1864
1865         port_cell.port_num = ATM_PORT_NUMBER;
1866         ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1867         if ( g_showtime ) {
1868                 atm_showtime_enter(&port_cell, &g_xdata_addr);
1869         } else {
1870                 qsb_global_set();
1871         }
1872
1873         validate_oam_htu_entry();
1874
1875         ifx_mei_atm_showtime_enter = atm_showtime_enter;
1876         ifx_mei_atm_showtime_exit  = atm_showtime_exit;
1877
1878         ifx_atm_version(ops, ver_str);
1879         printk(KERN_INFO "%s", ver_str);
1880         platform_set_drvdata(pdev, ops);
1881         printk("ifxmips_atm: ATM init succeed\n");
1882
1883         return 0;
1884
1885 PP32_START_FAIL:
1886         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1887 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1888 ATM_DEV_REGISTER_FAIL:
1889         while ( port_num-- > 0 )
1890                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1891 INIT_PRIV_DATA_FAIL:
1892         clear_priv_data();
1893         printk("ifxmips_atm: ATM init failed\n");
1894         return ret;
1895 }
1896
1897 static int ltq_atm_remove(struct platform_device *pdev)
1898 {
1899         int port_num;
1900         struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1901
1902         ifx_mei_atm_showtime_enter = NULL;
1903         ifx_mei_atm_showtime_exit  = NULL;
1904
1905         invalidate_oam_htu_entry();
1906
1907         ops->stop(0);
1908
1909         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1910
1911         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1912                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1913
1914         ops->shutdown();
1915
1916         clear_priv_data();
1917
1918         return 0;
1919 }
1920
1921 static struct platform_driver ltq_atm_driver = {
1922         .probe = ltq_atm_probe,
1923         .remove = ltq_atm_remove,
1924         .driver = {
1925                 .name = "atm",
1926                 .owner = THIS_MODULE,
1927                 .of_match_table = ltq_atm_match,
1928         },
1929 };
1930
1931 module_platform_driver(ltq_atm_driver);
1932
1933 MODULE_LICENSE("Dual BSD/GPL");