package/kernel/lantiq/ltq-atm/src/ltq_atm.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 **
  23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
  24 *******************************************************************************/
  25
  26 #define IFX_ATM_VER_MAJOR               1
  27 #define IFX_ATM_VER_MID                 0
  28 #define IFX_ATM_VER_MINOR               26
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/version.h>
  33 #include <linux/types.h>
  34 #include <linux/errno.h>
  35 #include <linux/proc_fs.h>
  36 #include <linux/init.h>
  37 #include <linux/ioctl.h>
  38 #include <linux/atmdev.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/of_device.h>
  41 #include <linux/atm.h>
  42 #include <linux/clk.h>
  43 #include <linux/interrupt.h>
  44 #ifdef CONFIG_XFRM
  45   #include <net/xfrm.h>
  46 #endif
  47
  48 #include <lantiq_soc.h>
  49
  50 #include "ifxmips_atm_core.h"
  51
  52 #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
  53 #define MODULE_PARM(a, b)         module_param(a, int, 0)
  54
  55 /*!
  56   \brief QSB cell delay variation due to concurrency
  57  */
  58 static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
  59 /*!
  60   \brief QSB scheduler burst length
  61  */
  62 static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
  63 /*!
  64   \brief QSB time step, all legal values are 1, 2, 4
  65  */
  66 static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
  67
  68 /*!
  69   \brief Write descriptor delay
  70  */
  71 static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
  72
  73 /*!
  74   \brief AAL5 padding byte ('~')
  75  */
  76 static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
  77 /*!
  78   \brief Max frame size for RX
  79  */
  80 static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
  81 /*!
  82   \brief Min frame size for RX
  83  */
  84 static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
  85 /*!
  86   \brief Max frame size for TX
  87  */
  88 static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
  89 /*!
  90   \brief Min frame size for TX
  91  */
  92 static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
  93 /*!
  94   \brief Drop error packet in RX path
  95  */
  96 static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
  97
  98 /*!
  99   \brief Number of descriptors per DMA RX channel
 100  */
 101 static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
 102 /*!
 103   \brief Number of descriptors per DMA TX channel
 104  */
 105 static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
 106 /*!
 107   \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
 108  */
 109 static int dma_rx_clp1_descriptor_threshold = 38;
 110 /*@}*/
 111
 112 MODULE_PARM(qsb_tau, "i");
 113 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
 114 MODULE_PARM(qsb_srvm, "i");
 115 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
 116 MODULE_PARM(qsb_tstep, "i");
 117 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
 118
 119 MODULE_PARM(write_descriptor_delay, "i");
 120 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
 121
 122 MODULE_PARM(aal5_fill_pattern, "i");
 123 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
 124 MODULE_PARM(aal5r_max_packet_size, "i");
 125 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
 126 MODULE_PARM(aal5r_min_packet_size, "i");
 127 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
 128 MODULE_PARM(aal5s_max_packet_size, "i");
 129 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
 130 MODULE_PARM(aal5s_min_packet_size, "i");
 131 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
 132 MODULE_PARM(aal5r_drop_error_packet, "i");
 133 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
 134
 135 MODULE_PARM(dma_rx_descriptor_length, "i");
 136 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
 137 MODULE_PARM(dma_tx_descriptor_length, "i");
 138 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
 139 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
 140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
 141
 142
 143
 144 /*
 145  * ####################################
 146  *              Definition
 147  * ####################################
 148  */
 149
 150 #ifdef CONFIG_AMAZON_SE
 151   #define ENABLE_LESS_CACHE_INV                 1
 152   #define LESS_CACHE_INV_LEN                    96
 153 #endif
 154
 155 #define DUMP_SKB_LEN                            ~0
 156
 157
 158
 159 /*
 160  * ####################################
 161  *             Declaration
 162  * ####################################
 163  */
 164
 165 /*
 166  *  Network Operations
 167  */
 168 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
 169 static int ppe_open(struct atm_vcc *);
 170 static void ppe_close(struct atm_vcc *);
 171 static int ppe_send(struct atm_vcc *, struct sk_buff *);
 172 static int ppe_send_oam(struct atm_vcc *, void *, int);
 173 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
 174
 175 /*
 176  *  ADSL LED
 177  */
 178 static inline void adsl_led_flash(void);
 179
 180 /*
 181  *  64-bit operation used by MIB calculation
 182  */
 183 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
 184
 185 /*
 186  *  buffer manage functions
 187  */
 188 static inline struct sk_buff* alloc_skb_rx(void);
 189 static inline struct sk_buff* alloc_skb_tx(unsigned int);
 190 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
 191 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
 192 static inline int get_tx_desc(unsigned int);
 193
 194 /*
 195  *  mailbox handler and signal function
 196  */
 197 static inline void mailbox_oam_rx_handler(void);
 198 static inline void mailbox_aal_rx_handler(void);
 199 static irqreturn_t mailbox_irq_handler(int, void *);
 200 static inline void mailbox_signal(unsigned int, int);
 201 static void do_ppe_tasklet(unsigned long);
 202 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
 203
 204 /*
 205  *  QSB & HTU setting functions
 206  */
 207 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
 208 static void qsb_global_set(void);
 209 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
 210 static inline void clear_htu_entry(unsigned int);
 211 static void validate_oam_htu_entry(void);
 212 static void invalidate_oam_htu_entry(void);
 213
 214 /*
 215  *  look up for connection ID
 216  */
 217 static inline int find_vpi(unsigned int);
 218 static inline int find_vpivci(unsigned int, unsigned int);
 219 static inline int find_vcc(struct atm_vcc *);
 220
 221 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
 222
 223 /*
 224  *  Init & clean-up functions
 225  */
 226 static inline void check_parameters(void);
 227 static inline int init_priv_data(void);
 228 static inline void clear_priv_data(void);
 229 static inline void init_rx_tables(void);
 230 static inline void init_tx_tables(void);
 231
 232 /*
 233  *  Exteranl Function
 234  */
 235 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
 236 extern void ifx_push_oam(unsigned char *);
 237 #else
 238 static inline void ifx_push_oam(unsigned char *dummy) {}
 239 #endif
 240
 241 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
 242 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
 243 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
 244
 245 extern int (*ifx_mei_atm_showtime_exit)(void);
 246 extern int ifx_mei_atm_led_blink(void);
 247 #else
 248 static inline int ifx_mei_atm_led_blink(void) { return 0; }
 249 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
 250 {
 251         if ( is_showtime != NULL )
 252                 *is_showtime = 0;
 253         return 0;
 254 }
 255 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
 256 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
 257
 258 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
 259 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
 260
 261 #endif
 262
 263 static struct atm_priv_data g_atm_priv_data;
 264
 265 static struct atmdev_ops g_ifx_atm_ops = {
 266         .open = ppe_open,
 267         .close = ppe_close,
 268         .ioctl = ppe_ioctl,
 269         .send = ppe_send,
 270         .send_oam = ppe_send_oam,
 271         .change_qos = ppe_change_qos,
 272         .owner = THIS_MODULE,
 273 };
 274
 275 static int g_showtime = 0;
 276 static void *g_xdata_addr = NULL;
 277
 278 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
 279 {
 280         int ret = 0;
 281         atm_cell_ifEntry_t mib_cell;
 282         atm_aal5_ifEntry_t mib_aal5;
 283         atm_aal5_vcc_x_t mib_vcc;
 284         unsigned int value;
 285         int conn;
 286
 287         if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
 288                         || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
 289                 return -ENOTTY;
 290
 291         if ( _IOC_DIR(cmd) & _IOC_READ )
 292                 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 293         else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 294                 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 295         if ( ret )
 296                 return -EFAULT;
 297
 298         switch (cmd) {
 299         case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
 300                 /*  These MIB should be read at ARC side, now put zero only.    */
 301                 mib_cell.ifHCInOctets_h = 0;
 302                 mib_cell.ifHCInOctets_l = 0;
 303                 mib_cell.ifHCOutOctets_h = 0;
 304                 mib_cell.ifHCOutOctets_l = 0;
 305                 mib_cell.ifInErrors = 0;
 306                 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
 307                 mib_cell.ifOutErrors = 0;
 308
 309                 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
 310                 break;
 311
 312         case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
 313                 value = WAN_MIB_TABLE->wrx_total_byte;
 314                 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
 315                 g_atm_priv_data.prev_wrx_total_byte = value;
 316                 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
 317                 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
 318
 319                 value = WAN_MIB_TABLE->wtx_total_byte;
 320                 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
 321                 g_atm_priv_data.prev_wtx_total_byte = value;
 322                 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
 323                 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
 324
 325                 mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
 326                 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
 327                 mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
 328                 mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
 329                 mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
 330                 mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
 331
 332                 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
 333                 break;
 334
 335         case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
 336                 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
 337                 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
 338                 if (conn >= 0) {
 339                         mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
 340                         mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
 341                         mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
 342                         ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
 343                 } else
 344                         ret = -EINVAL;
 345                 break;
 346
 347         default:
 348                 ret = -ENOIOCTLCMD;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static int ppe_open(struct atm_vcc *vcc)
 355 {
 356         int ret;
 357         short vpi = vcc->vpi;
 358         int   vci = vcc->vci;
 359         struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
 360         int conn;
 361         int f_enable_irq = 0;
 362
 363         if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
 364                 return -EPROTONOSUPPORT;
 365
 366 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
 367         /*  check bandwidth */
 368         if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 369                 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 370 #if 0
 371                 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 372 #endif
 373                 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
 374         {
 375                 ret = -EINVAL;
 376                 goto PPE_OPEN_EXIT;
 377         }
 378 #endif
 379
 380         /*  check existing vpi,vci  */
 381         conn = find_vpivci(vpi, vci);
 382         if ( conn >= 0 ) {
 383                 ret = -EADDRINUSE;
 384                 goto PPE_OPEN_EXIT;
 385         }
 386
 387         /*  check whether it need to enable irq */
 388         if ( g_atm_priv_data.conn_table == 0 )
 389                 f_enable_irq = 1;
 390
 391         /*  allocate connection */
 392         for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
 393                 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
 394                         g_atm_priv_data.conn[conn].vcc = vcc;
 395                         break;
 396                 }
 397         }
 398         if ( conn == MAX_PVC_NUMBER ) {
 399                 ret = -EINVAL;
 400                 goto PPE_OPEN_EXIT;
 401         }
 402
 403         /*  reserve bandwidth   */
 404         switch ( vcc->qos.txtp.traffic_class ) {
 405         case ATM_CBR:
 406         case ATM_VBR_RT:
 407                 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
 408                 break;
 409         case ATM_VBR_NRT:
 410 #if 0
 411                 port->tx_current_cell_rate += vcc->qos.txtp.scr;
 412 #endif
 413                 break;
 414         case ATM_UBR_PLUS:
 415                 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
 416                 break;
 417         }
 418
 419         /*  set qsb */
 420         set_qsb(vcc, &vcc->qos, conn);
 421
 422         /*  update atm_vcc structure    */
 423         vcc->itf = (int)vcc->dev->dev_data;
 424         vcc->vpi = vpi;
 425         vcc->vci = vci;
 426         set_bit(ATM_VF_READY, &vcc->flags);
 427
 428         /*  enable irq  */
 429         if ( f_enable_irq ) {
 430                 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 431                 *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 432
 433                 enable_irq(PPE_MAILBOX_IGU1_INT);
 434         }
 435
 436         /*  set port    */
 437         WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
 438
 439         /*  set htu entry   */
 440         set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
 441
 442         *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
 443         *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
 444
 445         ret = 0;
 446
 447 PPE_OPEN_EXIT:
 448         return ret;
 449 }
 450
 451 static void ppe_close(struct atm_vcc *vcc)
 452 {
 453         int conn;
 454         struct port *port;
 455         struct connection *connection;
 456         if ( vcc == NULL )
 457                 return;
 458
 459         /*  get connection id   */
 460         conn = find_vcc(vcc);
 461         if ( conn < 0 ) {
 462                 pr_err("can't find vcc\n");
 463                 goto PPE_CLOSE_EXIT;
 464         }
 465         connection = &g_atm_priv_data.conn[conn];
 466         port = &g_atm_priv_data.port[connection->port];
 467
 468         /*  clear htu   */
 469         clear_htu_entry(conn);
 470
 471         /*  release connection  */
 472         connection->vcc = NULL;
 473         connection->aal5_vcc_crc_err = 0;
 474         connection->aal5_vcc_oversize_sdu = 0;
 475         clear_bit(conn, &g_atm_priv_data.conn_table);
 476
 477         /*  disable irq */
 478         if ( g_atm_priv_data.conn_table == 0 )
 479                 disable_irq(PPE_MAILBOX_IGU1_INT);
 480
 481         /*  release bandwidth   */
 482         switch ( vcc->qos.txtp.traffic_class )
 483         {
 484         case ATM_CBR:
 485         case ATM_VBR_RT:
 486                 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
 487                 break;
 488         case ATM_VBR_NRT:
 489 #if 0
 490                 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
 491 #endif
 492                 break;
 493         case ATM_UBR_PLUS:
 494                 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
 495                 break;
 496         }
 497
 498         /* wait for incoming packets to be processed by upper layers */
 499         tasklet_unlock_wait(&g_dma_tasklet);
 500
 501 PPE_CLOSE_EXIT:
 502         return;
 503 }
 504
 505 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
 506 {
 507         int ret;
 508         int conn;
 509         int desc_base;
 510         int byteoff;
 511         int required;
 512         /* the len of the data without offset and header */
 513         int datalen;
 514         unsigned long flags;
 515         struct tx_descriptor reg_desc = {0};
 516         struct tx_inband_header *header;
 517
 518         if ( vcc == NULL || skb == NULL )
 519                 return -EINVAL;
 520
 521
 522         conn = find_vcc(vcc);
 523         if ( conn < 0 ) {
 524                 ret = -EINVAL;
 525                 goto FIND_VCC_FAIL;
 526         }
 527
 528         if ( !g_showtime ) {
 529                 pr_debug("not in showtime\n");
 530                 ret = -EIO;
 531                 goto PPE_SEND_FAIL;
 532         }
 533
 534         byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 535         required = sizeof(*header) + byteoff;
 536         if (!skb_clone_writable(skb, required)) {
 537                 int expand_by = 0;
 538                 int ret;
 539
 540                 if (skb_headroom(skb) < required)
 541                         expand_by = required - skb_headroom(skb);
 542
 543                 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
 544                 if (ret) {
 545                         printk("pskb_expand_head failed.\n");
 546                         atm_free_tx_skb_vcc(skb, vcc);
 547                         return ret;
 548                 }
 549         }
 550
 551         datalen = skb->len;
 552         header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
 553
 554
 555         if ( vcc->qos.aal == ATM_AAL5 ) {
 556                 /*  setup inband trailer    */
 557                 header->uu   = 0;
 558                 header->cpi  = 0;
 559                 header->pad  = aal5_fill_pattern;
 560                 header->res1 = 0;
 561
 562                 /*  setup cell header   */
 563                 header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
 564                 header->pti  = ATM_PTI_US0;
 565                 header->vci  = vcc->vci;
 566                 header->vpi  = vcc->vpi;
 567                 header->gfc  = 0;
 568
 569                 /*  setup descriptor    */
 570                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 571                 reg_desc.datalen = datalen;
 572                 reg_desc.byteoff = byteoff;
 573                 reg_desc.iscell  = 0;
 574         } else {
 575                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 576                 reg_desc.datalen = skb->len;
 577                 reg_desc.byteoff = byteoff;
 578                 reg_desc.iscell  = 1;
 579         }
 580
 581         reg_desc.own = 1;
 582         reg_desc.c = 1;
 583         reg_desc.sop = reg_desc.eop = 1;
 584
 585         spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
 586         desc_base = get_tx_desc(conn);
 587         if ( desc_base < 0 ) {
 588                 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 589                 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
 590                 ret = -EIO;
 591                 goto PPE_SEND_FAIL;
 592         }
 593         /*  update descriptor send pointer  */
 594         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 595                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 596         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 597
 598         spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 599
 600         if ( vcc->stats )
 601                 atomic_inc(&vcc->stats->tx);
 602         if ( vcc->qos.aal == ATM_AAL5 )
 603                 g_atm_priv_data.wtx_pdu++;
 604         /*  write discriptor to memory and write back cache */
 605         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 606         dma_cache_wback((unsigned long)skb->data, skb->len);
 607
 608         mailbox_signal(conn, 1);
 609
 610         adsl_led_flash();
 611
 612         return 0;
 613
 614 FIND_VCC_FAIL:
 615         pr_err("FIND_VCC_FAIL\n");
 616         g_atm_priv_data.wtx_err_pdu++;
 617         dev_kfree_skb_any(skb);
 618         return ret;
 619
 620 PPE_SEND_FAIL:
 621         if ( vcc->qos.aal == ATM_AAL5 )
 622                 g_atm_priv_data.wtx_drop_pdu++;
 623         if ( vcc->stats )
 624                 atomic_inc(&vcc->stats->tx_err);
 625         dev_kfree_skb_any(skb);
 626         return ret;
 627 }
 628
 629 /* operation and maintainance */
 630 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
 631 {
 632         int conn;
 633         struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
 634         int desc_base;
 635         struct sk_buff *skb;
 636         struct tx_descriptor reg_desc = {0};
 637
 638         if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
 639                         && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
 640                         || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
 641                         && find_vpi(uni_cell_header->vpi) < 0) )
 642         {
 643                 g_atm_priv_data.wtx_err_oam++;
 644                 return -EINVAL;
 645         }
 646
 647         if ( !g_showtime ) {
 648                 pr_err("not in showtime\n");
 649                 g_atm_priv_data.wtx_drop_oam++;
 650                 return -EIO;
 651         }
 652
 653         conn = find_vcc(vcc);
 654         if ( conn < 0 ) {
 655                 pr_err("FIND_VCC_FAIL\n");
 656                 g_atm_priv_data.wtx_drop_oam++;
 657                 return -EINVAL;
 658         }
 659
 660         skb = alloc_skb_tx(CELL_SIZE);
 661         if ( skb == NULL ) {
 662                 pr_err("ALLOC_SKB_TX_FAIL\n");
 663                 g_atm_priv_data.wtx_drop_oam++;
 664                 return -ENOMEM;
 665         }
 666         skb_put(skb, CELL_SIZE);
 667         memcpy(skb->data, cell, CELL_SIZE);
 668
 669         reg_desc.dataptr = (unsigned int)skb->data >> 2;
 670         reg_desc.datalen = CELL_SIZE;
 671         reg_desc.byteoff = 0;
 672         reg_desc.iscell  = 1;
 673
 674         reg_desc.own = 1;
 675         reg_desc.c = 1;
 676         reg_desc.sop = reg_desc.eop = 1;
 677
 678         desc_base = get_tx_desc(conn);
 679         if ( desc_base < 0 ) {
 680                 dev_kfree_skb_any(skb);
 681                 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
 682                 g_atm_priv_data.wtx_drop_oam++;
 683                 return -EIO;
 684         }
 685
 686         if ( vcc->stats )
 687                 atomic_inc(&vcc->stats->tx);
 688
 689         /*  update descriptor send pointer  */
 690         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 691                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 692         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 693
 694         /*  write discriptor to memory and write back cache */
 695         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 696         dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
 697
 698         mailbox_signal(conn, 1);
 699
 700         g_atm_priv_data.wtx_oam++;
 701         adsl_led_flash();
 702
 703         return 0;
 704 }
 705
 706 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
 707 {
 708         int conn;
 709
 710         if ( vcc == NULL || qos == NULL )
 711                 return -EINVAL;
 712
 713         conn = find_vcc(vcc);
 714         if ( conn < 0 )
 715                 return -EINVAL;
 716
 717         set_qsb(vcc, qos, conn);
 718
 719         return 0;
 720 }
 721
 722 static inline void adsl_led_flash(void)
 723 {
 724         ifx_mei_atm_led_blink();
 725 }
 726
 727 /*
 728 *  Description:
 729 *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
 730 *  Input:
 731 *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
 732 *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
 733 *    ret  --- ppe_u64_t, pointer to a variable to hold result
 734 *  Output:
 735 *    none
 736 */
 737 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
 738 {
 739         ret->l = opt1.l + opt2;
 740         if ( ret->l < opt1.l || ret->l < opt2 )
 741                 ret->h++;
 742 }
 743
 744 static inline struct sk_buff* alloc_skb_rx(void)
 745 {
 746         struct sk_buff *skb;
 747
 748         skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
 749         if ( skb != NULL ) {
 750                 /*  must be burst length alignment  */
 751                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
 752                         skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
 753                 /*  pub skb in reserved area "skb->data - 4"    */
 754                 *((struct sk_buff **)skb->data - 1) = skb;
 755                 /*  write back and invalidate cache */
 756                 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
 757                 /*  invalidate cache    */
 758 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 759                 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
 760 #else
 761                 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
 762 #endif
 763         }
 764         return skb;
 765 }
 766
 767 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
 768 {
 769         struct sk_buff *skb;
 770
 771         /*  allocate memory including header and padding    */
 772         size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
 773         size &= ~(DATA_BUFFER_ALIGNMENT - 1);
 774         skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
 775         /*  must be burst length alignment  */
 776         if ( skb != NULL )
 777                 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
 778         return skb;
 779 }
 780
 781 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
 782 {
 783         if ( vcc->pop != NULL )
 784                 vcc->pop(vcc, skb);
 785         else
 786                 dev_kfree_skb_any(skb);
 787 }
 788
 789 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
 790 {
 791         unsigned int skb_dataptr;
 792         struct sk_buff *skb;
 793
 794         skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
 795         skb = *(struct sk_buff **)skb_dataptr;
 796
 797         ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
 798         ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
 799
 800         return skb;
 801 }
 802
 803 static inline int get_tx_desc(unsigned int conn)
 804 {
 805         int desc_base = -1;
 806         struct connection *p_conn = &g_atm_priv_data.conn[conn];
 807
 808         if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
 809                 desc_base = p_conn->tx_desc_pos;
 810                 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
 811                         p_conn->tx_desc_pos = 0;
 812         }
 813
 814         return desc_base;
 815 }
 816
 817 static void free_tx_ring(unsigned int queue)
 818 {
 819         unsigned long flags;
 820         int i;
 821         struct connection *conn = &g_atm_priv_data.conn[queue];
 822         struct sk_buff *skb;
 823
 824         if (!conn)
 825                 return;
 826
 827         spin_lock_irqsave(&conn->lock, flags);
 828
 829         for (i = 0; i < dma_tx_descriptor_length; i++) {
 830                 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
 831                         skb = conn->tx_skb[i];
 832                         conn->tx_skb[i] = NULL;
 833                         atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
 834                 }
 835         }
 836         spin_unlock_irqrestore(&conn->lock, flags);
 837 }
 838
 839 static void mailbox_tx_handler(unsigned int queue_bitmap)
 840 {
 841         int i;
 842         int bit;
 843
 844         /* only get valid queues */
 845         queue_bitmap &= g_atm_priv_data.conn_table;
 846
 847         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
 848                 if (queue_bitmap & bit)
 849                         free_tx_ring(i);
 850         }
 851 }
 852
 853 static inline void mailbox_oam_rx_handler(void)
 854 {
 855         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
 856         struct rx_descriptor reg_desc;
 857         struct uni_cell_header *header;
 858         int conn;
 859         struct atm_vcc *vcc;
 860         unsigned int i;
 861
 862         for ( i = 0; i < vlddes; i++ ) {
 863                 unsigned int loop_count = 0;
 864
 865                 do {
 866                         reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
 867                         if ( ++loop_count == 1000 )
 868                                 break;
 869                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 870                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
 871
 872                 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
 873
 874                 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
 875                         conn = find_vpivci(header->vpi, header->vci);
 876                 else if ( header->vci == 0x03 || header->vci == 0x04 )
 877                         conn = find_vpi(header->vpi);
 878                 else
 879                         conn = -1;
 880
 881                 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
 882                         vcc = g_atm_priv_data.conn[conn].vcc;
 883
 884                         if ( vcc->push_oam != NULL )
 885                                 vcc->push_oam(vcc, header);
 886                         else
 887                                 ifx_push_oam((unsigned char *)header);
 888
 889                         g_atm_priv_data.wrx_oam++;
 890
 891                         adsl_led_flash();
 892                 } else
 893                         g_atm_priv_data.wrx_drop_oam++;
 894
 895                 reg_desc.byteoff = 0;
 896                 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
 897                 reg_desc.own = 1;
 898                 reg_desc.c   = 0;
 899
 900                 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
 901                 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
 902                         g_atm_priv_data.oam_desc_pos = 0;
 903
 904                 dma_cache_inv((unsigned long)header, CELL_SIZE);
 905                 mailbox_signal(RX_DMA_CH_OAM, 0);
 906         }
 907 }
 908
 909 static inline void mailbox_aal_rx_handler(void)
 910 {
 911         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
 912         struct rx_descriptor reg_desc;
 913         int conn;
 914         struct atm_vcc *vcc;
 915         struct sk_buff *skb, *new_skb;
 916         struct rx_inband_trailer *trailer;
 917         unsigned int i;
 918
 919         for ( i = 0; i < vlddes; i++ ) {
 920                 unsigned int loop_count = 0;
 921
 922                 do {
 923                         reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
 924                         if ( ++loop_count == 1000 )
 925                                 break;
 926                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 927                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
 928
 929                 conn = reg_desc.id;
 930
 931                 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
 932                         vcc = g_atm_priv_data.conn[conn].vcc;
 933
 934                         skb = get_skb_rx_pointer(reg_desc.dataptr);
 935
 936                         if ( reg_desc.err ) {
 937                                 if ( vcc->qos.aal == ATM_AAL5 ) {
 938                                         trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
 939                                         if ( trailer->stw_crc )
 940                                                 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
 941                                         if ( trailer->stw_ovz )
 942                                                 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
 943                                         g_atm_priv_data.wrx_drop_pdu++;
 944                                 }
 945                                 if ( vcc->stats ) {
 946                                         atomic_inc(&vcc->stats->rx_drop);
 947                                         atomic_inc(&vcc->stats->rx_err);
 948                                 }
 949                                 reg_desc.err = 0;
 950                         } else if ( atm_charge(vcc, skb->truesize) ) {
 951                                 new_skb = alloc_skb_rx();
 952                                 if ( new_skb != NULL ) {
 953 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 954                                         if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
 955                                                 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
 956 #endif
 957
 958                                         skb_reserve(skb, reg_desc.byteoff);
 959                                         skb_put(skb, reg_desc.datalen);
 960                                         ATM_SKB(skb)->vcc = vcc;
 961
 962                                         vcc->push(vcc, skb);
 963
 964                                         if ( vcc->qos.aal == ATM_AAL5 )
 965                                                 g_atm_priv_data.wrx_pdu++;
 966                                         if ( vcc->stats )
 967                                                 atomic_inc(&vcc->stats->rx);
 968                                         adsl_led_flash();
 969
 970                                         reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
 971                                 } else {
 972                                         atm_return(vcc, skb->truesize);
 973                                         if ( vcc->qos.aal == ATM_AAL5 )
 974                                                 g_atm_priv_data.wrx_drop_pdu++;
 975                                         if ( vcc->stats )
 976                                                 atomic_inc(&vcc->stats->rx_drop);
 977                                 }
 978                         } else {
 979                                 if ( vcc->qos.aal == ATM_AAL5 )
 980                                         g_atm_priv_data.wrx_drop_pdu++;
 981                                 if ( vcc->stats )
 982                                         atomic_inc(&vcc->stats->rx_drop);
 983                         }
 984                 } else {
 985                         g_atm_priv_data.wrx_drop_pdu++;
 986                 }
 987
 988                 reg_desc.byteoff = 0;
 989                 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
 990                 reg_desc.own = 1;
 991                 reg_desc.c   = 0;
 992
 993                 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
 994                 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
 995                         g_atm_priv_data.aal_desc_pos = 0;
 996
 997                 mailbox_signal(RX_DMA_CH_AAL, 0);
 998         }
 999 }
1000
1001 static void do_ppe_tasklet(unsigned long data)
1002 {
1003         unsigned int irqs = *MBOX_IGU1_ISR;
1004         *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1005
1006         if (irqs & (1 << RX_DMA_CH_AAL))
1007                 mailbox_aal_rx_handler();
1008         if (irqs & (1 << RX_DMA_CH_OAM))
1009                 mailbox_oam_rx_handler();
1010
1011         /* any valid tx irqs */
1012         if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1013                 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1014
1015         if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1016                 tasklet_schedule(&g_dma_tasklet);
1017         else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1018                 tasklet_schedule(&g_dma_tasklet);
1019         else
1020                 enable_irq(PPE_MAILBOX_IGU1_INT);
1021 }
1022
1023 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1024 {
1025         if ( !*MBOX_IGU1_ISR )
1026                 return IRQ_HANDLED;
1027
1028         disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1029         tasklet_schedule(&g_dma_tasklet);
1030
1031         return IRQ_HANDLED;
1032 }
1033
1034 static inline void mailbox_signal(unsigned int queue, int is_tx)
1035 {
1036         int count = 1000;
1037
1038         if ( is_tx ) {
1039                 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1040                         count--;
1041                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1042         } else {
1043                 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1044                         count--;
1045                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1046         }
1047
1048         ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1049 }
1050
1051 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1052 {
1053         struct clk *fpi_clk = clk_get_fpi();
1054         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1055         unsigned int qsb_qid = queue + FIRST_QSB_QID;
1056         union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1057         union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1058         unsigned int tmp;
1059
1060
1061         /*
1062          *  Peak Cell Rate (PCR) Limiter
1063          */
1064         if ( qos->txtp.max_pcr == 0 )
1065                 qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
1066         else {
1067                 /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1068                 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1069                 /*  check if overflow takes place   */
1070                 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1071         }
1072
1073 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1074         //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1075         //  Send packets to these two PVCs at same time, it trigger strange behavior.
1076         //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1077         //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1078         //  To work around, create UBR always with max_pcr.
1079         //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1080         if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1081                 int port = g_atm_priv_data.conn[queue].port;
1082                 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1083
1084                 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1085                 if ( tmp > QSB_TP_TS_MAX )
1086                         tmp = QSB_TP_TS_MAX;
1087                 else if ( tmp < 1 )
1088                         tmp = 1;
1089                 qsb_queue_parameter_table.bit.tp = tmp;
1090         }
1091 #endif
1092
1093         /*
1094          *  Weighted Fair Queueing Factor (WFQF)
1095          */
1096         switch ( qos->txtp.traffic_class ) {
1097         case ATM_CBR:
1098         case ATM_VBR_RT:
1099                 /*  real time queue gets weighted fair queueing bypass  */
1100                 qsb_queue_parameter_table.bit.wfqf = 0;
1101                 break;
1102         case ATM_VBR_NRT:
1103         case ATM_UBR_PLUS:
1104                 /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
1105                 /*  WFQF is maximum cell rate / garenteed cell rate                                             */
1106                 /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
1107                 if ( qos->txtp.min_pcr == 0 )
1108                         qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1109                 else {
1110                         tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1111                         if ( tmp == 0 )
1112                                 qsb_queue_parameter_table.bit.wfqf = 1;
1113                         else if ( tmp > QSB_WFQ_NONUBR_MAX )
1114                                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1115                         else
1116                                 qsb_queue_parameter_table.bit.wfqf = tmp;
1117                 }
1118                 break;
1119         default:
1120         case ATM_UBR:
1121                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1122         }
1123
1124         /*
1125          *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1126          */
1127         if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1128 #if 0
1129                 if ( qos->txtp.scr == 0 ) {
1130 #endif
1131                         /*  disable shaper  */
1132                         qsb_queue_vbr_parameter_table.bit.taus = 0;
1133                         qsb_queue_vbr_parameter_table.bit.ts = 0;
1134 #if 0
1135                 } else {
1136                         /*  Cell Loss Priority  (CLP)   */
1137                         if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1138                                 /*  CLP1    */
1139                                 qsb_queue_parameter_table.bit.vbr = 1;
1140                         else
1141                                 /*  CLP0    */
1142                                 qsb_queue_parameter_table.bit.vbr = 0;
1143                         /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1144                         tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1145                         qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1146                         tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1147                         if ( tmp == 0 )
1148                                 qsb_queue_vbr_parameter_table.bit.taus = 1;
1149                         else if ( tmp > QSB_TAUS_MAX )
1150                                 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1151                         else
1152                                 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1153                 }
1154 #endif
1155         } else {
1156                 qsb_queue_vbr_parameter_table.bit.taus = 0;
1157                 qsb_queue_vbr_parameter_table.bit.ts = 0;
1158         }
1159
1160         /*  Queue Parameter Table (QPT) */
1161         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1162         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1163         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1164         /*  Queue VBR Paramter Table (QVPT) */
1165         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1166         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1167         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1168
1169 }
1170
1171 static void qsb_global_set(void)
1172 {
1173         struct clk *fpi_clk = clk_get_fpi();
1174         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1175         int i;
1176         unsigned int tmp1, tmp2, tmp3;
1177
1178         *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1179         *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
1180         *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1181
1182         /*
1183          *  set SCT and SPT per port
1184          */
1185         for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1186                 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1187                         tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1188                         tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
1189                         tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
1190                         /*  carry over to integer part (?)  */
1191                         if ( tmp3 == (1 << 6) ) {
1192                                 tmp3 = 0;
1193                                 tmp2++;
1194                         }
1195                         if ( tmp2 == 0 )
1196                                 tmp2 = tmp3 = 1;
1197                         /*  1. set mask                                 */
1198                         /*  2. write value to data transfer register    */
1199                         /*  3. start the tranfer                        */
1200                         /*  SCT (FracRate)  */
1201                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1202                         *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
1203                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1204                                         QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1205                                         QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1206                                         QSB_RAMAC_TESEL_SET(i & 0x01);
1207                         /*  SPT (SBV + PN + IntRage)    */
1208                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1209                         *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1210                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1211                                 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1212                                 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1213                                 QSB_RAMAC_TESEL_SET(i & 0x01);
1214                 }
1215         }
1216 }
1217
1218 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1219 {
1220         struct htu_entry htu_entry = {
1221                 res1:       0x00,
1222                 clp:        is_retx ? 0x01 : 0x00,
1223                 pid:        g_atm_priv_data.conn[queue].port & 0x01,
1224                 vpi:        vpi,
1225                 vci:        vci,
1226                 pti:        0x00,
1227                 vld:        0x01};
1228
1229         struct htu_mask htu_mask = {
1230                 set:        0x01,
1231                 clp:        0x01,
1232                 pid_mask:   0x02,
1233                 vpi_mask:   0x00,
1234                 vci_mask:   0x0000,
1235                 pti_mask:   0x03,   //  0xx, user data
1236                 clear:      0x00};
1237
1238         struct htu_result htu_result = {
1239                 res1:       0x00,
1240                 cellid:     queue,
1241                 res2:       0x00,
1242                 type:       aal5 ? 0x00 : 0x01,
1243                 ven:        0x01,
1244                 res3:       0x00,
1245                 qid:        queue};
1246
1247         *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1248         *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1249         *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1250 }
1251
1252 static inline void clear_htu_entry(unsigned int queue)
1253 {
1254         HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1255 }
1256
1257 static void validate_oam_htu_entry(void)
1258 {
1259         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1260         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1261         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1262 }
1263
1264 static void invalidate_oam_htu_entry(void)
1265 {
1266         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1267         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1268         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1269 }
1270
1271 static inline int find_vpi(unsigned int vpi)
1272 {
1273         int i;
1274         unsigned int bit;
1275
1276         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1277                 if ( (g_atm_priv_data.conn_table & bit) != 0
1278                                 && g_atm_priv_data.conn[i].vcc != NULL
1279                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1280                         return i;
1281         }
1282
1283         return -1;
1284 }
1285
1286 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1287 {
1288         int i;
1289         unsigned int bit;
1290
1291         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1292                 if ( (g_atm_priv_data.conn_table & bit) != 0
1293                                 && g_atm_priv_data.conn[i].vcc != NULL
1294                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1295                                 && vci == g_atm_priv_data.conn[i].vcc->vci )
1296                         return i;
1297         }
1298
1299         return -1;
1300 }
1301
1302 static inline int find_vcc(struct atm_vcc *vcc)
1303 {
1304         int i;
1305         unsigned int bit;
1306
1307         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1308                 if ( (g_atm_priv_data.conn_table & bit) != 0
1309                         && g_atm_priv_data.conn[i].vcc == vcc )
1310                 return i;
1311         }
1312
1313         return -1;
1314 }
1315
1316 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1317 {
1318         int len = 0;
1319         unsigned int major, minor;
1320
1321         ops->fw_ver(&major, &minor);
1322
1323         len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1324         len += sprintf(buf + len, "    ATM (A1) firmware version %d.%d\n", major, minor);
1325
1326         return len;
1327 }
1328
1329 static inline void check_parameters(void)
1330 {
1331         /*  Please refer to Amazon spec 15.4 for setting these values.  */
1332         if ( qsb_tau < 1 )
1333                 qsb_tau = 1;
1334         if ( qsb_tstep < 1 )
1335                 qsb_tstep = 1;
1336         else if ( qsb_tstep > 4 )
1337                 qsb_tstep = 4;
1338         else if ( qsb_tstep == 3 )
1339                 qsb_tstep = 2;
1340
1341         /*  There is a delay between PPE write descriptor and descriptor is       */
1342         /*  really stored in memory. Host also has this delay when writing        */
1343         /*  descriptor. So PPE will use this value to determine if the write      */
1344         /*  operation makes effect.                                               */
1345         if ( write_descriptor_delay < 0 )
1346                 write_descriptor_delay = 0;
1347
1348         if ( aal5_fill_pattern < 0 )
1349                 aal5_fill_pattern = 0;
1350         else
1351                 aal5_fill_pattern &= 0xFF;
1352
1353         /*  Because of the limitation of length field in descriptors, the packet  */
1354         /*  size could not be larger than 64K minus overhead size.                */
1355         if ( aal5r_max_packet_size < 0 )
1356                 aal5r_max_packet_size = 0;
1357         else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1358                 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1359         if ( aal5r_min_packet_size < 0 )
1360                 aal5r_min_packet_size = 0;
1361         else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1362                 aal5r_min_packet_size = aal5r_max_packet_size;
1363         if ( aal5s_max_packet_size < 0 )
1364                 aal5s_max_packet_size = 0;
1365         else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1366                 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1367         if ( aal5s_min_packet_size < 0 )
1368                 aal5s_min_packet_size = 0;
1369         else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1370                 aal5s_min_packet_size = aal5s_max_packet_size;
1371
1372         if ( dma_rx_descriptor_length < 2 )
1373                 dma_rx_descriptor_length = 2;
1374         if ( dma_tx_descriptor_length < 2 )
1375                 dma_tx_descriptor_length = 2;
1376         if ( dma_rx_clp1_descriptor_threshold < 0 )
1377                 dma_rx_clp1_descriptor_threshold = 0;
1378         else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1379                 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1380
1381         if ( dma_tx_descriptor_length < 2 )
1382                 dma_tx_descriptor_length = 2;
1383 }
1384
1385 static inline int init_priv_data(void)
1386 {
1387         void *p;
1388         int i;
1389         struct rx_descriptor rx_desc = {0};
1390         struct sk_buff *skb;
1391         volatile struct tx_descriptor *p_tx_desc;
1392         struct sk_buff **ppskb;
1393
1394         //  clear atm private data structure
1395         memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1396
1397         //  allocate memory for RX (AAL) descriptors
1398         p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1399         if ( p == NULL )
1400                 return -1;
1401         dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1402         g_atm_priv_data.aal_desc_base = p;
1403         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1404         g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1405
1406         //  allocate memory for RX (OAM) descriptors
1407         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1408         if ( p == NULL )
1409                 return -1;
1410         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1411         g_atm_priv_data.oam_desc_base = p;
1412         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1413         g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1414
1415         //  allocate memory for RX (OAM) buffer
1416         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1417         if ( p == NULL )
1418                 return -1;
1419         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1420         g_atm_priv_data.oam_buf_base = p;
1421         p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1422         g_atm_priv_data.oam_buf = p;
1423
1424         //  allocate memory for TX descriptors
1425         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1426         if ( p == NULL )
1427                 return -1;
1428         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1429         g_atm_priv_data.tx_desc_base = p;
1430
1431         //  allocate memory for TX skb pointers
1432         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1433         if ( p == NULL )
1434                 return -1;
1435         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1436         g_atm_priv_data.tx_skb_base = p;
1437
1438         //  setup RX (AAL) descriptors
1439         rx_desc.own     = 1;
1440         rx_desc.c       = 0;
1441         rx_desc.sop     = 1;
1442         rx_desc.eop     = 1;
1443         rx_desc.byteoff = 0;
1444         rx_desc.id      = 0;
1445         rx_desc.err     = 0;
1446         rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1447         for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1448                 skb = alloc_skb_rx();
1449                 if ( skb == NULL )
1450                         return -1;
1451                 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1452                 g_atm_priv_data.aal_desc[i] = rx_desc;
1453         }
1454
1455         //  setup RX (OAM) descriptors
1456         p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1457         rx_desc.own     = 1;
1458         rx_desc.c       = 0;
1459         rx_desc.sop     = 1;
1460         rx_desc.eop     = 1;
1461         rx_desc.byteoff = 0;
1462         rx_desc.id      = 0;
1463         rx_desc.err     = 0;
1464         rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1465         for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1466                 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1467                 g_atm_priv_data.oam_desc[i] = rx_desc;
1468                 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1469         }
1470
1471         //  setup TX descriptors and skb pointers
1472         p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1473         ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1474         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1475                 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1476                 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1477                 g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
1478         }
1479
1480         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1481                 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1482
1483         return 0;
1484 }
1485
1486 static inline void clear_priv_data(void)
1487 {
1488         int i, j;
1489         struct sk_buff *skb;
1490
1491         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1492                 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1493                         for ( j = 0; j < dma_tx_descriptor_length; j++ )
1494                                 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1495                                         dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1496                 }
1497         }
1498
1499         if ( g_atm_priv_data.tx_skb_base != NULL )
1500                 kfree(g_atm_priv_data.tx_skb_base);
1501
1502         if ( g_atm_priv_data.tx_desc_base != NULL )
1503                 kfree(g_atm_priv_data.tx_desc_base);
1504
1505         if ( g_atm_priv_data.oam_buf_base != NULL )
1506                 kfree(g_atm_priv_data.oam_buf_base);
1507
1508         if ( g_atm_priv_data.oam_desc_base != NULL )
1509                 kfree(g_atm_priv_data.oam_desc_base);
1510
1511         if ( g_atm_priv_data.aal_desc_base != NULL ) {
1512                 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1513                         if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
1514                                 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1515                                 dev_kfree_skb_any(skb);
1516                         }
1517                 }
1518                 kfree(g_atm_priv_data.aal_desc_base);
1519         }
1520 }
1521
1522 static inline void init_rx_tables(void)
1523 {
1524         int i;
1525         struct wrx_queue_config wrx_queue_config = {0};
1526         struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1527         struct htu_entry htu_entry = {0};
1528         struct htu_result htu_result = {0};
1529         struct htu_mask htu_mask = {
1530                 set:        0x01,
1531                 clp:        0x01,
1532                 pid_mask:   0x00,
1533                 vpi_mask:   0x00,
1534                 vci_mask:   0x00,
1535                 pti_mask:   0x00,
1536                 clear:      0x00
1537         };
1538
1539         /*
1540          *  General Registers
1541          */
1542         *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1543 #ifndef CONFIG_AMAZON_SE
1544         *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
1545 #endif
1546         *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1547         *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
1548         *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1549
1550         /*
1551          *  WRX Queue Configuration Table
1552          */
1553         wrx_queue_config.uumask    = 0xFF;
1554         wrx_queue_config.cpimask   = 0xFF;
1555         wrx_queue_config.uuexp     = 0;
1556         wrx_queue_config.cpiexp    = 0;
1557         wrx_queue_config.mfs       = aal5r_max_packet_size;
1558         wrx_queue_config.oversize  = aal5r_max_packet_size;
1559         wrx_queue_config.undersize = aal5r_min_packet_size;
1560         wrx_queue_config.errdp     = aal5r_drop_error_packet;
1561         wrx_queue_config.dmach     = RX_DMA_CH_AAL;
1562         for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1563                 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1564         WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1565
1566         /*
1567          *  WRX DMA Channel Configuration Table
1568          */
1569         wrx_dma_channel_config.chrl   = 0;
1570         wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1571         wrx_dma_channel_config.mode   = 0;
1572         wrx_dma_channel_config.rlcfg  = 0;
1573
1574         wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1575         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1576         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1577
1578         wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1579         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1580         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1581
1582         /*
1583          *  HTU Tables
1584          */
1585         for (i = 0; i < MAX_PVC_NUMBER; i++) {
1586                 htu_result.qid = (unsigned int)i;
1587
1588                 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1589                 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1590                 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1591         }
1592
1593         /*  OAM HTU Entry   */
1594         htu_entry.vci = 0x03;
1595         htu_mask.pid_mask = 0x03;
1596         htu_mask.vpi_mask = 0xFF;
1597         htu_mask.vci_mask = 0x0000;
1598         htu_mask.pti_mask = 0x07;
1599         htu_result.cellid = OAM_RX_QUEUE;
1600         htu_result.type   = 1;
1601         htu_result.ven    = 1;
1602         htu_result.qid    = OAM_RX_QUEUE;
1603         *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1604         *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
1605         *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
1606         htu_entry.vci     = 0x04;
1607         htu_result.cellid = OAM_RX_QUEUE;
1608         htu_result.type   = 1;
1609         htu_result.ven    = 1;
1610         htu_result.qid    = OAM_RX_QUEUE;
1611         *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1612         *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
1613         *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
1614         htu_entry.vci     = 0x00;
1615         htu_entry.pti     = 0x04;
1616         htu_mask.vci_mask = 0xFFFF;
1617         htu_mask.pti_mask = 0x01;
1618         htu_result.cellid = OAM_RX_QUEUE;
1619         htu_result.type   = 1;
1620         htu_result.ven    = 1;
1621         htu_result.qid    = OAM_RX_QUEUE;
1622         *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1623         *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
1624         *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
1625 }
1626
1627 static inline void init_tx_tables(void)
1628 {
1629         int i;
1630         struct wtx_queue_config wtx_queue_config = {0};
1631         struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1632         struct wtx_port_config wtx_port_config = {
1633                 res1:   0,
1634                 qid:    0,
1635                 qsben:  1
1636         };
1637
1638         /*
1639          *  General Registers
1640          */
1641         *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
1642         *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1643         *CFG_WRDES_DELAY    = write_descriptor_delay;
1644
1645         /*
1646          *  WTX Port Configuration Table
1647          */
1648         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1649                 *WTX_PORT_CONFIG(i) = wtx_port_config;
1650
1651         /*
1652          *  WTX Queue Configuration Table
1653          */
1654         wtx_queue_config.qsben = 1;
1655         wtx_queue_config.sbid  = 0;
1656         for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1657                 wtx_queue_config.qsb_vcid = i;
1658                 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1659         }
1660
1661         /*
1662          *  WTX DMA Channel Configuration Table
1663          */
1664         wtx_dma_channel_config.mode   = 0;
1665         wtx_dma_channel_config.deslen = 0;
1666         wtx_dma_channel_config.desba  = 0;
1667         for ( i = 0; i < FIRST_QSB_QID; i++ )
1668                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1669         /*  normal connection   */
1670         wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1671         for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1672                 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1673                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1674         }
1675 }
1676
1677 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1678 {
1679         int i, j, port_num;
1680
1681         ASSERT(port_cell != NULL, "port_cell is NULL");
1682         ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1683
1684         for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1685                 if ( port_cell->tx_link_rate[j] > 0 )
1686                         break;
1687         for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1688                 g_atm_priv_data.port[i].tx_max_cell_rate =
1689                         port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1690
1691         qsb_global_set();
1692
1693         for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1694                 if ( g_atm_priv_data.conn[i].vcc != NULL )
1695                         set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1696
1697         //  TODO: ReTX set xdata_addr
1698         g_xdata_addr = xdata_addr;
1699
1700         g_showtime = 1;
1701
1702         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1703                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1704
1705 #if defined(CONFIG_VR9)
1706         IFX_REG_W32(0x0F, UTP_CFG);
1707 #endif
1708
1709         printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1710                 g_atm_priv_data.port[0].tx_max_cell_rate,
1711                 g_atm_priv_data.port[1].tx_max_cell_rate,
1712                 (unsigned int)g_xdata_addr);
1713
1714         return 0;
1715 }
1716
1717 static int atm_showtime_exit(void)
1718 {
1719         int port_num;
1720
1721         if ( !g_showtime )
1722                 return -1;
1723
1724 #if defined(CONFIG_VR9)
1725         IFX_REG_W32(0x00, UTP_CFG);
1726 #endif
1727
1728         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1729                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1730
1731         g_showtime = 0;
1732         g_xdata_addr = NULL;
1733         printk("leave showtime\n");
1734         return 0;
1735 }
1736
1737 extern struct ltq_atm_ops ar9_ops;
1738 extern struct ltq_atm_ops vr9_ops;
1739 extern struct ltq_atm_ops danube_ops;
1740 extern struct ltq_atm_ops ase_ops;
1741
1742 static const struct of_device_id ltq_atm_match[] = {
1743 #ifdef CONFIG_DANUBE
1744         { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1745 #elif defined CONFIG_AMAZON_SE
1746         { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1747 #elif defined CONFIG_AR9
1748         { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1749 #elif defined CONFIG_VR9
1750         { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1751 #endif
1752         {},
1753 };
1754 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1755
1756 static int ltq_atm_probe(struct platform_device *pdev)
1757 {
1758         const struct of_device_id *match;
1759         struct ltq_atm_ops *ops = NULL;
1760         int ret;
1761         int port_num;
1762         struct port_cell_info port_cell = {0};
1763         char ver_str[256];
1764
1765         match = of_match_device(ltq_atm_match, &pdev->dev);
1766         if (!match) {
1767                 dev_err(&pdev->dev, "failed to find matching device\n");
1768                 return -ENOENT;
1769         }
1770         ops = (struct ltq_atm_ops *) match->data;
1771
1772         check_parameters();
1773
1774         ret = init_priv_data();
1775         if ( ret != 0 ) {
1776                 pr_err("INIT_PRIV_DATA_FAIL\n");
1777                 goto INIT_PRIV_DATA_FAIL;
1778         }
1779
1780         ops->init();
1781         init_rx_tables();
1782         init_tx_tables();
1783
1784         /*  create devices  */
1785         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1786                 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1787                 if ( !g_atm_priv_data.port[port_num].dev ) {
1788                         pr_err("failed to register atm device %d!\n", port_num);
1789                         ret = -EIO;
1790                         goto ATM_DEV_REGISTER_FAIL;
1791                 } else {
1792                         g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1793                         g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1794                         g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1795                         g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1796
1797 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1798                         atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1799 #endif
1800                 }
1801         }
1802
1803         /*  register interrupt handler  */
1804 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1805         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1806 #else
1807         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1808 #endif
1809         if ( ret ) {
1810                 if ( ret == -EBUSY ) {
1811                         pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1812                 } else {
1813                         pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1814                 }
1815                 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1816         }
1817         disable_irq(PPE_MAILBOX_IGU1_INT);
1818
1819
1820         ret = ops->start(0);
1821         if ( ret ) {
1822                 pr_err("ifx_pp32_start fail!\n");
1823                 goto PP32_START_FAIL;
1824         }
1825
1826         port_cell.port_num = ATM_PORT_NUMBER;
1827         ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1828         if ( g_showtime ) {
1829                 atm_showtime_enter(&port_cell, &g_xdata_addr);
1830         } else {
1831                 qsb_global_set();
1832         }
1833
1834         validate_oam_htu_entry();
1835
1836         ifx_mei_atm_showtime_enter = atm_showtime_enter;
1837         ifx_mei_atm_showtime_exit  = atm_showtime_exit;
1838
1839         ifx_atm_version(ops, ver_str);
1840         printk(KERN_INFO "%s", ver_str);
1841         platform_set_drvdata(pdev, ops);
1842         printk("ifxmips_atm: ATM init succeed\n");
1843
1844         return 0;
1845
1846 PP32_START_FAIL:
1847         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1848 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1849 ATM_DEV_REGISTER_FAIL:
1850         while ( port_num-- > 0 )
1851                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1852 INIT_PRIV_DATA_FAIL:
1853         clear_priv_data();
1854         printk("ifxmips_atm: ATM init failed\n");
1855         return ret;
1856 }
1857
1858 static int ltq_atm_remove(struct platform_device *pdev)
1859 {
1860         int port_num;
1861         struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1862
1863         ifx_mei_atm_showtime_enter = NULL;
1864         ifx_mei_atm_showtime_exit  = NULL;
1865
1866         invalidate_oam_htu_entry();
1867
1868         ops->stop(0);
1869
1870         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1871
1872         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1873                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1874
1875         ops->shutdown();
1876
1877         clear_priv_data();
1878
1879         return 0;
1880 }
1881
1882 static struct platform_driver ltq_atm_driver = {
1883         .probe = ltq_atm_probe,
1884         .remove = ltq_atm_remove,
1885         .driver = {
1886                 .name = "atm",
1887                 .owner = THIS_MODULE,
1888                 .of_match_table = ltq_atm_match,
1889         },
1890 };
1891
1892 module_platform_driver(ltq_atm_driver);
1893
1894 MODULE_LICENSE("Dual BSD/GPL");