package/kernel/lantiq/ltq-atm/src/ltq_atm.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 **
  23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
  24 *******************************************************************************/
  25
  26 #define IFX_ATM_VER_MAJOR               1
  27 #define IFX_ATM_VER_MID                 0
  28 #define IFX_ATM_VER_MINOR               26
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/version.h>
  33 #include <linux/types.h>
  34 #include <linux/errno.h>
  35 #include <linux/proc_fs.h>
  36 #include <linux/init.h>
  37 #include <linux/ioctl.h>
  38 #include <linux/atmdev.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/of_device.h>
  41 #include <linux/atm.h>
  42 #include <linux/clk.h>
  43 #include <linux/interrupt.h>
  44 #ifdef CONFIG_XFRM
  45   #include <net/xfrm.h>
  46 #endif
  47
  48 #include <lantiq_soc.h>
  49
  50 #include "ifxmips_atm_core.h"
  51
  52 #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
  53 #define MODULE_PARM(a, b)         module_param(a, int, 0)
  54
  55 /*!
  56   \brief QSB cell delay variation due to concurrency
  57  */
  58 static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
  59 /*!
  60   \brief QSB scheduler burst length
  61  */
  62 static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
  63 /*!
  64   \brief QSB time step, all legal values are 1, 2, 4
  65  */
  66 static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
  67
  68 /*!
  69   \brief Write descriptor delay
  70  */
  71 static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
  72
  73 /*!
  74   \brief AAL5 padding byte ('~')
  75  */
  76 static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
  77 /*!
  78   \brief Max frame size for RX
  79  */
  80 static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
  81 /*!
  82   \brief Min frame size for RX
  83  */
  84 static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
  85 /*!
  86   \brief Max frame size for TX
  87  */
  88 static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
  89 /*!
  90   \brief Min frame size for TX
  91  */
  92 static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
  93 /*!
  94   \brief Drop error packet in RX path
  95  */
  96 static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
  97
  98 /*!
  99   \brief Number of descriptors per DMA RX channel
 100  */
 101 static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
 102 /*!
 103   \brief Number of descriptors per DMA TX channel
 104  */
 105 static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
 106 /*!
 107   \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
 108  */
 109 static int dma_rx_clp1_descriptor_threshold = 38;
 110 /*@}*/
 111
 112 MODULE_PARM(qsb_tau, "i");
 113 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
 114 MODULE_PARM(qsb_srvm, "i");
 115 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
 116 MODULE_PARM(qsb_tstep, "i");
 117 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
 118
 119 MODULE_PARM(write_descriptor_delay, "i");
 120 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
 121
 122 MODULE_PARM(aal5_fill_pattern, "i");
 123 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
 124 MODULE_PARM(aal5r_max_packet_size, "i");
 125 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
 126 MODULE_PARM(aal5r_min_packet_size, "i");
 127 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
 128 MODULE_PARM(aal5s_max_packet_size, "i");
 129 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
 130 MODULE_PARM(aal5s_min_packet_size, "i");
 131 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
 132 MODULE_PARM(aal5r_drop_error_packet, "i");
 133 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
 134
 135 MODULE_PARM(dma_rx_descriptor_length, "i");
 136 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
 137 MODULE_PARM(dma_tx_descriptor_length, "i");
 138 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
 139 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
 140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
 141
 142
 143
 144 /*
 145  * ####################################
 146  *              Definition
 147  * ####################################
 148  */
 149
 150 #ifdef CONFIG_AMAZON_SE
 151   #define ENABLE_LESS_CACHE_INV                 1
 152   #define LESS_CACHE_INV_LEN                    96
 153 #endif
 154
 155 #define DUMP_SKB_LEN                            ~0
 156
 157
 158
 159 /*
 160  * ####################################
 161  *             Declaration
 162  * ####################################
 163  */
 164
 165 /*
 166  *  Network Operations
 167  */
 168 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
 169 static int ppe_open(struct atm_vcc *);
 170 static void ppe_close(struct atm_vcc *);
 171 static int ppe_send(struct atm_vcc *, struct sk_buff *);
 172 static int ppe_send_oam(struct atm_vcc *, void *, int);
 173 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
 174
 175 /*
 176  *  ADSL LED
 177  */
 178 static inline void adsl_led_flash(void);
 179
 180 /*
 181  *  64-bit operation used by MIB calculation
 182  */
 183 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
 184
 185 /*
 186  *  buffer manage functions
 187  */
 188 static inline struct sk_buff* alloc_skb_rx(void);
 189 static inline struct sk_buff* alloc_skb_tx(unsigned int);
 190 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
 191 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
 192 static inline int get_tx_desc(unsigned int);
 193
 194 /*
 195  *  mailbox handler and signal function
 196  */
 197 static inline void mailbox_oam_rx_handler(void);
 198 static inline void mailbox_aal_rx_handler(void);
 199 static irqreturn_t mailbox_irq_handler(int, void *);
 200 static inline void mailbox_signal(unsigned int, int);
 201 static void do_ppe_tasklet(unsigned long);
 202 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
 203
 204 /*
 205  *  QSB & HTU setting functions
 206  */
 207 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
 208 static void qsb_global_set(void);
 209 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
 210 static inline void clear_htu_entry(unsigned int);
 211 static void validate_oam_htu_entry(void);
 212 static void invalidate_oam_htu_entry(void);
 213
 214 /*
 215  *  look up for connection ID
 216  */
 217 static inline int find_vpi(unsigned int);
 218 static inline int find_vpivci(unsigned int, unsigned int);
 219 static inline int find_vcc(struct atm_vcc *);
 220
 221 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
 222
 223 /*
 224  *  Init & clean-up functions
 225  */
 226 static inline void check_parameters(void);
 227 static inline int init_priv_data(void);
 228 static inline void clear_priv_data(void);
 229 static inline void init_rx_tables(void);
 230 static inline void init_tx_tables(void);
 231
 232 /*
 233  *  Exteranl Function
 234  */
 235 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
 236 extern void ifx_push_oam(unsigned char *);
 237 #else
 238 static inline void ifx_push_oam(unsigned char *dummy) {}
 239 #endif
 240
 241 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
 242 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
 243 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
 244
 245 extern int (*ifx_mei_atm_showtime_exit)(void);
 246 extern int ifx_mei_atm_led_blink(void);
 247 #else
 248 static inline int ifx_mei_atm_led_blink(void) { return 0; }
 249 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
 250 {
 251         if ( is_showtime != NULL )
 252                 *is_showtime = 0;
 253         return 0;
 254 }
 255 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
 256 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
 257
 258 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
 259 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
 260
 261 #endif
 262
 263 static struct atm_priv_data g_atm_priv_data;
 264
 265 static struct atmdev_ops g_ifx_atm_ops = {
 266         .open = ppe_open,
 267         .close = ppe_close,
 268         .ioctl = ppe_ioctl,
 269         .send = ppe_send,
 270         .send_oam = ppe_send_oam,
 271         .change_qos = ppe_change_qos,
 272         .owner = THIS_MODULE,
 273 };
 274
 275 static int g_showtime = 0;
 276 static void *g_xdata_addr = NULL;
 277
 278 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
 279 {
 280         int ret = 0;
 281         atm_cell_ifEntry_t mib_cell;
 282         atm_aal5_ifEntry_t mib_aal5;
 283         atm_aal5_vcc_x_t mib_vcc;
 284         unsigned int value;
 285         int conn;
 286
 287         if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
 288                         || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
 289                 return -ENOTTY;
 290
 291         if ( _IOC_DIR(cmd) & _IOC_READ )
 292 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
 293                 ret = !access_ok(arg, _IOC_SIZE(cmd));
 294 #else
 295                 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 296 #endif
 297         else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 298 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
 299                 ret = !access_ok(arg, _IOC_SIZE(cmd));
 300 #else
 301                 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 302 #endif
 303         if ( ret )
 304                 return -EFAULT;
 305
 306         switch (cmd) {
 307         case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
 308                 /*  These MIB should be read at ARC side, now put zero only.    */
 309                 mib_cell.ifHCInOctets_h = 0;
 310                 mib_cell.ifHCInOctets_l = 0;
 311                 mib_cell.ifHCOutOctets_h = 0;
 312                 mib_cell.ifHCOutOctets_l = 0;
 313                 mib_cell.ifInErrors = 0;
 314                 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
 315                 mib_cell.ifOutErrors = 0;
 316
 317                 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
 318                 break;
 319
 320         case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
 321                 value = WAN_MIB_TABLE->wrx_total_byte;
 322                 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
 323                 g_atm_priv_data.prev_wrx_total_byte = value;
 324                 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
 325                 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
 326
 327                 value = WAN_MIB_TABLE->wtx_total_byte;
 328                 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
 329                 g_atm_priv_data.prev_wtx_total_byte = value;
 330                 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
 331                 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
 332
 333                 mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
 334                 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
 335                 mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
 336                 mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
 337                 mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
 338                 mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
 339
 340                 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
 341                 break;
 342
 343         case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
 344                 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
 345                 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
 346                 if (conn >= 0) {
 347                         mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
 348                         mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
 349                         mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
 350                         ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
 351                 } else
 352                         ret = -EINVAL;
 353                 break;
 354
 355         default:
 356                 ret = -ENOIOCTLCMD;
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int ppe_open(struct atm_vcc *vcc)
 363 {
 364         int ret;
 365         short vpi = vcc->vpi;
 366         int   vci = vcc->vci;
 367         struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
 368         int conn;
 369         int f_enable_irq = 0;
 370
 371         if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
 372                 return -EPROTONOSUPPORT;
 373
 374 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
 375         /*  check bandwidth */
 376         if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 377                 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 378 #if 0
 379                 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 380 #endif
 381                 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
 382         {
 383                 ret = -EINVAL;
 384                 goto PPE_OPEN_EXIT;
 385         }
 386 #endif
 387
 388         /*  check existing vpi,vci  */
 389         conn = find_vpivci(vpi, vci);
 390         if ( conn >= 0 ) {
 391                 ret = -EADDRINUSE;
 392                 goto PPE_OPEN_EXIT;
 393         }
 394
 395         /*  check whether it need to enable irq */
 396         if ( g_atm_priv_data.conn_table == 0 )
 397                 f_enable_irq = 1;
 398
 399         /*  allocate connection */
 400         for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
 401                 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
 402                         g_atm_priv_data.conn[conn].vcc = vcc;
 403                         break;
 404                 }
 405         }
 406         if ( conn == MAX_PVC_NUMBER ) {
 407                 ret = -EINVAL;
 408                 goto PPE_OPEN_EXIT;
 409         }
 410
 411         /*  reserve bandwidth   */
 412         switch ( vcc->qos.txtp.traffic_class ) {
 413         case ATM_CBR:
 414         case ATM_VBR_RT:
 415                 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
 416                 break;
 417         case ATM_VBR_NRT:
 418 #if 0
 419                 port->tx_current_cell_rate += vcc->qos.txtp.scr;
 420 #endif
 421                 break;
 422         case ATM_UBR_PLUS:
 423                 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
 424                 break;
 425         }
 426
 427         /*  set qsb */
 428         set_qsb(vcc, &vcc->qos, conn);
 429
 430         /*  update atm_vcc structure    */
 431         vcc->itf = (int)vcc->dev->dev_data;
 432         vcc->vpi = vpi;
 433         vcc->vci = vci;
 434         set_bit(ATM_VF_READY, &vcc->flags);
 435
 436         /*  enable irq  */
 437         if ( f_enable_irq ) {
 438                 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 439                 *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 440
 441                 enable_irq(PPE_MAILBOX_IGU1_INT);
 442         }
 443
 444         /*  set port    */
 445         WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
 446
 447         /*  set htu entry   */
 448         set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
 449
 450         *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
 451         *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
 452
 453         ret = 0;
 454
 455 PPE_OPEN_EXIT:
 456         return ret;
 457 }
 458
 459 static void ppe_close(struct atm_vcc *vcc)
 460 {
 461         int conn;
 462         struct port *port;
 463         struct connection *connection;
 464         if ( vcc == NULL )
 465                 return;
 466
 467         /*  get connection id   */
 468         conn = find_vcc(vcc);
 469         if ( conn < 0 ) {
 470                 pr_err("can't find vcc\n");
 471                 goto PPE_CLOSE_EXIT;
 472         }
 473         connection = &g_atm_priv_data.conn[conn];
 474         port = &g_atm_priv_data.port[connection->port];
 475
 476         /*  clear htu   */
 477         clear_htu_entry(conn);
 478
 479         /*  release connection  */
 480         connection->vcc = NULL;
 481         connection->aal5_vcc_crc_err = 0;
 482         connection->aal5_vcc_oversize_sdu = 0;
 483         clear_bit(conn, &g_atm_priv_data.conn_table);
 484
 485         /*  disable irq */
 486         if ( g_atm_priv_data.conn_table == 0 )
 487                 disable_irq(PPE_MAILBOX_IGU1_INT);
 488
 489         /*  release bandwidth   */
 490         switch ( vcc->qos.txtp.traffic_class )
 491         {
 492         case ATM_CBR:
 493         case ATM_VBR_RT:
 494                 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
 495                 break;
 496         case ATM_VBR_NRT:
 497 #if 0
 498                 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
 499 #endif
 500                 break;
 501         case ATM_UBR_PLUS:
 502                 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
 503                 break;
 504         }
 505
 506         /* wait for incoming packets to be processed by upper layers */
 507         tasklet_unlock_wait(&g_dma_tasklet);
 508
 509 PPE_CLOSE_EXIT:
 510         return;
 511 }
 512
 513 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
 514 {
 515         int ret;
 516         int conn;
 517         int desc_base;
 518         int byteoff;
 519         int required;
 520         /* the len of the data without offset and header */
 521         int datalen;
 522         unsigned long flags;
 523         struct tx_descriptor reg_desc = {0};
 524         struct tx_inband_header *header;
 525
 526         if ( vcc == NULL || skb == NULL )
 527                 return -EINVAL;
 528
 529
 530         conn = find_vcc(vcc);
 531         if ( conn < 0 ) {
 532                 ret = -EINVAL;
 533                 goto FIND_VCC_FAIL;
 534         }
 535
 536         if ( !g_showtime ) {
 537                 pr_debug("not in showtime\n");
 538                 ret = -EIO;
 539                 goto PPE_SEND_FAIL;
 540         }
 541
 542         byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 543         required = sizeof(*header) + byteoff;
 544         if (!skb_clone_writable(skb, required)) {
 545                 int expand_by = 0;
 546                 int ret;
 547
 548                 if (skb_headroom(skb) < required)
 549                         expand_by = required - skb_headroom(skb);
 550
 551                 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
 552                 if (ret) {
 553                         printk("pskb_expand_head failed.\n");
 554                         atm_free_tx_skb_vcc(skb, vcc);
 555                         return ret;
 556                 }
 557         }
 558
 559         datalen = skb->len;
 560         header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
 561
 562
 563         if ( vcc->qos.aal == ATM_AAL5 ) {
 564                 /*  setup inband trailer    */
 565                 header->uu   = 0;
 566                 header->cpi  = 0;
 567                 header->pad  = aal5_fill_pattern;
 568                 header->res1 = 0;
 569
 570                 /*  setup cell header   */
 571                 header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
 572                 header->pti  = ATM_PTI_US0;
 573                 header->vci  = vcc->vci;
 574                 header->vpi  = vcc->vpi;
 575                 header->gfc  = 0;
 576
 577                 /*  setup descriptor    */
 578                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 579                 reg_desc.datalen = datalen;
 580                 reg_desc.byteoff = byteoff;
 581                 reg_desc.iscell  = 0;
 582         } else {
 583                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 584                 reg_desc.datalen = skb->len;
 585                 reg_desc.byteoff = byteoff;
 586                 reg_desc.iscell  = 1;
 587         }
 588
 589         reg_desc.own = 1;
 590         reg_desc.c = 1;
 591         reg_desc.sop = reg_desc.eop = 1;
 592
 593         spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
 594         desc_base = get_tx_desc(conn);
 595         if ( desc_base < 0 ) {
 596                 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 597                 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
 598                 ret = -EIO;
 599                 goto PPE_SEND_FAIL;
 600         }
 601         /*  update descriptor send pointer  */
 602         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 603                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 604         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 605
 606         spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
 607
 608         if ( vcc->stats )
 609                 atomic_inc(&vcc->stats->tx);
 610         if ( vcc->qos.aal == ATM_AAL5 )
 611                 g_atm_priv_data.wtx_pdu++;
 612         /*  write discriptor to memory and write back cache */
 613         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 614         dma_cache_wback((unsigned long)skb->data, skb->len);
 615
 616         mailbox_signal(conn, 1);
 617
 618         adsl_led_flash();
 619
 620         return 0;
 621
 622 FIND_VCC_FAIL:
 623         pr_err("FIND_VCC_FAIL\n");
 624         g_atm_priv_data.wtx_err_pdu++;
 625         dev_kfree_skb_any(skb);
 626         return ret;
 627
 628 PPE_SEND_FAIL:
 629         if ( vcc->qos.aal == ATM_AAL5 )
 630                 g_atm_priv_data.wtx_drop_pdu++;
 631         if ( vcc->stats )
 632                 atomic_inc(&vcc->stats->tx_err);
 633         dev_kfree_skb_any(skb);
 634         return ret;
 635 }
 636
 637 /* operation and maintainance */
 638 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
 639 {
 640         int conn;
 641         struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
 642         int desc_base;
 643         struct sk_buff *skb;
 644         struct tx_descriptor reg_desc = {0};
 645
 646         if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
 647                         && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
 648                         || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
 649                         && find_vpi(uni_cell_header->vpi) < 0) )
 650         {
 651                 g_atm_priv_data.wtx_err_oam++;
 652                 return -EINVAL;
 653         }
 654
 655         if ( !g_showtime ) {
 656                 pr_err("not in showtime\n");
 657                 g_atm_priv_data.wtx_drop_oam++;
 658                 return -EIO;
 659         }
 660
 661         conn = find_vcc(vcc);
 662         if ( conn < 0 ) {
 663                 pr_err("FIND_VCC_FAIL\n");
 664                 g_atm_priv_data.wtx_drop_oam++;
 665                 return -EINVAL;
 666         }
 667
 668         skb = alloc_skb_tx(CELL_SIZE);
 669         if ( skb == NULL ) {
 670                 pr_err("ALLOC_SKB_TX_FAIL\n");
 671                 g_atm_priv_data.wtx_drop_oam++;
 672                 return -ENOMEM;
 673         }
 674         skb_put(skb, CELL_SIZE);
 675         memcpy(skb->data, cell, CELL_SIZE);
 676
 677         reg_desc.dataptr = (unsigned int)skb->data >> 2;
 678         reg_desc.datalen = CELL_SIZE;
 679         reg_desc.byteoff = 0;
 680         reg_desc.iscell  = 1;
 681
 682         reg_desc.own = 1;
 683         reg_desc.c = 1;
 684         reg_desc.sop = reg_desc.eop = 1;
 685
 686         desc_base = get_tx_desc(conn);
 687         if ( desc_base < 0 ) {
 688                 dev_kfree_skb_any(skb);
 689                 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
 690                 g_atm_priv_data.wtx_drop_oam++;
 691                 return -EIO;
 692         }
 693
 694         if ( vcc->stats )
 695                 atomic_inc(&vcc->stats->tx);
 696
 697         /*  update descriptor send pointer  */
 698         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 699                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 700         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 701
 702         /*  write discriptor to memory and write back cache */
 703         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 704         dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
 705
 706         mailbox_signal(conn, 1);
 707
 708         g_atm_priv_data.wtx_oam++;
 709         adsl_led_flash();
 710
 711         return 0;
 712 }
 713
 714 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
 715 {
 716         int conn;
 717
 718         if ( vcc == NULL || qos == NULL )
 719                 return -EINVAL;
 720
 721         conn = find_vcc(vcc);
 722         if ( conn < 0 )
 723                 return -EINVAL;
 724
 725         set_qsb(vcc, qos, conn);
 726
 727         return 0;
 728 }
 729
 730 static inline void adsl_led_flash(void)
 731 {
 732         ifx_mei_atm_led_blink();
 733 }
 734
 735 /*
 736 *  Description:
 737 *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
 738 *  Input:
 739 *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
 740 *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
 741 *    ret  --- ppe_u64_t, pointer to a variable to hold result
 742 *  Output:
 743 *    none
 744 */
 745 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
 746 {
 747         ret->l = opt1.l + opt2;
 748         if ( ret->l < opt1.l || ret->l < opt2 )
 749                 ret->h++;
 750 }
 751
 752 static inline struct sk_buff* alloc_skb_rx(void)
 753 {
 754         struct sk_buff *skb;
 755
 756         skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
 757         if ( skb != NULL ) {
 758                 /*  must be burst length alignment  */
 759                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
 760                         skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
 761                 /*  pub skb in reserved area "skb->data - 4"    */
 762                 *((struct sk_buff **)skb->data - 1) = skb;
 763                 /*  write back and invalidate cache */
 764                 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
 765                 /*  invalidate cache    */
 766 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 767                 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
 768 #else
 769                 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
 770 #endif
 771         }
 772         return skb;
 773 }
 774
 775 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
 776 {
 777         struct sk_buff *skb;
 778
 779         /*  allocate memory including header and padding    */
 780         size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
 781         size &= ~(DATA_BUFFER_ALIGNMENT - 1);
 782         skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
 783         /*  must be burst length alignment  */
 784         if ( skb != NULL )
 785                 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
 786         return skb;
 787 }
 788
 789 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
 790 {
 791         if ( vcc->pop != NULL )
 792                 vcc->pop(vcc, skb);
 793         else
 794                 dev_kfree_skb_any(skb);
 795 }
 796
 797 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
 798 {
 799         unsigned int skb_dataptr;
 800         struct sk_buff *skb;
 801
 802         skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
 803         skb = *(struct sk_buff **)skb_dataptr;
 804
 805         ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
 806         ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
 807
 808         return skb;
 809 }
 810
 811 static inline int get_tx_desc(unsigned int conn)
 812 {
 813         int desc_base = -1;
 814         struct connection *p_conn = &g_atm_priv_data.conn[conn];
 815
 816         if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
 817                 desc_base = p_conn->tx_desc_pos;
 818                 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
 819                         p_conn->tx_desc_pos = 0;
 820         }
 821
 822         return desc_base;
 823 }
 824
 825 static void free_tx_ring(unsigned int queue)
 826 {
 827         unsigned long flags;
 828         int i;
 829         struct connection *conn = &g_atm_priv_data.conn[queue];
 830         struct sk_buff *skb;
 831
 832         if (!conn)
 833                 return;
 834
 835         spin_lock_irqsave(&conn->lock, flags);
 836
 837         for (i = 0; i < dma_tx_descriptor_length; i++) {
 838                 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
 839                         skb = conn->tx_skb[i];
 840                         conn->tx_skb[i] = NULL;
 841                         atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
 842                 }
 843         }
 844         spin_unlock_irqrestore(&conn->lock, flags);
 845 }
 846
 847 static void mailbox_tx_handler(unsigned int queue_bitmap)
 848 {
 849         int i;
 850         int bit;
 851
 852         /* only get valid queues */
 853         queue_bitmap &= g_atm_priv_data.conn_table;
 854
 855         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
 856                 if (queue_bitmap & bit)
 857                         free_tx_ring(i);
 858         }
 859 }
 860
 861 static inline void mailbox_oam_rx_handler(void)
 862 {
 863         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
 864         struct rx_descriptor reg_desc;
 865         struct uni_cell_header *header;
 866         int conn;
 867         struct atm_vcc *vcc;
 868         unsigned int i;
 869
 870         for ( i = 0; i < vlddes; i++ ) {
 871                 unsigned int loop_count = 0;
 872
 873                 do {
 874                         reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
 875                         if ( ++loop_count == 1000 )
 876                                 break;
 877                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 878                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
 879
 880                 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
 881
 882                 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
 883                         conn = find_vpivci(header->vpi, header->vci);
 884                 else if ( header->vci == 0x03 || header->vci == 0x04 )
 885                         conn = find_vpi(header->vpi);
 886                 else
 887                         conn = -1;
 888
 889                 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
 890                         vcc = g_atm_priv_data.conn[conn].vcc;
 891
 892                         if ( vcc->push_oam != NULL )
 893                                 vcc->push_oam(vcc, header);
 894                         else
 895                                 ifx_push_oam((unsigned char *)header);
 896
 897                         g_atm_priv_data.wrx_oam++;
 898
 899                         adsl_led_flash();
 900                 } else
 901                         g_atm_priv_data.wrx_drop_oam++;
 902
 903                 reg_desc.byteoff = 0;
 904                 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
 905                 reg_desc.own = 1;
 906                 reg_desc.c   = 0;
 907
 908                 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
 909                 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
 910                         g_atm_priv_data.oam_desc_pos = 0;
 911
 912                 dma_cache_inv((unsigned long)header, CELL_SIZE);
 913                 mailbox_signal(RX_DMA_CH_OAM, 0);
 914         }
 915 }
 916
 917 static inline void mailbox_aal_rx_handler(void)
 918 {
 919         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
 920         struct rx_descriptor reg_desc;
 921         int conn;
 922         struct atm_vcc *vcc;
 923         struct sk_buff *skb, *new_skb;
 924         struct rx_inband_trailer *trailer;
 925         unsigned int i;
 926
 927         for ( i = 0; i < vlddes; i++ ) {
 928                 unsigned int loop_count = 0;
 929
 930                 do {
 931                         reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
 932                         if ( ++loop_count == 1000 )
 933                                 break;
 934                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 935                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
 936
 937                 conn = reg_desc.id;
 938
 939                 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
 940                         vcc = g_atm_priv_data.conn[conn].vcc;
 941
 942                         skb = get_skb_rx_pointer(reg_desc.dataptr);
 943
 944                         if ( reg_desc.err ) {
 945                                 if ( vcc->qos.aal == ATM_AAL5 ) {
 946                                         trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
 947                                         if ( trailer->stw_crc )
 948                                                 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
 949                                         if ( trailer->stw_ovz )
 950                                                 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
 951                                         g_atm_priv_data.wrx_drop_pdu++;
 952                                 }
 953                                 if ( vcc->stats ) {
 954                                         atomic_inc(&vcc->stats->rx_drop);
 955                                         atomic_inc(&vcc->stats->rx_err);
 956                                 }
 957                                 reg_desc.err = 0;
 958                         } else if ( atm_charge(vcc, skb->truesize) ) {
 959                                 new_skb = alloc_skb_rx();
 960                                 if ( new_skb != NULL ) {
 961 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 962                                         if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
 963                                                 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
 964 #endif
 965
 966                                         skb_reserve(skb, reg_desc.byteoff);
 967                                         skb_put(skb, reg_desc.datalen);
 968                                         ATM_SKB(skb)->vcc = vcc;
 969
 970                                         vcc->push(vcc, skb);
 971
 972                                         if ( vcc->qos.aal == ATM_AAL5 )
 973                                                 g_atm_priv_data.wrx_pdu++;
 974                                         if ( vcc->stats )
 975                                                 atomic_inc(&vcc->stats->rx);
 976                                         adsl_led_flash();
 977
 978                                         reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
 979                                 } else {
 980                                         atm_return(vcc, skb->truesize);
 981                                         if ( vcc->qos.aal == ATM_AAL5 )
 982                                                 g_atm_priv_data.wrx_drop_pdu++;
 983                                         if ( vcc->stats )
 984                                                 atomic_inc(&vcc->stats->rx_drop);
 985                                 }
 986                         } else {
 987                                 if ( vcc->qos.aal == ATM_AAL5 )
 988                                         g_atm_priv_data.wrx_drop_pdu++;
 989                                 if ( vcc->stats )
 990                                         atomic_inc(&vcc->stats->rx_drop);
 991                         }
 992                 } else {
 993                         g_atm_priv_data.wrx_drop_pdu++;
 994                 }
 995
 996                 reg_desc.byteoff = 0;
 997                 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
 998                 reg_desc.own = 1;
 999                 reg_desc.c   = 0;
1000
1001                 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1002                 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1003                         g_atm_priv_data.aal_desc_pos = 0;
1004
1005                 mailbox_signal(RX_DMA_CH_AAL, 0);
1006         }
1007 }
1008
1009 static void do_ppe_tasklet(unsigned long data)
1010 {
1011         unsigned int irqs = *MBOX_IGU1_ISR;
1012         *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1013
1014         if (irqs & (1 << RX_DMA_CH_AAL))
1015                 mailbox_aal_rx_handler();
1016         if (irqs & (1 << RX_DMA_CH_OAM))
1017                 mailbox_oam_rx_handler();
1018
1019         /* any valid tx irqs */
1020         if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1021                 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1022
1023         if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1024                 tasklet_schedule(&g_dma_tasklet);
1025         else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1026                 tasklet_schedule(&g_dma_tasklet);
1027         else
1028                 enable_irq(PPE_MAILBOX_IGU1_INT);
1029 }
1030
1031 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1032 {
1033         if ( !*MBOX_IGU1_ISR )
1034                 return IRQ_HANDLED;
1035
1036         disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1037         tasklet_schedule(&g_dma_tasklet);
1038
1039         return IRQ_HANDLED;
1040 }
1041
1042 static inline void mailbox_signal(unsigned int queue, int is_tx)
1043 {
1044         int count = 1000;
1045
1046         if ( is_tx ) {
1047                 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1048                         count--;
1049                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1050         } else {
1051                 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1052                         count--;
1053                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1054         }
1055
1056         ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1057 }
1058
1059 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1060 {
1061         struct clk *fpi_clk = clk_get_fpi();
1062         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1063         unsigned int qsb_qid = queue + FIRST_QSB_QID;
1064         union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1065         union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1066         unsigned int tmp;
1067
1068
1069         /*
1070          *  Peak Cell Rate (PCR) Limiter
1071          */
1072         if ( qos->txtp.max_pcr == 0 )
1073                 qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
1074         else {
1075                 /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1076                 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1077                 /*  check if overflow takes place   */
1078                 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1079         }
1080
1081 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1082         //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1083         //  Send packets to these two PVCs at same time, it trigger strange behavior.
1084         //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1085         //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1086         //  To work around, create UBR always with max_pcr.
1087         //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1088         if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1089                 int port = g_atm_priv_data.conn[queue].port;
1090                 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1091
1092                 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1093                 if ( tmp > QSB_TP_TS_MAX )
1094                         tmp = QSB_TP_TS_MAX;
1095                 else if ( tmp < 1 )
1096                         tmp = 1;
1097                 qsb_queue_parameter_table.bit.tp = tmp;
1098         }
1099 #endif
1100
1101         /*
1102          *  Weighted Fair Queueing Factor (WFQF)
1103          */
1104         switch ( qos->txtp.traffic_class ) {
1105         case ATM_CBR:
1106         case ATM_VBR_RT:
1107                 /*  real time queue gets weighted fair queueing bypass  */
1108                 qsb_queue_parameter_table.bit.wfqf = 0;
1109                 break;
1110         case ATM_VBR_NRT:
1111         case ATM_UBR_PLUS:
1112                 /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
1113                 /*  WFQF is maximum cell rate / garenteed cell rate                                             */
1114                 /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
1115                 if ( qos->txtp.min_pcr == 0 )
1116                         qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1117                 else {
1118                         tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1119                         if ( tmp == 0 )
1120                                 qsb_queue_parameter_table.bit.wfqf = 1;
1121                         else if ( tmp > QSB_WFQ_NONUBR_MAX )
1122                                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1123                         else
1124                                 qsb_queue_parameter_table.bit.wfqf = tmp;
1125                 }
1126                 break;
1127         default:
1128         case ATM_UBR:
1129                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1130         }
1131
1132         /*
1133          *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1134          */
1135         if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1136 #if 0
1137                 if ( qos->txtp.scr == 0 ) {
1138 #endif
1139                         /*  disable shaper  */
1140                         qsb_queue_vbr_parameter_table.bit.taus = 0;
1141                         qsb_queue_vbr_parameter_table.bit.ts = 0;
1142 #if 0
1143                 } else {
1144                         /*  Cell Loss Priority  (CLP)   */
1145                         if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1146                                 /*  CLP1    */
1147                                 qsb_queue_parameter_table.bit.vbr = 1;
1148                         else
1149                                 /*  CLP0    */
1150                                 qsb_queue_parameter_table.bit.vbr = 0;
1151                         /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1152                         tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1153                         qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1154                         tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1155                         if ( tmp == 0 )
1156                                 qsb_queue_vbr_parameter_table.bit.taus = 1;
1157                         else if ( tmp > QSB_TAUS_MAX )
1158                                 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1159                         else
1160                                 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1161                 }
1162 #endif
1163         } else {
1164                 qsb_queue_vbr_parameter_table.bit.taus = 0;
1165                 qsb_queue_vbr_parameter_table.bit.ts = 0;
1166         }
1167
1168         /*  Queue Parameter Table (QPT) */
1169         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1170         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1171         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1172         /*  Queue VBR Paramter Table (QVPT) */
1173         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1174         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1175         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1176
1177 }
1178
1179 static void qsb_global_set(void)
1180 {
1181         struct clk *fpi_clk = clk_get_fpi();
1182         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1183         int i;
1184         unsigned int tmp1, tmp2, tmp3;
1185
1186         *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1187         *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
1188         *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1189
1190         /*
1191          *  set SCT and SPT per port
1192          */
1193         for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1194                 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1195                         tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1196                         tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
1197                         tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
1198                         /*  carry over to integer part (?)  */
1199                         if ( tmp3 == (1 << 6) ) {
1200                                 tmp3 = 0;
1201                                 tmp2++;
1202                         }
1203                         if ( tmp2 == 0 )
1204                                 tmp2 = tmp3 = 1;
1205                         /*  1. set mask                                 */
1206                         /*  2. write value to data transfer register    */
1207                         /*  3. start the tranfer                        */
1208                         /*  SCT (FracRate)  */
1209                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1210                         *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
1211                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1212                                         QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1213                                         QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1214                                         QSB_RAMAC_TESEL_SET(i & 0x01);
1215                         /*  SPT (SBV + PN + IntRage)    */
1216                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1217                         *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1218                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1219                                 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1220                                 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1221                                 QSB_RAMAC_TESEL_SET(i & 0x01);
1222                 }
1223         }
1224 }
1225
1226 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1227 {
1228         struct htu_entry htu_entry = {
1229                 res1:       0x00,
1230                 clp:        is_retx ? 0x01 : 0x00,
1231                 pid:        g_atm_priv_data.conn[queue].port & 0x01,
1232                 vpi:        vpi,
1233                 vci:        vci,
1234                 pti:        0x00,
1235                 vld:        0x01};
1236
1237         struct htu_mask htu_mask = {
1238                 set:        0x01,
1239                 clp:        0x01,
1240                 pid_mask:   0x02,
1241                 vpi_mask:   0x00,
1242                 vci_mask:   0x0000,
1243                 pti_mask:   0x03,   //  0xx, user data
1244                 clear:      0x00};
1245
1246         struct htu_result htu_result = {
1247                 res1:       0x00,
1248                 cellid:     queue,
1249                 res2:       0x00,
1250                 type:       aal5 ? 0x00 : 0x01,
1251                 ven:        0x01,
1252                 res3:       0x00,
1253                 qid:        queue};
1254
1255         *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1256         *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1257         *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1258 }
1259
1260 static inline void clear_htu_entry(unsigned int queue)
1261 {
1262         HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1263 }
1264
1265 static void validate_oam_htu_entry(void)
1266 {
1267         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1268         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1269         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1270 }
1271
1272 static void invalidate_oam_htu_entry(void)
1273 {
1274         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1275         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1276         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1277 }
1278
1279 static inline int find_vpi(unsigned int vpi)
1280 {
1281         int i;
1282         unsigned int bit;
1283
1284         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1285                 if ( (g_atm_priv_data.conn_table & bit) != 0
1286                                 && g_atm_priv_data.conn[i].vcc != NULL
1287                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1288                         return i;
1289         }
1290
1291         return -1;
1292 }
1293
1294 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1295 {
1296         int i;
1297         unsigned int bit;
1298
1299         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1300                 if ( (g_atm_priv_data.conn_table & bit) != 0
1301                                 && g_atm_priv_data.conn[i].vcc != NULL
1302                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1303                                 && vci == g_atm_priv_data.conn[i].vcc->vci )
1304                         return i;
1305         }
1306
1307         return -1;
1308 }
1309
1310 static inline int find_vcc(struct atm_vcc *vcc)
1311 {
1312         int i;
1313         unsigned int bit;
1314
1315         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1316                 if ( (g_atm_priv_data.conn_table & bit) != 0
1317                         && g_atm_priv_data.conn[i].vcc == vcc )
1318                 return i;
1319         }
1320
1321         return -1;
1322 }
1323
1324 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1325 {
1326         int len = 0;
1327         unsigned int major, minor;
1328
1329         ops->fw_ver(&major, &minor);
1330
1331         len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1332         len += sprintf(buf + len, "    ATM (A1) firmware version %d.%d\n", major, minor);
1333
1334         return len;
1335 }
1336
1337 static inline void check_parameters(void)
1338 {
1339         /*  Please refer to Amazon spec 15.4 for setting these values.  */
1340         if ( qsb_tau < 1 )
1341                 qsb_tau = 1;
1342         if ( qsb_tstep < 1 )
1343                 qsb_tstep = 1;
1344         else if ( qsb_tstep > 4 )
1345                 qsb_tstep = 4;
1346         else if ( qsb_tstep == 3 )
1347                 qsb_tstep = 2;
1348
1349         /*  There is a delay between PPE write descriptor and descriptor is       */
1350         /*  really stored in memory. Host also has this delay when writing        */
1351         /*  descriptor. So PPE will use this value to determine if the write      */
1352         /*  operation makes effect.                                               */
1353         if ( write_descriptor_delay < 0 )
1354                 write_descriptor_delay = 0;
1355
1356         if ( aal5_fill_pattern < 0 )
1357                 aal5_fill_pattern = 0;
1358         else
1359                 aal5_fill_pattern &= 0xFF;
1360
1361         /*  Because of the limitation of length field in descriptors, the packet  */
1362         /*  size could not be larger than 64K minus overhead size.                */
1363         if ( aal5r_max_packet_size < 0 )
1364                 aal5r_max_packet_size = 0;
1365         else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1366                 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1367         if ( aal5r_min_packet_size < 0 )
1368                 aal5r_min_packet_size = 0;
1369         else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1370                 aal5r_min_packet_size = aal5r_max_packet_size;
1371         if ( aal5s_max_packet_size < 0 )
1372                 aal5s_max_packet_size = 0;
1373         else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1374                 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1375         if ( aal5s_min_packet_size < 0 )
1376                 aal5s_min_packet_size = 0;
1377         else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1378                 aal5s_min_packet_size = aal5s_max_packet_size;
1379
1380         if ( dma_rx_descriptor_length < 2 )
1381                 dma_rx_descriptor_length = 2;
1382         if ( dma_tx_descriptor_length < 2 )
1383                 dma_tx_descriptor_length = 2;
1384         if ( dma_rx_clp1_descriptor_threshold < 0 )
1385                 dma_rx_clp1_descriptor_threshold = 0;
1386         else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1387                 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1388
1389         if ( dma_tx_descriptor_length < 2 )
1390                 dma_tx_descriptor_length = 2;
1391 }
1392
1393 static inline int init_priv_data(void)
1394 {
1395         void *p;
1396         int i;
1397         struct rx_descriptor rx_desc = {0};
1398         struct sk_buff *skb;
1399         volatile struct tx_descriptor *p_tx_desc;
1400         struct sk_buff **ppskb;
1401
1402         //  clear atm private data structure
1403         memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1404
1405         //  allocate memory for RX (AAL) descriptors
1406         p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1407         if ( p == NULL )
1408                 return -1;
1409         dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1410         g_atm_priv_data.aal_desc_base = p;
1411         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1412         g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1413
1414         //  allocate memory for RX (OAM) descriptors
1415         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1416         if ( p == NULL )
1417                 return -1;
1418         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1419         g_atm_priv_data.oam_desc_base = p;
1420         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1421         g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1422
1423         //  allocate memory for RX (OAM) buffer
1424         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1425         if ( p == NULL )
1426                 return -1;
1427         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1428         g_atm_priv_data.oam_buf_base = p;
1429         p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1430         g_atm_priv_data.oam_buf = p;
1431
1432         //  allocate memory for TX descriptors
1433         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1434         if ( p == NULL )
1435                 return -1;
1436         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1437         g_atm_priv_data.tx_desc_base = p;
1438
1439         //  allocate memory for TX skb pointers
1440         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1441         if ( p == NULL )
1442                 return -1;
1443         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1444         g_atm_priv_data.tx_skb_base = p;
1445
1446         //  setup RX (AAL) descriptors
1447         rx_desc.own     = 1;
1448         rx_desc.c       = 0;
1449         rx_desc.sop     = 1;
1450         rx_desc.eop     = 1;
1451         rx_desc.byteoff = 0;
1452         rx_desc.id      = 0;
1453         rx_desc.err     = 0;
1454         rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1455         for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1456                 skb = alloc_skb_rx();
1457                 if ( skb == NULL )
1458                         return -1;
1459                 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1460                 g_atm_priv_data.aal_desc[i] = rx_desc;
1461         }
1462
1463         //  setup RX (OAM) descriptors
1464         p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1465         rx_desc.own     = 1;
1466         rx_desc.c       = 0;
1467         rx_desc.sop     = 1;
1468         rx_desc.eop     = 1;
1469         rx_desc.byteoff = 0;
1470         rx_desc.id      = 0;
1471         rx_desc.err     = 0;
1472         rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1473         for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1474                 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1475                 g_atm_priv_data.oam_desc[i] = rx_desc;
1476                 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1477         }
1478
1479         //  setup TX descriptors and skb pointers
1480         p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1481         ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1482         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1483                 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1484                 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1485                 g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
1486         }
1487
1488         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1489                 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1490
1491         return 0;
1492 }
1493
1494 static inline void clear_priv_data(void)
1495 {
1496         int i, j;
1497         struct sk_buff *skb;
1498
1499         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1500                 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1501                         for ( j = 0; j < dma_tx_descriptor_length; j++ )
1502                                 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1503                                         dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1504                 }
1505         }
1506
1507         if ( g_atm_priv_data.tx_skb_base != NULL )
1508                 kfree(g_atm_priv_data.tx_skb_base);
1509
1510         if ( g_atm_priv_data.tx_desc_base != NULL )
1511                 kfree(g_atm_priv_data.tx_desc_base);
1512
1513         if ( g_atm_priv_data.oam_buf_base != NULL )
1514                 kfree(g_atm_priv_data.oam_buf_base);
1515
1516         if ( g_atm_priv_data.oam_desc_base != NULL )
1517                 kfree(g_atm_priv_data.oam_desc_base);
1518
1519         if ( g_atm_priv_data.aal_desc_base != NULL ) {
1520                 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1521                         if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
1522                                 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1523                                 dev_kfree_skb_any(skb);
1524                         }
1525                 }
1526                 kfree(g_atm_priv_data.aal_desc_base);
1527         }
1528 }
1529
1530 static inline void init_rx_tables(void)
1531 {
1532         int i;
1533         struct wrx_queue_config wrx_queue_config = {0};
1534         struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1535         struct htu_entry htu_entry = {0};
1536         struct htu_result htu_result = {0};
1537         struct htu_mask htu_mask = {
1538                 set:        0x01,
1539                 clp:        0x01,
1540                 pid_mask:   0x00,
1541                 vpi_mask:   0x00,
1542                 vci_mask:   0x00,
1543                 pti_mask:   0x00,
1544                 clear:      0x00
1545         };
1546
1547         /*
1548          *  General Registers
1549          */
1550         *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1551 #ifndef CONFIG_AMAZON_SE
1552         *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
1553 #endif
1554         *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1555         *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
1556         *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1557
1558         /*
1559          *  WRX Queue Configuration Table
1560          */
1561         wrx_queue_config.uumask    = 0xFF;
1562         wrx_queue_config.cpimask   = 0xFF;
1563         wrx_queue_config.uuexp     = 0;
1564         wrx_queue_config.cpiexp    = 0;
1565         wrx_queue_config.mfs       = aal5r_max_packet_size;
1566         wrx_queue_config.oversize  = aal5r_max_packet_size;
1567         wrx_queue_config.undersize = aal5r_min_packet_size;
1568         wrx_queue_config.errdp     = aal5r_drop_error_packet;
1569         wrx_queue_config.dmach     = RX_DMA_CH_AAL;
1570         for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1571                 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1572         WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1573
1574         /*
1575          *  WRX DMA Channel Configuration Table
1576          */
1577         wrx_dma_channel_config.chrl   = 0;
1578         wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1579         wrx_dma_channel_config.mode   = 0;
1580         wrx_dma_channel_config.rlcfg  = 0;
1581
1582         wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1583         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1584         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1585
1586         wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1587         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1588         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1589
1590         /*
1591          *  HTU Tables
1592          */
1593         for (i = 0; i < MAX_PVC_NUMBER; i++) {
1594                 htu_result.qid = (unsigned int)i;
1595
1596                 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1597                 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1598                 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1599         }
1600
1601         /*  OAM HTU Entry   */
1602         htu_entry.vci = 0x03;
1603         htu_mask.pid_mask = 0x03;
1604         htu_mask.vpi_mask = 0xFF;
1605         htu_mask.vci_mask = 0x0000;
1606         htu_mask.pti_mask = 0x07;
1607         htu_result.cellid = OAM_RX_QUEUE;
1608         htu_result.type   = 1;
1609         htu_result.ven    = 1;
1610         htu_result.qid    = OAM_RX_QUEUE;
1611         *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1612         *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
1613         *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
1614         htu_entry.vci     = 0x04;
1615         htu_result.cellid = OAM_RX_QUEUE;
1616         htu_result.type   = 1;
1617         htu_result.ven    = 1;
1618         htu_result.qid    = OAM_RX_QUEUE;
1619         *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1620         *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
1621         *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
1622         htu_entry.vci     = 0x00;
1623         htu_entry.pti     = 0x04;
1624         htu_mask.vci_mask = 0xFFFF;
1625         htu_mask.pti_mask = 0x01;
1626         htu_result.cellid = OAM_RX_QUEUE;
1627         htu_result.type   = 1;
1628         htu_result.ven    = 1;
1629         htu_result.qid    = OAM_RX_QUEUE;
1630         *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1631         *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
1632         *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
1633 }
1634
1635 static inline void init_tx_tables(void)
1636 {
1637         int i;
1638         struct wtx_queue_config wtx_queue_config = {0};
1639         struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1640         struct wtx_port_config wtx_port_config = {
1641                 res1:   0,
1642                 qid:    0,
1643                 qsben:  1
1644         };
1645
1646         /*
1647          *  General Registers
1648          */
1649         *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
1650         *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1651         *CFG_WRDES_DELAY    = write_descriptor_delay;
1652
1653         /*
1654          *  WTX Port Configuration Table
1655          */
1656         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1657                 *WTX_PORT_CONFIG(i) = wtx_port_config;
1658
1659         /*
1660          *  WTX Queue Configuration Table
1661          */
1662         wtx_queue_config.qsben = 1;
1663         wtx_queue_config.sbid  = 0;
1664         for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1665                 wtx_queue_config.qsb_vcid = i;
1666                 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1667         }
1668
1669         /*
1670          *  WTX DMA Channel Configuration Table
1671          */
1672         wtx_dma_channel_config.mode   = 0;
1673         wtx_dma_channel_config.deslen = 0;
1674         wtx_dma_channel_config.desba  = 0;
1675         for ( i = 0; i < FIRST_QSB_QID; i++ )
1676                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1677         /*  normal connection   */
1678         wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1679         for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1680                 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1681                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1682         }
1683 }
1684
1685 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1686 {
1687         int i, j, port_num;
1688
1689         ASSERT(port_cell != NULL, "port_cell is NULL");
1690         ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1691
1692         for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1693                 if ( port_cell->tx_link_rate[j] > 0 )
1694                         break;
1695         for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1696                 g_atm_priv_data.port[i].tx_max_cell_rate =
1697                         port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1698
1699         qsb_global_set();
1700
1701         for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1702                 if ( g_atm_priv_data.conn[i].vcc != NULL )
1703                         set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1704
1705         //  TODO: ReTX set xdata_addr
1706         g_xdata_addr = xdata_addr;
1707
1708         g_showtime = 1;
1709
1710         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1711                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1712
1713 #if defined(CONFIG_VR9)
1714         IFX_REG_W32(0x0F, UTP_CFG);
1715 #endif
1716
1717         printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1718                 g_atm_priv_data.port[0].tx_max_cell_rate,
1719                 g_atm_priv_data.port[1].tx_max_cell_rate,
1720                 (unsigned int)g_xdata_addr);
1721
1722         return 0;
1723 }
1724
1725 static int atm_showtime_exit(void)
1726 {
1727         int port_num;
1728
1729         if ( !g_showtime )
1730                 return -1;
1731
1732 #if defined(CONFIG_VR9)
1733         IFX_REG_W32(0x00, UTP_CFG);
1734 #endif
1735
1736         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1737                 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1738
1739         g_showtime = 0;
1740         g_xdata_addr = NULL;
1741         printk("leave showtime\n");
1742         return 0;
1743 }
1744
1745 extern struct ltq_atm_ops ar9_ops;
1746 extern struct ltq_atm_ops vr9_ops;
1747 extern struct ltq_atm_ops danube_ops;
1748 extern struct ltq_atm_ops ase_ops;
1749
1750 static const struct of_device_id ltq_atm_match[] = {
1751 #ifdef CONFIG_DANUBE
1752         { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1753 #elif defined CONFIG_AMAZON_SE
1754         { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1755 #elif defined CONFIG_AR9
1756         { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1757 #elif defined CONFIG_VR9
1758         { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1759 #endif
1760         {},
1761 };
1762 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1763
1764 static int ltq_atm_probe(struct platform_device *pdev)
1765 {
1766         const struct of_device_id *match;
1767         struct ltq_atm_ops *ops = NULL;
1768         int ret;
1769         int port_num;
1770         struct port_cell_info port_cell = {0};
1771         char ver_str[256];
1772
1773         match = of_match_device(ltq_atm_match, &pdev->dev);
1774         if (!match) {
1775                 dev_err(&pdev->dev, "failed to find matching device\n");
1776                 return -ENOENT;
1777         }
1778         ops = (struct ltq_atm_ops *) match->data;
1779
1780         check_parameters();
1781
1782         ret = init_priv_data();
1783         if ( ret != 0 ) {
1784                 pr_err("INIT_PRIV_DATA_FAIL\n");
1785                 goto INIT_PRIV_DATA_FAIL;
1786         }
1787
1788         ops->init(pdev);
1789         init_rx_tables();
1790         init_tx_tables();
1791
1792         /*  create devices  */
1793         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1794                 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1795                 if ( !g_atm_priv_data.port[port_num].dev ) {
1796                         pr_err("failed to register atm device %d!\n", port_num);
1797                         ret = -EIO;
1798                         goto ATM_DEV_REGISTER_FAIL;
1799                 } else {
1800                         g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1801                         g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1802                         g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1803                         g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1804
1805 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1806                         atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1807 #endif
1808                 }
1809         }
1810
1811         /*  register interrupt handler  */
1812         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1813         if ( ret ) {
1814                 if ( ret == -EBUSY ) {
1815                         pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1816                 } else {
1817                         pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1818                 }
1819                 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1820         }
1821         disable_irq(PPE_MAILBOX_IGU1_INT);
1822
1823
1824         ret = ops->start(0);
1825         if ( ret ) {
1826                 pr_err("ifx_pp32_start fail!\n");
1827                 goto PP32_START_FAIL;
1828         }
1829
1830         port_cell.port_num = ATM_PORT_NUMBER;
1831         ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1832         if ( g_showtime ) {
1833                 atm_showtime_enter(&port_cell, &g_xdata_addr);
1834         } else {
1835                 qsb_global_set();
1836         }
1837
1838         validate_oam_htu_entry();
1839
1840         ifx_mei_atm_showtime_enter = atm_showtime_enter;
1841         ifx_mei_atm_showtime_exit  = atm_showtime_exit;
1842
1843         ifx_atm_version(ops, ver_str);
1844         printk(KERN_INFO "%s", ver_str);
1845         platform_set_drvdata(pdev, ops);
1846         printk("ifxmips_atm: ATM init succeed\n");
1847
1848         return 0;
1849
1850 PP32_START_FAIL:
1851         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1852 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1853 ATM_DEV_REGISTER_FAIL:
1854         while ( port_num-- > 0 )
1855                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1856 INIT_PRIV_DATA_FAIL:
1857         clear_priv_data();
1858         printk("ifxmips_atm: ATM init failed\n");
1859         return ret;
1860 }
1861
1862 static int ltq_atm_remove(struct platform_device *pdev)
1863 {
1864         int port_num;
1865         struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1866
1867         ifx_mei_atm_showtime_enter = NULL;
1868         ifx_mei_atm_showtime_exit  = NULL;
1869
1870         invalidate_oam_htu_entry();
1871
1872         ops->stop(0);
1873
1874         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1875
1876         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1877                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1878
1879         ops->shutdown();
1880
1881         clear_priv_data();
1882
1883         return 0;
1884 }
1885
1886 static struct platform_driver ltq_atm_driver = {
1887         .probe = ltq_atm_probe,
1888         .remove = ltq_atm_remove,
1889         .driver = {
1890                 .name = "atm",
1891                 .owner = THIS_MODULE,
1892                 .of_match_table = ltq_atm_match,
1893         },
1894 };
1895
1896 module_platform_driver(ltq_atm_driver);
1897
1898 MODULE_LICENSE("Dual BSD/GPL");