1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_core.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
48 #include <lantiq_soc.h>
50 #include "ifxmips_atm_core.h"
52 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
53 #define MODULE_PARM(a, b) module_param(a, int, 0)
56 \brief QSB cell delay variation due to concurrency
58 static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */
60 \brief QSB scheduler burst length
62 static int qsb_srvm = 0x0F; /* QSB scheduler burst length */
64 \brief QSB time step, all legal values are 1, 2, 4
66 static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */
69 \brief Write descriptor delay
71 static int write_descriptor_delay = 0x20; /* Write descriptor delay */
74 \brief AAL5 padding byte ('~')
76 static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */
78 \brief Max frame size for RX
80 static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */
82 \brief Min frame size for RX
84 static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */
86 \brief Max frame size for TX
88 static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */
90 \brief Min frame size for TX
92 static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */
94 \brief Drop error packet in RX path
96 static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */
99 \brief Number of descriptors per DMA RX channel
101 static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */
103 \brief Number of descriptors per DMA TX channel
105 static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */
107 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
109 static int dma_rx_clp1_descriptor_threshold = 38;
112 MODULE_PARM(qsb_tau, "i");
113 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
114 MODULE_PARM(qsb_srvm, "i");
115 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
116 MODULE_PARM(qsb_tstep, "i");
117 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
119 MODULE_PARM(write_descriptor_delay, "i");
120 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
122 MODULE_PARM(aal5_fill_pattern, "i");
123 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
124 MODULE_PARM(aal5r_max_packet_size, "i");
125 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
126 MODULE_PARM(aal5r_min_packet_size, "i");
127 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
128 MODULE_PARM(aal5s_max_packet_size, "i");
129 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
130 MODULE_PARM(aal5s_min_packet_size, "i");
131 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
132 MODULE_PARM(aal5r_drop_error_packet, "i");
133 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
135 MODULE_PARM(dma_rx_descriptor_length, "i");
136 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
137 MODULE_PARM(dma_tx_descriptor_length, "i");
138 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
139 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
145 * ####################################
147 * ####################################
150 #ifdef CONFIG_AMAZON_SE
151 #define ENABLE_LESS_CACHE_INV 1
152 #define LESS_CACHE_INV_LEN 96
155 #define DUMP_SKB_LEN ~0
160 * ####################################
162 * ####################################
168 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
169 static int ppe_open(struct atm_vcc *);
170 static void ppe_close(struct atm_vcc *);
171 static int ppe_send(struct atm_vcc *, struct sk_buff *);
172 static int ppe_send_oam(struct atm_vcc *, void *, int);
173 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
178 static inline void adsl_led_flash(void);
181 * 64-bit operation used by MIB calculation
183 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
186 * buffer manage functions
188 static inline struct sk_buff* alloc_skb_rx(void);
189 static inline struct sk_buff* alloc_skb_tx(unsigned int);
190 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
191 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
192 static inline int get_tx_desc(unsigned int);
195 * mailbox handler and signal function
197 static inline void mailbox_oam_rx_handler(void);
198 static inline void mailbox_aal_rx_handler(void);
199 static irqreturn_t mailbox_irq_handler(int, void *);
200 static inline void mailbox_signal(unsigned int, int);
201 static void do_ppe_tasklet(unsigned long);
202 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
205 * QSB & HTU setting functions
207 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
208 static void qsb_global_set(void);
209 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
210 static inline void clear_htu_entry(unsigned int);
211 static void validate_oam_htu_entry(void);
212 static void invalidate_oam_htu_entry(void);
215 * look up for connection ID
217 static inline int find_vpi(unsigned int);
218 static inline int find_vpivci(unsigned int, unsigned int);
219 static inline int find_vcc(struct atm_vcc *);
221 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
224 * Init & clean-up functions
226 static inline void check_parameters(void);
227 static inline int init_priv_data(void);
228 static inline void clear_priv_data(void);
229 static inline void init_rx_tables(void);
230 static inline void init_tx_tables(void);
235 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
236 extern void ifx_push_oam(unsigned char *);
238 static inline void ifx_push_oam(unsigned char *dummy) {}
241 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
242 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
243 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
245 extern int (*ifx_mei_atm_showtime_exit)(void);
246 extern int ifx_mei_atm_led_blink(void);
248 static inline int ifx_mei_atm_led_blink(void) { return 0; }
249 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
251 if ( is_showtime != NULL )
255 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
256 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
258 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
259 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
263 static struct atm_priv_data g_atm_priv_data;
265 static struct atmdev_ops g_ifx_atm_ops = {
270 .send_oam = ppe_send_oam,
271 .change_qos = ppe_change_qos,
272 .owner = THIS_MODULE,
275 static int g_showtime = 0;
276 static void *g_xdata_addr = NULL;
278 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
281 atm_cell_ifEntry_t mib_cell;
282 atm_aal5_ifEntry_t mib_aal5;
283 atm_aal5_vcc_x_t mib_vcc;
287 if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
288 || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
291 if ( _IOC_DIR(cmd) & _IOC_READ )
292 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
293 ret = !access_ok(arg, _IOC_SIZE(cmd));
295 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
297 else if ( _IOC_DIR(cmd) & _IOC_WRITE )
298 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
299 ret = !access_ok(arg, _IOC_SIZE(cmd));
301 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
307 case PPE_ATM_MIB_CELL: /* cell level MIB */
308 /* These MIB should be read at ARC side, now put zero only. */
309 mib_cell.ifHCInOctets_h = 0;
310 mib_cell.ifHCInOctets_l = 0;
311 mib_cell.ifHCOutOctets_h = 0;
312 mib_cell.ifHCOutOctets_l = 0;
313 mib_cell.ifInErrors = 0;
314 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
315 mib_cell.ifOutErrors = 0;
317 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
320 case PPE_ATM_MIB_AAL5: /* AAL5 MIB */
321 value = WAN_MIB_TABLE->wrx_total_byte;
322 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
323 g_atm_priv_data.prev_wrx_total_byte = value;
324 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
325 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
327 value = WAN_MIB_TABLE->wtx_total_byte;
328 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
329 g_atm_priv_data.prev_wtx_total_byte = value;
330 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
331 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
333 mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu;
334 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
335 mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu;
336 mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
337 mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu;
338 mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu;
340 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
343 case PPE_ATM_MIB_VCC: /* VCC related MIB */
344 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
345 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
347 mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
348 mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
349 mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */
350 ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
362 static int ppe_open(struct atm_vcc *vcc)
365 short vpi = vcc->vpi;
367 struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
369 int f_enable_irq = 0;
371 if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
372 return -EPROTONOSUPPORT;
374 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
375 /* check bandwidth */
376 if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
377 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
379 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
381 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
388 /* check existing vpi,vci */
389 conn = find_vpivci(vpi, vci);
395 /* check whether it need to enable irq */
396 if ( g_atm_priv_data.conn_table == 0 )
399 /* allocate connection */
400 for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
401 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
402 g_atm_priv_data.conn[conn].vcc = vcc;
406 if ( conn == MAX_PVC_NUMBER ) {
411 /* reserve bandwidth */
412 switch ( vcc->qos.txtp.traffic_class ) {
415 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
419 port->tx_current_cell_rate += vcc->qos.txtp.scr;
423 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
428 set_qsb(vcc, &vcc->qos, conn);
430 /* update atm_vcc structure */
431 vcc->itf = (int)vcc->dev->dev_data;
434 set_bit(ATM_VF_READY, &vcc->flags);
437 if ( f_enable_irq ) {
438 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
439 *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
441 enable_irq(PPE_MAILBOX_IGU1_INT);
445 WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
448 set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
450 *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
451 *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
459 static void ppe_close(struct atm_vcc *vcc)
463 struct connection *connection;
467 /* get connection id */
468 conn = find_vcc(vcc);
470 pr_err("can't find vcc\n");
473 connection = &g_atm_priv_data.conn[conn];
474 port = &g_atm_priv_data.port[connection->port];
477 clear_htu_entry(conn);
479 /* release connection */
480 connection->vcc = NULL;
481 connection->aal5_vcc_crc_err = 0;
482 connection->aal5_vcc_oversize_sdu = 0;
483 clear_bit(conn, &g_atm_priv_data.conn_table);
486 if ( g_atm_priv_data.conn_table == 0 )
487 disable_irq(PPE_MAILBOX_IGU1_INT);
489 /* release bandwidth */
490 switch ( vcc->qos.txtp.traffic_class )
494 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
498 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
502 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
506 /* wait for incoming packets to be processed by upper layers */
507 tasklet_unlock_wait(&g_dma_tasklet);
513 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
520 /* the len of the data without offset and header */
523 struct tx_descriptor reg_desc = {0};
524 struct tx_inband_header *header;
526 if ( vcc == NULL || skb == NULL )
530 conn = find_vcc(vcc);
537 pr_debug("not in showtime\n");
542 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
543 required = sizeof(*header) + byteoff;
544 if (!skb_clone_writable(skb, required)) {
548 if (skb_headroom(skb) < required)
549 expand_by = required - skb_headroom(skb);
551 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
553 printk("pskb_expand_head failed.\n");
554 atm_free_tx_skb_vcc(skb, vcc);
560 header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
563 if ( vcc->qos.aal == ATM_AAL5 ) {
564 /* setup inband trailer */
567 header->pad = aal5_fill_pattern;
570 /* setup cell header */
571 header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
572 header->pti = ATM_PTI_US0;
573 header->vci = vcc->vci;
574 header->vpi = vcc->vpi;
577 /* setup descriptor */
578 reg_desc.dataptr = (unsigned int)skb->data >> 2;
579 reg_desc.datalen = datalen;
580 reg_desc.byteoff = byteoff;
583 reg_desc.dataptr = (unsigned int)skb->data >> 2;
584 reg_desc.datalen = skb->len;
585 reg_desc.byteoff = byteoff;
591 reg_desc.sop = reg_desc.eop = 1;
593 spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
594 desc_base = get_tx_desc(conn);
595 if ( desc_base < 0 ) {
596 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
597 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
601 /* update descriptor send pointer */
602 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
603 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
604 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
606 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
609 atomic_inc(&vcc->stats->tx);
610 if ( vcc->qos.aal == ATM_AAL5 )
611 g_atm_priv_data.wtx_pdu++;
612 /* write discriptor to memory and write back cache */
613 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
614 dma_cache_wback((unsigned long)skb->data, skb->len);
616 mailbox_signal(conn, 1);
623 pr_err("FIND_VCC_FAIL\n");
624 g_atm_priv_data.wtx_err_pdu++;
625 dev_kfree_skb_any(skb);
629 if ( vcc->qos.aal == ATM_AAL5 )
630 g_atm_priv_data.wtx_drop_pdu++;
632 atomic_inc(&vcc->stats->tx_err);
633 dev_kfree_skb_any(skb);
637 /* operation and maintainance */
638 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
641 struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
644 struct tx_descriptor reg_desc = {0};
646 if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
647 && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
648 || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
649 && find_vpi(uni_cell_header->vpi) < 0) )
651 g_atm_priv_data.wtx_err_oam++;
656 pr_err("not in showtime\n");
657 g_atm_priv_data.wtx_drop_oam++;
661 conn = find_vcc(vcc);
663 pr_err("FIND_VCC_FAIL\n");
664 g_atm_priv_data.wtx_drop_oam++;
668 skb = alloc_skb_tx(CELL_SIZE);
670 pr_err("ALLOC_SKB_TX_FAIL\n");
671 g_atm_priv_data.wtx_drop_oam++;
674 skb_put(skb, CELL_SIZE);
675 memcpy(skb->data, cell, CELL_SIZE);
677 reg_desc.dataptr = (unsigned int)skb->data >> 2;
678 reg_desc.datalen = CELL_SIZE;
679 reg_desc.byteoff = 0;
684 reg_desc.sop = reg_desc.eop = 1;
686 desc_base = get_tx_desc(conn);
687 if ( desc_base < 0 ) {
688 dev_kfree_skb_any(skb);
689 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
690 g_atm_priv_data.wtx_drop_oam++;
695 atomic_inc(&vcc->stats->tx);
697 /* update descriptor send pointer */
698 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
699 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
700 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
702 /* write discriptor to memory and write back cache */
703 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
704 dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
706 mailbox_signal(conn, 1);
708 g_atm_priv_data.wtx_oam++;
714 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
718 if ( vcc == NULL || qos == NULL )
721 conn = find_vcc(vcc);
725 set_qsb(vcc, qos, conn);
730 static inline void adsl_led_flash(void)
732 ifx_mei_atm_led_blink();
737 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
739 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
740 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
741 * ret --- ppe_u64_t, pointer to a variable to hold result
745 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
747 ret->l = opt1.l + opt2;
748 if ( ret->l < opt1.l || ret->l < opt2 )
752 static inline struct sk_buff* alloc_skb_rx(void)
756 skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
758 /* must be burst length alignment */
759 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
760 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
761 /* pub skb in reserved area "skb->data - 4" */
762 *((struct sk_buff **)skb->data - 1) = skb;
763 /* write back and invalidate cache */
764 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
765 /* invalidate cache */
766 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
767 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
769 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
775 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
779 /* allocate memory including header and padding */
780 size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
781 size &= ~(DATA_BUFFER_ALIGNMENT - 1);
782 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
783 /* must be burst length alignment */
785 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
789 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
791 if ( vcc->pop != NULL )
794 dev_kfree_skb_any(skb);
797 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
799 unsigned int skb_dataptr;
802 skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
803 skb = *(struct sk_buff **)skb_dataptr;
805 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
806 ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
811 static inline int get_tx_desc(unsigned int conn)
814 struct connection *p_conn = &g_atm_priv_data.conn[conn];
816 if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
817 desc_base = p_conn->tx_desc_pos;
818 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
819 p_conn->tx_desc_pos = 0;
825 static void free_tx_ring(unsigned int queue)
829 struct connection *conn = &g_atm_priv_data.conn[queue];
835 spin_lock_irqsave(&conn->lock, flags);
837 for (i = 0; i < dma_tx_descriptor_length; i++) {
838 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
839 skb = conn->tx_skb[i];
840 conn->tx_skb[i] = NULL;
841 atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
844 spin_unlock_irqrestore(&conn->lock, flags);
847 static void mailbox_tx_handler(unsigned int queue_bitmap)
852 /* only get valid queues */
853 queue_bitmap &= g_atm_priv_data.conn_table;
855 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
856 if (queue_bitmap & bit)
861 static inline void mailbox_oam_rx_handler(void)
863 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
864 struct rx_descriptor reg_desc;
865 struct uni_cell_header *header;
870 for ( i = 0; i < vlddes; i++ ) {
871 unsigned int loop_count = 0;
874 reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
875 if ( ++loop_count == 1000 )
877 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
878 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
880 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
882 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
883 conn = find_vpivci(header->vpi, header->vci);
884 else if ( header->vci == 0x03 || header->vci == 0x04 )
885 conn = find_vpi(header->vpi);
889 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
890 vcc = g_atm_priv_data.conn[conn].vcc;
892 if ( vcc->push_oam != NULL )
893 vcc->push_oam(vcc, header);
895 ifx_push_oam((unsigned char *)header);
897 g_atm_priv_data.wrx_oam++;
901 g_atm_priv_data.wrx_drop_oam++;
903 reg_desc.byteoff = 0;
904 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
908 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
909 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
910 g_atm_priv_data.oam_desc_pos = 0;
912 dma_cache_inv((unsigned long)header, CELL_SIZE);
913 mailbox_signal(RX_DMA_CH_OAM, 0);
917 static inline void mailbox_aal_rx_handler(void)
919 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
920 struct rx_descriptor reg_desc;
923 struct sk_buff *skb, *new_skb;
924 struct rx_inband_trailer *trailer;
927 for ( i = 0; i < vlddes; i++ ) {
928 unsigned int loop_count = 0;
931 reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
932 if ( ++loop_count == 1000 )
934 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
935 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
939 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
940 vcc = g_atm_priv_data.conn[conn].vcc;
942 skb = get_skb_rx_pointer(reg_desc.dataptr);
944 if ( reg_desc.err ) {
945 if ( vcc->qos.aal == ATM_AAL5 ) {
946 trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
947 if ( trailer->stw_crc )
948 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
949 if ( trailer->stw_ovz )
950 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
951 g_atm_priv_data.wrx_drop_pdu++;
954 atomic_inc(&vcc->stats->rx_drop);
955 atomic_inc(&vcc->stats->rx_err);
958 } else if ( atm_charge(vcc, skb->truesize) ) {
959 new_skb = alloc_skb_rx();
960 if ( new_skb != NULL ) {
961 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
962 if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
963 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
966 skb_reserve(skb, reg_desc.byteoff);
967 skb_put(skb, reg_desc.datalen);
968 ATM_SKB(skb)->vcc = vcc;
972 if ( vcc->qos.aal == ATM_AAL5 )
973 g_atm_priv_data.wrx_pdu++;
975 atomic_inc(&vcc->stats->rx);
978 reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
980 atm_return(vcc, skb->truesize);
981 if ( vcc->qos.aal == ATM_AAL5 )
982 g_atm_priv_data.wrx_drop_pdu++;
984 atomic_inc(&vcc->stats->rx_drop);
987 if ( vcc->qos.aal == ATM_AAL5 )
988 g_atm_priv_data.wrx_drop_pdu++;
990 atomic_inc(&vcc->stats->rx_drop);
993 g_atm_priv_data.wrx_drop_pdu++;
996 reg_desc.byteoff = 0;
997 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1001 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1002 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1003 g_atm_priv_data.aal_desc_pos = 0;
1005 mailbox_signal(RX_DMA_CH_AAL, 0);
1009 static void do_ppe_tasklet(unsigned long data)
1011 unsigned int irqs = *MBOX_IGU1_ISR;
1012 *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1014 if (irqs & (1 << RX_DMA_CH_AAL))
1015 mailbox_aal_rx_handler();
1016 if (irqs & (1 << RX_DMA_CH_OAM))
1017 mailbox_oam_rx_handler();
1019 /* any valid tx irqs */
1020 if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1021 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1023 if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1024 tasklet_schedule(&g_dma_tasklet);
1025 else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1026 tasklet_schedule(&g_dma_tasklet);
1028 enable_irq(PPE_MAILBOX_IGU1_INT);
1031 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1033 if ( !*MBOX_IGU1_ISR )
1036 disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1037 tasklet_schedule(&g_dma_tasklet);
1042 static inline void mailbox_signal(unsigned int queue, int is_tx)
1047 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1049 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1051 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1053 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1056 ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1059 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1061 struct clk *fpi_clk = clk_get_fpi();
1062 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1063 unsigned int qsb_qid = queue + FIRST_QSB_QID;
1064 union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1065 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1070 * Peak Cell Rate (PCR) Limiter
1072 if ( qos->txtp.max_pcr == 0 )
1073 qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */
1075 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1076 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1077 /* check if overflow takes place */
1078 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1081 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1082 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1083 // Send packets to these two PVCs at same time, it trigger strange behavior.
1084 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1085 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1086 // To work around, create UBR always with max_pcr.
1087 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1088 if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1089 int port = g_atm_priv_data.conn[queue].port;
1090 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1092 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1093 if ( tmp > QSB_TP_TS_MAX )
1094 tmp = QSB_TP_TS_MAX;
1097 qsb_queue_parameter_table.bit.tp = tmp;
1102 * Weighted Fair Queueing Factor (WFQF)
1104 switch ( qos->txtp.traffic_class ) {
1107 /* real time queue gets weighted fair queueing bypass */
1108 qsb_queue_parameter_table.bit.wfqf = 0;
1112 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1113 /* WFQF is maximum cell rate / garenteed cell rate */
1114 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1115 if ( qos->txtp.min_pcr == 0 )
1116 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1118 tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1120 qsb_queue_parameter_table.bit.wfqf = 1;
1121 else if ( tmp > QSB_WFQ_NONUBR_MAX )
1122 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1124 qsb_queue_parameter_table.bit.wfqf = tmp;
1129 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1133 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1135 if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1137 if ( qos->txtp.scr == 0 ) {
1139 /* disable shaper */
1140 qsb_queue_vbr_parameter_table.bit.taus = 0;
1141 qsb_queue_vbr_parameter_table.bit.ts = 0;
1144 /* Cell Loss Priority (CLP) */
1145 if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1147 qsb_queue_parameter_table.bit.vbr = 1;
1150 qsb_queue_parameter_table.bit.vbr = 0;
1151 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1152 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1153 qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1154 tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1156 qsb_queue_vbr_parameter_table.bit.taus = 1;
1157 else if ( tmp > QSB_TAUS_MAX )
1158 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1160 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1164 qsb_queue_vbr_parameter_table.bit.taus = 0;
1165 qsb_queue_vbr_parameter_table.bit.ts = 0;
1168 /* Queue Parameter Table (QPT) */
1169 *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1170 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1171 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1172 /* Queue VBR Paramter Table (QVPT) */
1173 *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1174 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1175 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1179 static void qsb_global_set(void)
1181 struct clk *fpi_clk = clk_get_fpi();
1182 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1184 unsigned int tmp1, tmp2, tmp3;
1186 *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1187 *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm);
1188 *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1191 * set SCT and SPT per port
1193 for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1194 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1195 tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1196 tmp2 = tmp1 >> 6; /* integer value of Tsb */
1197 tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1198 /* carry over to integer part (?) */
1199 if ( tmp3 == (1 << 6) ) {
1206 /* 2. write value to data transfer register */
1207 /* 3. start the tranfer */
1208 /* SCT (FracRate) */
1209 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1210 *QSB_RTD = QSB_RTD_TTV_SET(tmp3);
1211 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1212 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1213 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1214 QSB_RAMAC_TESEL_SET(i & 0x01);
1215 /* SPT (SBV + PN + IntRage) */
1216 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1217 *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1218 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1219 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1220 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1221 QSB_RAMAC_TESEL_SET(i & 0x01);
1226 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1228 struct htu_entry htu_entry = {
1230 clp: is_retx ? 0x01 : 0x00,
1231 pid: g_atm_priv_data.conn[queue].port & 0x01,
1237 struct htu_mask htu_mask = {
1243 pti_mask: 0x03, // 0xx, user data
1246 struct htu_result htu_result = {
1250 type: aal5 ? 0x00 : 0x01,
1255 *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1256 *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1257 *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1260 static inline void clear_htu_entry(unsigned int queue)
1262 HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1265 static void validate_oam_htu_entry(void)
1267 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1268 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1269 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1272 static void invalidate_oam_htu_entry(void)
1274 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1275 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1276 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1279 static inline int find_vpi(unsigned int vpi)
1284 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1285 if ( (g_atm_priv_data.conn_table & bit) != 0
1286 && g_atm_priv_data.conn[i].vcc != NULL
1287 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1294 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1299 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1300 if ( (g_atm_priv_data.conn_table & bit) != 0
1301 && g_atm_priv_data.conn[i].vcc != NULL
1302 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1303 && vci == g_atm_priv_data.conn[i].vcc->vci )
1310 static inline int find_vcc(struct atm_vcc *vcc)
1315 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1316 if ( (g_atm_priv_data.conn_table & bit) != 0
1317 && g_atm_priv_data.conn[i].vcc == vcc )
1324 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1327 unsigned int major, minor;
1329 ops->fw_ver(&major, &minor);
1331 len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1332 len += sprintf(buf + len, " ATM (A1) firmware version %d.%d\n", major, minor);
1337 static inline void check_parameters(void)
1339 /* Please refer to Amazon spec 15.4 for setting these values. */
1342 if ( qsb_tstep < 1 )
1344 else if ( qsb_tstep > 4 )
1346 else if ( qsb_tstep == 3 )
1349 /* There is a delay between PPE write descriptor and descriptor is */
1350 /* really stored in memory. Host also has this delay when writing */
1351 /* descriptor. So PPE will use this value to determine if the write */
1352 /* operation makes effect. */
1353 if ( write_descriptor_delay < 0 )
1354 write_descriptor_delay = 0;
1356 if ( aal5_fill_pattern < 0 )
1357 aal5_fill_pattern = 0;
1359 aal5_fill_pattern &= 0xFF;
1361 /* Because of the limitation of length field in descriptors, the packet */
1362 /* size could not be larger than 64K minus overhead size. */
1363 if ( aal5r_max_packet_size < 0 )
1364 aal5r_max_packet_size = 0;
1365 else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1366 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1367 if ( aal5r_min_packet_size < 0 )
1368 aal5r_min_packet_size = 0;
1369 else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1370 aal5r_min_packet_size = aal5r_max_packet_size;
1371 if ( aal5s_max_packet_size < 0 )
1372 aal5s_max_packet_size = 0;
1373 else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1374 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1375 if ( aal5s_min_packet_size < 0 )
1376 aal5s_min_packet_size = 0;
1377 else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1378 aal5s_min_packet_size = aal5s_max_packet_size;
1380 if ( dma_rx_descriptor_length < 2 )
1381 dma_rx_descriptor_length = 2;
1382 if ( dma_tx_descriptor_length < 2 )
1383 dma_tx_descriptor_length = 2;
1384 if ( dma_rx_clp1_descriptor_threshold < 0 )
1385 dma_rx_clp1_descriptor_threshold = 0;
1386 else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1387 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1389 if ( dma_tx_descriptor_length < 2 )
1390 dma_tx_descriptor_length = 2;
1393 static inline int init_priv_data(void)
1397 struct rx_descriptor rx_desc = {0};
1398 struct sk_buff *skb;
1399 volatile struct tx_descriptor *p_tx_desc;
1400 struct sk_buff **ppskb;
1402 // clear atm private data structure
1403 memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1405 // allocate memory for RX (AAL) descriptors
1406 p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1409 dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1410 g_atm_priv_data.aal_desc_base = p;
1411 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1412 g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1414 // allocate memory for RX (OAM) descriptors
1415 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1418 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1419 g_atm_priv_data.oam_desc_base = p;
1420 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1421 g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1423 // allocate memory for RX (OAM) buffer
1424 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1427 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1428 g_atm_priv_data.oam_buf_base = p;
1429 p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1430 g_atm_priv_data.oam_buf = p;
1432 // allocate memory for TX descriptors
1433 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1436 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1437 g_atm_priv_data.tx_desc_base = p;
1439 // allocate memory for TX skb pointers
1440 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1443 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1444 g_atm_priv_data.tx_skb_base = p;
1446 // setup RX (AAL) descriptors
1451 rx_desc.byteoff = 0;
1454 rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1455 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1456 skb = alloc_skb_rx();
1459 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1460 g_atm_priv_data.aal_desc[i] = rx_desc;
1463 // setup RX (OAM) descriptors
1464 p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1469 rx_desc.byteoff = 0;
1472 rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1473 for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1474 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1475 g_atm_priv_data.oam_desc[i] = rx_desc;
1476 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1479 // setup TX descriptors and skb pointers
1480 p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1481 ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1482 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1483 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1484 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1485 g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
1488 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1489 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1494 static inline void clear_priv_data(void)
1497 struct sk_buff *skb;
1499 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1500 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1501 for ( j = 0; j < dma_tx_descriptor_length; j++ )
1502 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1503 dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1507 if ( g_atm_priv_data.tx_skb_base != NULL )
1508 kfree(g_atm_priv_data.tx_skb_base);
1510 if ( g_atm_priv_data.tx_desc_base != NULL )
1511 kfree(g_atm_priv_data.tx_desc_base);
1513 if ( g_atm_priv_data.oam_buf_base != NULL )
1514 kfree(g_atm_priv_data.oam_buf_base);
1516 if ( g_atm_priv_data.oam_desc_base != NULL )
1517 kfree(g_atm_priv_data.oam_desc_base);
1519 if ( g_atm_priv_data.aal_desc_base != NULL ) {
1520 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1521 if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized
1522 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1523 dev_kfree_skb_any(skb);
1526 kfree(g_atm_priv_data.aal_desc_base);
1530 static inline void init_rx_tables(void)
1533 struct wrx_queue_config wrx_queue_config = {0};
1534 struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1535 struct htu_entry htu_entry = {0};
1536 struct htu_result htu_result = {0};
1537 struct htu_mask htu_mask = {
1550 *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1551 #ifndef CONFIG_AMAZON_SE
1552 *CFG_WRX_QNUM = MAX_QUEUE_NUMBER;
1554 *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1555 *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1;
1556 *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1559 * WRX Queue Configuration Table
1561 wrx_queue_config.uumask = 0xFF;
1562 wrx_queue_config.cpimask = 0xFF;
1563 wrx_queue_config.uuexp = 0;
1564 wrx_queue_config.cpiexp = 0;
1565 wrx_queue_config.mfs = aal5r_max_packet_size;
1566 wrx_queue_config.oversize = aal5r_max_packet_size;
1567 wrx_queue_config.undersize = aal5r_min_packet_size;
1568 wrx_queue_config.errdp = aal5r_drop_error_packet;
1569 wrx_queue_config.dmach = RX_DMA_CH_AAL;
1570 for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1571 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1572 WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1575 * WRX DMA Channel Configuration Table
1577 wrx_dma_channel_config.chrl = 0;
1578 wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1579 wrx_dma_channel_config.mode = 0;
1580 wrx_dma_channel_config.rlcfg = 0;
1582 wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1583 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1584 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1586 wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1587 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1588 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1593 for (i = 0; i < MAX_PVC_NUMBER; i++) {
1594 htu_result.qid = (unsigned int)i;
1596 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1597 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1598 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1602 htu_entry.vci = 0x03;
1603 htu_mask.pid_mask = 0x03;
1604 htu_mask.vpi_mask = 0xFF;
1605 htu_mask.vci_mask = 0x0000;
1606 htu_mask.pti_mask = 0x07;
1607 htu_result.cellid = OAM_RX_QUEUE;
1608 htu_result.type = 1;
1610 htu_result.qid = OAM_RX_QUEUE;
1611 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1612 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask;
1613 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry;
1614 htu_entry.vci = 0x04;
1615 htu_result.cellid = OAM_RX_QUEUE;
1616 htu_result.type = 1;
1618 htu_result.qid = OAM_RX_QUEUE;
1619 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1620 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask;
1621 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry;
1622 htu_entry.vci = 0x00;
1623 htu_entry.pti = 0x04;
1624 htu_mask.vci_mask = 0xFFFF;
1625 htu_mask.pti_mask = 0x01;
1626 htu_result.cellid = OAM_RX_QUEUE;
1627 htu_result.type = 1;
1629 htu_result.qid = OAM_RX_QUEUE;
1630 *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1631 *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask;
1632 *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry;
1635 static inline void init_tx_tables(void)
1638 struct wtx_queue_config wtx_queue_config = {0};
1639 struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1640 struct wtx_port_config wtx_port_config = {
1649 *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER;
1650 *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1651 *CFG_WRDES_DELAY = write_descriptor_delay;
1654 * WTX Port Configuration Table
1656 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1657 *WTX_PORT_CONFIG(i) = wtx_port_config;
1660 * WTX Queue Configuration Table
1662 wtx_queue_config.qsben = 1;
1663 wtx_queue_config.sbid = 0;
1664 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1665 wtx_queue_config.qsb_vcid = i;
1666 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1670 * WTX DMA Channel Configuration Table
1672 wtx_dma_channel_config.mode = 0;
1673 wtx_dma_channel_config.deslen = 0;
1674 wtx_dma_channel_config.desba = 0;
1675 for ( i = 0; i < FIRST_QSB_QID; i++ )
1676 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1677 /* normal connection */
1678 wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1679 for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1680 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1681 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1685 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1689 ASSERT(port_cell != NULL, "port_cell is NULL");
1690 ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1692 for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1693 if ( port_cell->tx_link_rate[j] > 0 )
1695 for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1696 g_atm_priv_data.port[i].tx_max_cell_rate =
1697 port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1701 for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1702 if ( g_atm_priv_data.conn[i].vcc != NULL )
1703 set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1705 // TODO: ReTX set xdata_addr
1706 g_xdata_addr = xdata_addr;
1710 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1711 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1713 #if defined(CONFIG_VR9)
1714 IFX_REG_W32(0x0F, UTP_CFG);
1717 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1718 g_atm_priv_data.port[0].tx_max_cell_rate,
1719 g_atm_priv_data.port[1].tx_max_cell_rate,
1720 (unsigned int)g_xdata_addr);
1725 static int atm_showtime_exit(void)
1732 #if defined(CONFIG_VR9)
1733 IFX_REG_W32(0x00, UTP_CFG);
1736 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1737 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1740 g_xdata_addr = NULL;
1741 printk("leave showtime\n");
1745 extern struct ltq_atm_ops ar9_ops;
1746 extern struct ltq_atm_ops vr9_ops;
1747 extern struct ltq_atm_ops danube_ops;
1748 extern struct ltq_atm_ops ase_ops;
1750 static const struct of_device_id ltq_atm_match[] = {
1751 #ifdef CONFIG_DANUBE
1752 { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1753 #elif defined CONFIG_AMAZON_SE
1754 { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1755 #elif defined CONFIG_AR9
1756 { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1757 #elif defined CONFIG_VR9
1758 { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1762 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1764 static int ltq_atm_probe(struct platform_device *pdev)
1766 const struct of_device_id *match;
1767 struct ltq_atm_ops *ops = NULL;
1770 struct port_cell_info port_cell = {0};
1773 match = of_match_device(ltq_atm_match, &pdev->dev);
1775 dev_err(&pdev->dev, "failed to find matching device\n");
1778 ops = (struct ltq_atm_ops *) match->data;
1782 ret = init_priv_data();
1784 pr_err("INIT_PRIV_DATA_FAIL\n");
1785 goto INIT_PRIV_DATA_FAIL;
1792 /* create devices */
1793 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1794 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1795 if ( !g_atm_priv_data.port[port_num].dev ) {
1796 pr_err("failed to register atm device %d!\n", port_num);
1798 goto ATM_DEV_REGISTER_FAIL;
1800 g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1801 g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1802 g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1803 g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1805 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1806 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1811 /* register interrupt handler */
1812 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1813 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1815 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1818 if ( ret == -EBUSY ) {
1819 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1821 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1823 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1825 disable_irq(PPE_MAILBOX_IGU1_INT);
1828 ret = ops->start(0);
1830 pr_err("ifx_pp32_start fail!\n");
1831 goto PP32_START_FAIL;
1834 port_cell.port_num = ATM_PORT_NUMBER;
1835 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1837 atm_showtime_enter(&port_cell, &g_xdata_addr);
1842 validate_oam_htu_entry();
1844 ifx_mei_atm_showtime_enter = atm_showtime_enter;
1845 ifx_mei_atm_showtime_exit = atm_showtime_exit;
1847 ifx_atm_version(ops, ver_str);
1848 printk(KERN_INFO "%s", ver_str);
1849 platform_set_drvdata(pdev, ops);
1850 printk("ifxmips_atm: ATM init succeed\n");
1855 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1856 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1857 ATM_DEV_REGISTER_FAIL:
1858 while ( port_num-- > 0 )
1859 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1860 INIT_PRIV_DATA_FAIL:
1862 printk("ifxmips_atm: ATM init failed\n");
1866 static int ltq_atm_remove(struct platform_device *pdev)
1869 struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1871 ifx_mei_atm_showtime_enter = NULL;
1872 ifx_mei_atm_showtime_exit = NULL;
1874 invalidate_oam_htu_entry();
1878 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1880 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1881 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1890 static struct platform_driver ltq_atm_driver = {
1891 .probe = ltq_atm_probe,
1892 .remove = ltq_atm_remove,
1895 .owner = THIS_MODULE,
1896 .of_match_table = ltq_atm_match,
1900 module_platform_driver(ltq_atm_driver);
1902 MODULE_LICENSE("Dual BSD/GPL");