package/kernel/lantiq/ltq-adsl/patches/100-dsl_compat.patch

   1 --- a/src/include/drv_dsl_cpe_device_danube.h
   2 +++ b/src/include/drv_dsl_cpe_device_danube.h
   3 @@ -24,7 +24,7 @@
   4     #include "drv_dsl_cpe_simulator_danube.h"
   5  #else
   6  /* Include for the low level driver interface header file */
   7 -#include "asm/ifx/ifx_mei_bsp.h"
   8 +#include "ifxmips_mei_interface.h"
   9  #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
  10
  11  #define DSL_MAX_LINE_NUMBER 1
  12 --- a/src/common/drv_dsl_cpe_os_linux.c
  13 +++ b/src/common/drv_dsl_cpe_os_linux.c
  14 @@ -11,6 +11,7 @@
  15  #ifdef __LINUX__
  16
  17  #define DSL_INTERN
  18 +#include <linux/device.h>
  19
  20  #include "drv_dsl_cpe_api.h"
  21  #include "drv_dsl_cpe_api_ioctl.h"
  22 @@ -34,9 +35,13 @@ static const char* dsl_cpe_api_version =
  23  static DSL_ssize_t DSL_DRV_Write(DSL_DRV_file_t *pFile, const DSL_char_t * pBuf,
  24                                   DSL_DRV_size_t nSize, DSL_DRV_offset_t * pLoff);
  25
  26 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  27  static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,
  28                           DSL_uint_t nCommand, unsigned long nArg);
  29 -
  30 +#else
  31 +static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,
  32 +                         DSL_uint_t nCommand, unsigned long nArg);
  33 +#endif
  34  static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
  35
  36  static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
  37 @@ -72,7 +77,11 @@ static struct file_operations dslCpeApiO
  38     open:    DSL_DRV_Open,
  39     release: DSL_DRV_Release,
  40     write:   DSL_DRV_Write,
  41 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  42     ioctl:   DSL_DRV_Ioctls,
  43 +#else
  44 +   unlocked_ioctl:   DSL_DRV_Ioctls,
  45 +#endif
  46     poll:    DSL_DRV_Poll
  47  };
  48  #else
  49 @@ -168,10 +177,17 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV
  50     \return  Success or failure.
  51     \ingroup Internal
  52  */
  53 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  54  static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode,
  55     DSL_DRV_file_t * pFile,
  56     DSL_uint_t nCommand,
  57     unsigned long nArg)
  58 +#else
  59 +static DSL_int_t DSL_DRV_Ioctls(
  60 +   DSL_DRV_file_t * pFile,
  61 +   DSL_uint_t nCommand,
  62 +   unsigned long nArg)
  63 +#endif
  64  {
  65     DSL_int_t nErr=0;
  66     DSL_boolean_t bIsInKernel;
  67 @@ -216,16 +232,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_
  68           }
  69        }
  70     }
  71 -
  72 -   if (pINode == DSL_NULL)
  73 -   {
  74 -      bIsInKernel = DSL_TRUE;
  75 -   }
  76 -   else
  77 -   {
  78 -      bIsInKernel = DSL_FALSE;
  79 -   }
  80 -
  81 +   bIsInKernel = DSL_FALSE;
  82     if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||
  83          (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||
  84          (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||
  85 @@ -828,12 +835,19 @@ DSL_int32_t DSL_DRV_ThreadShutdown(
  86
  87  DSL_uint32_t DSL_DRV_SysTimeGet(DSL_uint32_t nOffset)
  88  {
  89 -   struct timeval tv;
  90     DSL_uint32_t nTime = 0;
  91 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
  92 +   struct timeval tv;
  93
  94     memset(&tv, 0, sizeof(tv));
  95     do_gettimeofday(&tv);
  96     nTime = (DSL_uint32_t)tv.tv_sec;
  97 +#else
  98 +   struct timespec64 now;
  99 +
 100 +   ktime_get_real_ts64(&now);
 101 +   nTime = (DSL_uint32_t)now.tv_sec;
 102 +#endif
 103
 104     if ( (nOffset == 0) || (nOffset > nTime) )
 105     {
 106 @@ -1058,6 +1072,7 @@ static void DSL_DRV_DebugInit(void)
 107  /* Entry point of driver */
 108  int __init DSL_ModuleInit(void)
 109  {
 110 +   struct class *dsl_class;
 111     DSL_int_t i;
 112
 113     printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
 114 @@ -1104,7 +1119,8 @@ int __init DSL_ModuleInit(void)
 115     }
 116
 117     DSL_DRV_DevNodeInit();
 118 -
 119 +   dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
 120 +   device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
 121     return 0;
 122  }
 123
 124 --- a/src/include/drv_dsl_cpe_os_linux.h
 125 +++ b/src/include/drv_dsl_cpe_os_linux.h
 126 @@ -16,18 +16,18 @@
 127     extern "C" {
 128  #endif
 129
 130 -#include <asm/ioctl.h>
 131 -#include <linux/autoconf.h>
 132  #include <linux/module.h>
 133  #include <linux/kernel.h>
 134  #include <linux/init.h>
 135  #include <linux/ctype.h>
 136  #include <linux/version.h>
 137  #include <linux/spinlock.h>
 138 +#include <linux/sched.h>
 139
 140 -
 141 -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
 142 -   #include <linux/utsrelease.h>
 143 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
 144 +#include <linux/utsrelease.h>
 145 +#else
 146 +#include <generated/utsrelease.h>
 147  #endif
 148
 149  #include <linux/types.h>
 150 @@ -39,7 +39,8 @@
 151  #include <linux/delay.h>
 152  #include <linux/poll.h>
 153  #include <asm/uaccess.h>
 154 -#include <linux/smp_lock.h>
 155 +//#include <linux/smp_lock.h>
 156 +#include <asm/ioctl.h>
 157
 158  #ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
 159  /** IFXOS includes*/
 160 --- /dev/null
 161 +++ b/src/include/ifxmips_mei_interface.h
 162 @@ -0,0 +1,702 @@
 163 +/******************************************************************************
 164 +
 165 +                               Copyright (c) 2009
 166 +                            Infineon Technologies AG
 167 +                     Am Campeon 1-12; 81726 Munich, Germany
 168 +
 169 +  For licensing information, see the file 'LICENSE' in the root folder of
 170 +  this software module.
 171 +
 172 +******************************************************************************/
 173 +
 174 +#ifndef IFXMIPS_MEI_H
 175 +#define IFXMIPS_MEI_H
 176 +
 177 +//#define CONFIG_AMAZON_SE 1
 178 +//#define CONFIG_DANUBE 1
 179 +//#define CONFIG_AR9 1
 180 +
 181 +#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
 182 +#error Platform undefined!!!
 183 +#endif
 184 +
 185 +#ifdef IFX_MEI_BSP
 186 +/** This is the character datatype. */
 187 +typedef char            DSL_char_t;
 188 +/** This is the unsigned 8-bit datatype. */
 189 +typedef unsigned char   DSL_uint8_t;
 190 +/** This is the signed 8-bit datatype. */
 191 +typedef signed char     DSL_int8_t;
 192 +/** This is the unsigned 16-bit datatype. */
 193 +typedef unsigned short  DSL_uint16_t;
 194 +/** This is the signed 16-bit datatype. */
 195 +typedef signed short    DSL_int16_t;
 196 +/** This is the unsigned 32-bit datatype. */
 197 +typedef unsigned long   DSL_uint32_t;
 198 +/** This is the signed 32-bit datatype. */
 199 +typedef signed long     DSL_int32_t;
 200 +/** This is the float datatype. */
 201 +typedef float           DSL_float_t;
 202 +/** This is the void datatype. */
 203 +typedef void            DSL_void_t;
 204 +/** integer type, width is depending on processor arch */
 205 +typedef int             DSL_int_t;
 206 +/** unsigned integer type, width is depending on processor arch */
 207 +typedef unsigned int    DSL_uint_t;
 208 +typedef struct file DSL_DRV_file_t;
 209 +typedef struct inode DSL_DRV_inode_t;
 210 +
 211 +/**
 212 + *    Defines all possible CMV groups
 213 + *    */
 214 +typedef enum {
 215 +   DSL_CMV_GROUP_CNTL = 1,
 216 +   DSL_CMV_GROUP_STAT = 2,
 217 +   DSL_CMV_GROUP_INFO = 3,
 218 +   DSL_CMV_GROUP_TEST = 4,
 219 +   DSL_CMV_GROUP_OPTN = 5,
 220 +   DSL_CMV_GROUP_RATE = 6,
 221 +   DSL_CMV_GROUP_PLAM = 7,
 222 +   DSL_CMV_GROUP_CNFG = 8
 223 +} DSL_CmvGroup_t;
 224 +/**
 225 + *    Defines all opcode types
 226 + *    */
 227 +typedef enum {
 228 +   H2D_CMV_READ = 0x00,
 229 +   H2D_CMV_WRITE = 0x04,
 230 +   H2D_CMV_INDICATE_REPLY = 0x10,
 231 +   H2D_ERROR_OPCODE_UNKNOWN =0x20,
 232 +   H2D_ERROR_CMV_UNKNOWN =0x30,
 233 +
 234 +   D2H_CMV_READ_REPLY =0x01,
 235 +   D2H_CMV_WRITE_REPLY = 0x05,
 236 +   D2H_CMV_INDICATE = 0x11,
 237 +   D2H_ERROR_OPCODE_UNKNOWN = 0x21,
 238 +   D2H_ERROR_CMV_UNKNOWN = 0x31,
 239 +   D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
 240 +   D2H_ERROR_CMV_WRITE_ONLY = 0x51,
 241 +   D2H_ERROR_CMV_READ_ONLY = 0x61,
 242 +
 243 +   H2D_DEBUG_READ_DM = 0x02,
 244 +   H2D_DEBUG_READ_PM = 0x06,
 245 +   H2D_DEBUG_WRITE_DM = 0x0a,
 246 +   H2D_DEBUG_WRITE_PM = 0x0e,
 247 +
 248 +   D2H_DEBUG_READ_DM_REPLY = 0x03,
 249 +   D2H_DEBUG_READ_FM_REPLY = 0x07,
 250 +   D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
 251 +   D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
 252 +   D2H_ERROR_ADDR_UNKNOWN = 0x33,
 253 +
 254 +   D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
 255 +} DSL_CmvOpcode_t;
 256 +
 257 +/* mutex macros */
 258 +#define MEI_MUTEX_INIT(id,flag) \
 259 +        sema_init(&id,flag)
 260 +#define MEI_MUTEX_LOCK(id) \
 261 +        down_interruptible(&id)
 262 +#define MEI_MUTEX_UNLOCK(id) \
 263 +        up(&id)
 264 +#define MEI_WAIT(ms) \
 265 +        {\
 266 +                set_current_state(TASK_INTERRUPTIBLE);\
 267 +                schedule_timeout(ms);\
 268 +        }
 269 +#define MEI_INIT_WAKELIST(name,queue) \
 270 +        init_waitqueue_head(&queue)
 271 +
 272 +/* wait for an event, timeout is measured in ms */
 273 +#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
 274 +        interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
 275 +#define MEI_WAKEUP_EVENT(ev)\
 276 +        wake_up_interruptible(&ev)
 277 +#endif /* IFX_MEI_BSP */
 278 +
 279 +/***   Register address offsets, relative to MEI_SPACE_ADDRESS ***/
 280 +#define ME_DX_DATA                             (0x0000)
 281 +#define        ME_VERSION                              (0x0004)
 282 +#define        ME_ARC_GP_STAT                          (0x0008)
 283 +#define ME_DX_STAT                             (0x000C)
 284 +#define        ME_DX_AD                                (0x0010)
 285 +#define ME_DX_MWS                              (0x0014)
 286 +#define        ME_ME2ARC_INT                           (0x0018)
 287 +#define        ME_ARC2ME_STAT                          (0x001C)
 288 +#define        ME_ARC2ME_MASK                          (0x0020)
 289 +#define        ME_DBG_WR_AD                            (0x0024)
 290 +#define ME_DBG_RD_AD                           (0x0028)
 291 +#define        ME_DBG_DATA                             (0x002C)
 292 +#define        ME_DBG_DECODE                           (0x0030)
 293 +#define ME_CONFIG                              (0x0034)
 294 +#define        ME_RST_CTRL                             (0x0038)
 295 +#define        ME_DBG_MASTER                           (0x003C)
 296 +#define        ME_CLK_CTRL                             (0x0040)
 297 +#define        ME_BIST_CTRL                            (0x0044)
 298 +#define        ME_BIST_STAT                            (0x0048)
 299 +#define ME_XDATA_BASE_SH                       (0x004c)
 300 +#define ME_XDATA_BASE                          (0x0050)
 301 +#define ME_XMEM_BAR_BASE                       (0x0054)
 302 +#define ME_XMEM_BAR0                           (0x0054)
 303 +#define ME_XMEM_BAR1                           (0x0058)
 304 +#define ME_XMEM_BAR2                           (0x005C)
 305 +#define ME_XMEM_BAR3                           (0x0060)
 306 +#define ME_XMEM_BAR4                           (0x0064)
 307 +#define ME_XMEM_BAR5                           (0x0068)
 308 +#define ME_XMEM_BAR6                           (0x006C)
 309 +#define ME_XMEM_BAR7                           (0x0070)
 310 +#define ME_XMEM_BAR8                           (0x0074)
 311 +#define ME_XMEM_BAR9                           (0x0078)
 312 +#define ME_XMEM_BAR10                          (0x007C)
 313 +#define ME_XMEM_BAR11                          (0x0080)
 314 +#define ME_XMEM_BAR12                          (0x0084)
 315 +#define ME_XMEM_BAR13                          (0x0088)
 316 +#define ME_XMEM_BAR14                          (0x008C)
 317 +#define ME_XMEM_BAR15                          (0x0090)
 318 +#define ME_XMEM_BAR16                          (0x0094)
 319 +
 320 +#define WHILE_DELAY            20000
 321 +/*
 322 +**     Define where in ME Processor's memory map the Stratify chip lives
 323 +*/
 324 +
 325 +#define MAXSWAPSIZE            (8 * 1024)      //8k *(32bits)
 326 +
 327 +//      Mailboxes
 328 +#define MSG_LENGTH             16      // x16 bits
 329 +#define YES_REPLY                      1
 330 +#define NO_REPLY               0
 331 +
 332 +#define CMV_TIMEOUT            1000    //jiffies
 333 +
 334 +//  Block size per BAR
 335 +#define SDRAM_SEGMENT_SIZE     (64*1024)
 336 +// Number of Bar registers
 337 +#define MAX_BAR_REGISTERS      (17)
 338 +
 339 +#define XDATA_REGISTER         (15)
 340 +
 341 +// ARC register addresss
 342 +#define ARC_STATUS             0x0
 343 +#define ARC_LP_START           0x2
 344 +#define ARC_LP_END             0x3
 345 +#define ARC_DEBUG              0x5
 346 +#define ARC_INT_MASK           0x10A
 347 +
 348 +#define IRAM0_BASE             (0x00000)
 349 +#define IRAM1_BASE             (0x04000)
 350 +#if defined(CONFIG_DANUBE)
 351 +#define BRAM_BASE              (0x0A000)
 352 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
 353 +#define BRAM_BASE               (0x08000)
 354 +#endif
 355 +#define XRAM_BASE              (0x18000)
 356 +#define YRAM_BASE              (0x1A000)
 357 +#define EXT_MEM_BASE           (0x80000)
 358 +#define ARC_GPIO_CTRL          (0xC030)
 359 +#define ARC_GPIO_DATA          (0xC034)
 360 +
 361 +#define IRAM0_SIZE             (16*1024)
 362 +#define IRAM1_SIZE             (16*1024)
 363 +#define BRAM_SIZE              (12*1024)
 364 +#define XRAM_SIZE              (8*1024)
 365 +#define YRAM_SIZE              (8*1024)
 366 +#define EXT_MEM_SIZE           (1536*1024)
 367 +
 368 +#define ADSL_BASE              (0x20000)
 369 +#define CRI_BASE               (ADSL_BASE + 0x11F00)
 370 +#define CRI_CCR0               (CRI_BASE + 0x00)
 371 +#define CRI_RST                        (CRI_BASE + 0x04*4)
 372 +#define ADSL_DILV_BASE                 (ADSL_BASE+0x20000)
 373 +
 374 +//
 375 +#define IRAM0_ADDR_BIT_MASK    0xFFF
 376 +#define IRAM1_ADDR_BIT_MASK    0xFFF
 377 +#define BRAM_ADDR_BIT_MASK     0xFFF
 378 +#define RX_DILV_ADDR_BIT_MASK  0x1FFF
 379 +
 380 +/***  Bit definitions ***/
 381 +#define ARC_AUX_HALT           (1 << 25)
 382 +#define ARC_DEBUG_HALT         (1 << 1)
 383 +#define FALSE                  0
 384 +#define TRUE                   1
 385 +#define BIT0                   (1<<0)
 386 +#define BIT1                   (1<<1)
 387 +#define BIT2                   (1<<2)
 388 +#define BIT3                   (1<<3)
 389 +#define BIT4                   (1<<4)
 390 +#define BIT5                   (1<<5)
 391 +#define BIT6                   (1<<6)
 392 +#define BIT7                   (1<<7)
 393 +#define BIT8                   (1<<8)
 394 +#define BIT9                   (1<<9)
 395 +#define BIT10                  (1<<10)
 396 +#define BIT11                  (1<<11)
 397 +#define BIT12                  (1<<12)
 398 +#define BIT13                  (1<<13)
 399 +#define BIT14                  (1<<14)
 400 +#define BIT15                  (1<<15)
 401 +#define BIT16                  (1<<16)
 402 +#define BIT17                  (1<<17)
 403 +#define BIT18                  (1<<18)
 404 +#define BIT19                  (1<<19)
 405 +#define BIT20                  (1<<20)
 406 +#define BIT21                  (1<<21)
 407 +#define BIT22                  (1<<22)
 408 +#define BIT23                  (1<<23)
 409 +#define BIT24                  (1<<24)
 410 +#define BIT25                  (1<<25)
 411 +#define BIT26                  (1<<26)
 412 +#define BIT27                  (1<<27)
 413 +#define BIT28                  (1<<28)
 414 +#define BIT29                  (1<<29)
 415 +#define BIT30                  (1<<30)
 416 +#define BIT31                  (1<<31)
 417 +
 418 +// CRI_CCR0 Register definitions
 419 +#define CLK_2M_MODE_ENABLE     BIT6
 420 +#define        ACL_CLK_MODE_ENABLE     BIT4
 421 +#define FDF_CLK_MODE_ENABLE    BIT2
 422 +#define STM_CLK_MODE_ENABLE    BIT0
 423 +
 424 +// CRI_RST Register definitions
 425 +#define FDF_SRST               BIT3
 426 +#define MTE_SRST               BIT2
 427 +#define FCI_SRST               BIT1
 428 +#define AAI_SRST               BIT0
 429 +
 430 +//      MEI_TO_ARC_INTERRUPT Register definitions
 431 +#define        MEI_TO_ARC_INT1         BIT3
 432 +#define        MEI_TO_ARC_INT0         BIT2
 433 +#define MEI_TO_ARC_CS_DONE     BIT1    //need to check
 434 +#define        MEI_TO_ARC_MSGAV        BIT0
 435 +
 436 +//      ARC_TO_MEI_INTERRUPT Register definitions
 437 +#define        ARC_TO_MEI_INT1         BIT8
 438 +#define        ARC_TO_MEI_INT0         BIT7
 439 +#define        ARC_TO_MEI_CS_REQ       BIT6
 440 +#define        ARC_TO_MEI_DBG_DONE     BIT5
 441 +#define        ARC_TO_MEI_MSGACK       BIT4
 442 +#define        ARC_TO_MEI_NO_ACCESS    BIT3
 443 +#define        ARC_TO_MEI_CHECK_AAITX  BIT2
 444 +#define        ARC_TO_MEI_CHECK_AAIRX  BIT1
 445 +#define        ARC_TO_MEI_MSGAV        BIT0
 446 +
 447 +//      ARC_TO_MEI_INTERRUPT_MASK Register definitions
 448 +#define        GP_INT1_EN              BIT8
 449 +#define        GP_INT0_EN              BIT7
 450 +#define        CS_REQ_EN               BIT6
 451 +#define        DBG_DONE_EN             BIT5
 452 +#define        MSGACK_EN               BIT4
 453 +#define        NO_ACC_EN               BIT3
 454 +#define        AAITX_EN                BIT2
 455 +#define        AAIRX_EN                BIT1
 456 +#define        MSGAV_EN                BIT0
 457 +
 458 +#define        MEI_SOFT_RESET          BIT0
 459 +
 460 +#define        HOST_MSTR               BIT0
 461 +
 462 +#define JTAG_MASTER_MODE       0x0
 463 +#define MEI_MASTER_MODE                HOST_MSTR
 464 +
 465 +//      MEI_DEBUG_DECODE Register definitions
 466 +#define MEI_DEBUG_DEC_MASK     (0x3)
 467 +#define MEI_DEBUG_DEC_AUX_MASK (0x0)
 468 +#define ME_DBG_DECODE_DMP1_MASK        (0x1)
 469 +#define MEI_DEBUG_DEC_DMP2_MASK        (0x2)
 470 +#define MEI_DEBUG_DEC_CORE_MASK        (0x3)
 471 +
 472 +#define AUX_STATUS             (0x0)
 473 +#define AUX_ARC_GPIO_CTRL      (0x10C)
 474 +#define AUX_ARC_GPIO_DATA      (0x10D)
 475 +//      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
 476 +//      page swap requests.
 477 +#if defined(CONFIG_DANUBE)
 478 +#define OMBOX_BASE             0xDF80
 479 +#define        ARC_TO_MEI_MAILBOX      0xDFA0
 480 +#define IMBOX_BASE             0xDFC0
 481 +#define MEI_TO_ARC_MAILBOX     0xDFD0
 482 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
 483 +#define OMBOX_BASE              0xAF80
 484 +#define ARC_TO_MEI_MAILBOX      0xAFA0
 485 +#define IMBOX_BASE              0xAFC0
 486 +#define MEI_TO_ARC_MAILBOX      0xAFD0
 487 +#endif
 488 +
 489 +#define MEI_TO_ARC_MAILBOXR    (MEI_TO_ARC_MAILBOX + 0x2C)
 490 +#define ARC_MEI_MAILBOXR       (ARC_TO_MEI_MAILBOX + 0x2C)
 491 +#define OMBOX1                 (OMBOX_BASE+0x4)
 492 +
 493 +// Codeswap request messages are indicated by setting BIT31
 494 +#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK     (0x80000000)
 495 +
 496 +// Clear Eoc messages received are indicated by setting BIT17
 497 +#define OMB_CLEAREOC_INTERRUPT_CODE            (0x00020000)
 498 +#define OMB_REBOOT_INTERRUPT_CODE               (1 << 18)
 499 +
 500 +/*
 501 +**     Swap page header
 502 +*/
 503 +//      Page must be loaded at boot time if size field has BIT31 set
 504 +#define BOOT_FLAG              (BIT31)
 505 +#define BOOT_FLAG_MASK         ~BOOT_FLAG
 506 +
 507 +#define FREE_RELOAD            1
 508 +#define FREE_SHOWTIME          2
 509 +#define FREE_ALL               3
 510 +
 511 +// marcos
 512 +#define        IFX_MEI_WRITE_REGISTER_L(data,addr)     *((volatile u32*)(addr)) = (u32)(data)
 513 +#define IFX_MEI_READ_REGISTER_L(addr)  (*((volatile u32*)(addr)))
 514 +#define SET_BIT(reg, mask)                     reg |= (mask)
 515 +#define CLEAR_BIT(reg, mask)                   reg &= (~mask)
 516 +#define CLEAR_BITS(reg, mask)                  CLEAR_BIT(reg, mask)
 517 +//#define SET_BITS(reg, mask)                  SET_BIT(reg, mask)
 518 +#define SET_BITFIELD(reg, mask, off, val)      {reg &= (~mask); reg |= (val << off);}
 519 +
 520 +#define ALIGN_SIZE                             ( 1L<<10 )      //1K size align
 521 +#define MEM_ALIGN(addr)                                (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
 522 +
 523 +// swap marco
 524 +#define MEI_HALF_WORD_SWAP(data)               {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
 525 +#define MEI_BYTE_SWAP(data)                    {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
 526 +
 527 +
 528 +#ifdef CONFIG_PROC_FS
 529 +typedef struct reg_entry
 530 +{
 531 +   int *flag;
 532 +   char name[30];               /* big enough to hold names */
 533 +   char description[100];       /* big enough to hold description */
 534 +   unsigned short low_ino;
 535 +} reg_entry_t;
 536 +#endif
 537 +//      Swap page header describes size in 32-bit words, load location, and image offset
 538 +//      for program and/or data segments
 539 +typedef struct _arc_swp_page_hdr {
 540 +       u32 p_offset;           //Offset bytes of progseg from beginning of image
 541 +       u32 p_dest;             //Destination addr of progseg on processor
 542 +       u32 p_size;             //Size in 32-bitwords of program segment
 543 +       u32 d_offset;           //Offset bytes of dataseg from beginning of image
 544 +       u32 d_dest;             //Destination addr of dataseg on processor
 545 +       u32 d_size;             //Size in 32-bitwords of data segment
 546 +} ARC_SWP_PAGE_HDR;
 547 +
 548 +/*
 549 +**     Swap image header
 550 +*/
 551 +#define GET_PROG       0       //      Flag used for program mem segment
 552 +#define GET_DATA       1       //      Flag used for data mem segment
 553 +
 554 +//      Image header contains size of image, checksum for image, and count of
 555 +//      page headers. Following that are 'count' page headers followed by
 556 +//      the code and/or data segments to be loaded
 557 +typedef struct _arc_img_hdr {
 558 +       u32 size;               //      Size of binary image in bytes
 559 +       u32 checksum;           //      Checksum for image
 560 +       u32 count;              //      Count of swp pages in image
 561 +       ARC_SWP_PAGE_HDR page[1];       //      Should be "count" pages - '1' to make compiler happy
 562 +} ARC_IMG_HDR;
 563 +
 564 +typedef struct smmu_mem_info {
 565 +       int type;
 566 +       int boot;
 567 +       unsigned long nCopy;
 568 +       unsigned long size;
 569 +       unsigned char *address;
 570 +       unsigned char *org_address;
 571 +} smmu_mem_info_t;
 572 +
 573 +#ifdef __KERNEL__
 574 +typedef struct ifx_mei_device_private {
 575 +       int modem_ready;
 576 +       int arcmsgav;
 577 +       int cmv_reply;
 578 +       int cmv_waiting;
 579 +       // Mei to ARC CMV count, reply count, ARC Indicator count
 580 +       int modem_ready_cnt;
 581 +       int cmv_count;
 582 +       int reply_count;
 583 +       unsigned long image_size;
 584 +       int nBar;
 585 +       u16 Recent_indicator[MSG_LENGTH];
 586 +
 587 +       u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
 588 +
 589 +       smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
 590 +       ARC_IMG_HDR *img_hdr;
 591 +       //  to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
 592 +       wait_queue_head_t wait_queue_arcmsgav;
 593 +       wait_queue_head_t wait_queue_modemready;
 594 +       struct semaphore mei_cmv_sema;
 595 +} ifx_mei_device_private_t;
 596 +#endif
 597 +typedef struct winhost_message {
 598 +       union {
 599 +               u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
 600 +               u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
 601 +       } msg;
 602 +} DSL_DEV_WinHost_Message_t;
 603 +/********************************************************************************************************
 604 + * DSL CPE API Driver Stack Interface Definitions
 605 + * *****************************************************************************************************/
 606 +/** IOCTL codes for bsp driver */
 607 +#define DSL_IOC_MEI_BSP_MAGIC          's'
 608 +
 609 +#define DSL_FIO_BSP_DSL_START          _IO  (DSL_IOC_MEI_BSP_MAGIC, 0)
 610 +#define DSL_FIO_BSP_RUN                        _IO  (DSL_IOC_MEI_BSP_MAGIC, 1)
 611 +#define DSL_FIO_BSP_FREE_RESOURCE      _IO  (DSL_IOC_MEI_BSP_MAGIC, 2)
 612 +#define DSL_FIO_BSP_RESET              _IO  (DSL_IOC_MEI_BSP_MAGIC, 3)
 613 +#define DSL_FIO_BSP_REBOOT             _IO  (DSL_IOC_MEI_BSP_MAGIC, 4)
 614 +#define DSL_FIO_BSP_HALT               _IO  (DSL_IOC_MEI_BSP_MAGIC, 5)
 615 +#define DSL_FIO_BSP_BOOTDOWNLOAD       _IO  (DSL_IOC_MEI_BSP_MAGIC, 6)
 616 +#define DSL_FIO_BSP_JTAG_ENABLE                _IO  (DSL_IOC_MEI_BSP_MAGIC, 7)
 617 +#define DSL_FIO_FREE_RESOURCE          _IO  (DSL_IOC_MEI_BSP_MAGIC, 8)
 618 +#define DSL_FIO_ARC_MUX_TEST           _IO  (DSL_IOC_MEI_BSP_MAGIC, 9)
 619 +#define DSL_FIO_BSP_REMOTE             _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
 620 +#define DSL_FIO_BSP_GET_BASE_ADDRESS   _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
 621 +#define DSL_FIO_BSP_IS_MODEM_READY     _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
 622 +#define DSL_FIO_BSP_GET_VERSION                _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
 623 +#define DSL_FIO_BSP_CMV_WINHOST                _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
 624 +#define DSL_FIO_BSP_CMV_READ           _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
 625 +#define DSL_FIO_BSP_CMV_WRITE          _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
 626 +#define DSL_FIO_BSP_DEBUG_READ         _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
 627 +#define DSL_FIO_BSP_DEBUG_WRITE                _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
 628 +#define DSL_FIO_BSP_GET_CHIP_INFO      _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
 629 +
 630 +#define DSL_DEV_MEIDEBUG_BUFFER_SIZES  512
 631 +
 632 +typedef struct DSL_DEV_MeiDebug
 633 +{
 634 +       DSL_uint32_t iAddress;
 635 +       DSL_uint32_t iCount;
 636 +       DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
 637 +} DSL_DEV_MeiDebug_t;                  /* meidebug */
 638 +
 639 +/**
 640 + *    Structure is used for debug access only.
 641 + *       Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
 642 +typedef struct struct_meireg
 643 +{
 644 +       /*
 645 +       *       Specifies that address for debug access */
 646 +       unsigned long iAddress;
 647 +       /*
 648 +       *       Specifies the pointer to the data that has to be written or returns a
 649 +       *             pointer to the data that has been read out*/
 650 +       unsigned long iData;
 651 +} DSL_DEV_MeiReg_t;                                    /* meireg */
 652 +
 653 +typedef struct DSL_DEV_Device
 654 +{
 655 +       DSL_int_t nInUse;                /* modem state, update by bsp driver, */
 656 +       DSL_void_t *pPriv;
 657 +       DSL_uint32_t base_address;       /* mei base address */
 658 +       DSL_int_t nIrq[2];                  /* irq number */
 659 +#define IFX_DFEIR              0
 660 +#define IFX_DYING_GASP 1
 661 +       DSL_DEV_MeiDebug_t lop_debugwr;  /* dying gasp */
 662 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
 663 +       struct module *owner;
 664 +#endif
 665 +} DSL_DEV_Device_t;                    /* ifx_adsl_device_t */
 666 +
 667 +#define DSL_DEV_PRIVATE(dev)  ((ifx_mei_device_private_t*)(dev->pPriv))
 668 +
 669 +typedef struct DSL_DEV_Version         /* ifx_adsl_bsp_version */
 670 +{
 671 +       unsigned long major;
 672 +       unsigned long minor;
 673 +       unsigned long revision;
 674 +} DSL_DEV_Version_t;                   /* ifx_adsl_bsp_version_t */
 675 +
 676 +typedef struct DSL_DEV_ChipInfo
 677 +{
 678 +       unsigned long major;
 679 +       unsigned long minor;
 680 +} DSL_DEV_HwVersion_t;
 681 +
 682 +typedef struct
 683 +{
 684 +       DSL_uint8_t dummy;
 685 +} DSL_DEV_DeviceConfig_t;
 686 +
 687 +/** error code definitions */
 688 +typedef enum DSL_DEV_MeiError
 689 +{
 690 +       DSL_DEV_MEI_ERR_SUCCESS = 0,
 691 +       DSL_DEV_MEI_ERR_FAILURE = -1,
 692 +       DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
 693 +       DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
 694 +       DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
 695 +} DSL_DEV_MeiError_t;                  /* MEI_ERROR */
 696 +
 697 +typedef enum {
 698 +       DSL_BSP_MEMORY_READ=0,
 699 +       DSL_BSP_MEMORY_WRITE,
 700 +} DSL_BSP_MemoryAccessType_t;          /* ifx_adsl_memory_access_type_t */
 701 +
 702 +typedef enum
 703 +{
 704 +       DSL_LED_LINK_ID=0,
 705 +       DSL_LED_DATA_ID
 706 +} DSL_DEV_LedId_t;                     /* ifx_adsl_led_id_t */
 707 +
 708 +typedef enum
 709 +{
 710 +       DSL_LED_LINK_TYPE=0,
 711 +       DSL_LED_DATA_TYPE
 712 +} DSL_DEV_LedType_t;                   /* ifx_adsl_led_type_t */
 713 +
 714 +typedef enum
 715 +{
 716 +       DSL_LED_HD_CPU=0,
 717 +       DSL_LED_HD_FW
 718 +} DSL_DEV_LedHandler_t;                        /* ifx_adsl_led_handler_t */
 719 +
 720 +typedef enum {
 721 +       DSL_LED_ON=0,
 722 +       DSL_LED_OFF,
 723 +       DSL_LED_FLASH,
 724 +} DSL_DEV_LedMode_t;                   /* ifx_adsl_led_mode_t */
 725 +
 726 +typedef enum {
 727 +       DSL_CPU_HALT=0,
 728 +       DSL_CPU_RUN,
 729 +       DSL_CPU_RESET,
 730 +} DSL_DEV_CpuMode_t;                   /* ifx_adsl_cpu_mode_t */
 731 +
 732 +#if 0
 733 +typedef enum {
 734 +       DSL_BSP_EVENT_DYING_GASP = 0,
 735 +       DSL_BSP_EVENT_CEOC_IRQ,
 736 +} DSL_BSP_Event_id_t;                  /* ifx_adsl_event_id_t */
 737 +
 738 +typedef union DSL_BSP_CB_Param
 739 +{
 740 +       DSL_uint32_t nIrqMessage;
 741 +} DSL_BSP_CB_Param_t;                  /* ifx_adsl_cbparam_t */
 742 +
 743 +typedef struct DSL_BSP_CB_Event
 744 +{
 745 +       DSL_BSP_Event_id_t nID;
 746 +       DSL_DEV_Device_t *pDev;
 747 +       DSL_BSP_CB_Param_t *pParam;
 748 +} DSL_BSP_CB_Event_t;                  /* ifx_adsl_cb_event_t */
 749 +#endif
 750 +
 751 +/* external functions (from the BSP Driver) */
 752 +extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
 753 +extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
 754 +extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
 755 +extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
 756 +extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
 757 +extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
 758 +extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
 759 +extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
 760 +extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
 761 +extern volatile DSL_DEV_Device_t *adsl_dev;
 762 +
 763 +/**
 764 + *    Dummy structure by now to show mechanism of extended data that will be
 765 + *       provided within event callback itself.
 766 + *       */
 767 +typedef struct
 768 +{
 769 +       /**
 770 +       *    Dummy value */
 771 +       DSL_uint32_t nDummy1;
 772 +} DSL_BSP_CB_Event1DataDummy_t;
 773 +
 774 +/**
 775 + *    Dummy structure by now to show mechanism of extended data that will be
 776 + *       provided within event callback itself.
 777 + *       */
 778 +typedef struct
 779 +{
 780 +       /**
 781 +       *    Dummy value */
 782 +       DSL_uint32_t nDummy2;
 783 +} DSL_BSP_CB_Event2DataDummy_t;
 784 +
 785 +/**
 786 + *    encapsulate all data structures that are necessary for status event
 787 + *       callbacks.
 788 + *       */
 789 +typedef union
 790 +{
 791 +       DSL_BSP_CB_Event1DataDummy_t dataEvent1;
 792 +       DSL_BSP_CB_Event2DataDummy_t dataEvent2;
 793 +} DSL_BSP_CB_DATA_Union_t;
 794 +
 795 +
 796 +typedef enum
 797 +{
 798 +       /**
 799 +        *    Informs the upper layer driver (DSL CPE API) about a reboot request from the
 800 +        *       firmware.
 801 +        *          \note This event does NOT include any additional data.
 802 +        *                   More detailed information upon reboot reason has to be requested from
 803 +        *                            upper layer software via CMV (INFO 109) if necessary. */
 804 +       DSL_BSP_CB_FIRST = 0,
 805 +        DSL_BSP_CB_DYING_GASP,
 806 +       DSL_BSP_CB_CEOC_IRQ,
 807 +       DSL_BSP_CB_FIRMWARE_REBOOT,
 808 +       /**
 809 +        *    Delimiter only */
 810 +       DSL_BSP_CB_LAST
 811 +} DSL_BSP_CB_Type_t;
 812 +
 813 +/**
 814 + *    Specifies the common event type that has to be used for registering and
 815 + *       signalling of interrupts/autonomous status events from MEI BSP Driver.
 816 + *
 817 + *    \param pDev
 818 + *    Context pointer from MEI BSP Driver.
 819 + *
 820 + *    \param IFX_ADSL_BSP_CallbackType_t
 821 + *    Specifies the event callback type (reason of callback). Regrading to the
 822 + *    setting of this value the data which is included in the following union
 823 + *    might have different meanings.
 824 + *    Please refer to the description of the union to get information about the
 825 + *    meaning of the included data.
 826 + *
 827 + *    \param pData
 828 + *    Data according to \ref DSL_BSP_CB_DATA_Union_t.
 829 + *    If this pointer is NULL there is no additional data available.
 830 + *
 831 + *    \return depending on event
 832 + */
 833 +typedef int (*DSL_BSP_EventCallback_t)
 834 +(
 835 +       DSL_DEV_Device_t *pDev,
 836 +       DSL_BSP_CB_Type_t nCallbackType,
 837 +       DSL_BSP_CB_DATA_Union_t *pData
 838 +);
 839 +
 840 +typedef struct {
 841 +        DSL_BSP_EventCallback_t function;
 842 +        DSL_BSP_CB_Type_t       event;
 843 +        DSL_BSP_CB_DATA_Union_t *pData;
 844 +} DSL_BSP_EventCallBack_t;
 845 +
 846 +extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
 847 +extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
 848 +
 849 +/** Modem states */
 850 +#define DSL_DEV_STAT_InitState              0x0000
 851 +#define DSL_DEV_STAT_ReadyState             0x0001
 852 +#define DSL_DEV_STAT_FailState              0x0002
 853 +#define DSL_DEV_STAT_IdleState              0x0003
 854 +#define DSL_DEV_STAT_QuietState             0x0004
 855 +#define DSL_DEV_STAT_GhsState               0x0005
 856 +#define DSL_DEV_STAT_FullInitState          0x0006
 857 +#define DSL_DEV_STAT_ShowTimeState          0x0007
 858 +#define DSL_DEV_STAT_FastRetrainState       0x0008
 859 +#define DSL_DEV_STAT_LoopDiagMode           0x0009
 860 +#define DSL_DEV_STAT_ShortInit              0x000A     /* Bis short initialization */
 861 +
 862 +#define DSL_DEV_STAT_CODESWAP_COMPLETE     0x0002
 863 +
 864 +#endif //IFXMIPS_MEI_H
 865 --- a/configure.in
 866 +++ b/configure.in
 867 @@ -310,7 +310,7 @@ dnl Set kernel build path
 868  AC_ARG_ENABLE(kernelbuild,
 869      AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
 870      [
 871 -        if test -e $enableval/include/linux/autoconf.h; then
 872 +        if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
 873              AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
 874          else
 875              AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
 876 @@ -333,12 +333,12 @@ AC_ARG_ENABLE(ifxos-include,
 877              echo Set the lib_ifxos include path $enableval
 878              AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
 879          else
 880 -            echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 881 +            echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 882              AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
 883          fi
 884      ],
 885      [
 886 -        echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 887 +        echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 888          AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
 889      ]
 890  )
 891 @@ -1702,73 +1702,73 @@ dnl Set the configure params for dist ch
 892  AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
 893
 894  AC_CONFIG_COMMANDS_PRE([
 895 -echo -e "------------------------------------------------------------------------"
 896 -echo -e " Configuration for drv_dsl_cpe_api:"
 897 -echo -e "  Configure model type:             $DSL_CONFIG_MODEL_TYPE"
 898 -echo -e "  Source code location:             $srcdir"
 899 -echo -e "  Compiler:                         $CC"
 900 -echo -e "  Compiler c-flags:                 $CFLAGS"
 901 -echo -e "  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS"
 902 -echo -e "  Host System Type:                 $host"
 903 -echo -e "  Install path:                     $prefix"
 904 -echo -e "  Linux kernel include path:        $KERNEL_INCL_PATH"
 905 -echo -e "  Linux kernel build path:          $KERNEL_BUILD_PATH"
 906 -echo -e "  Linux kernel architecture:        $KERNEL_ARCH"
 907 -echo -e "  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
 908 -echo -e "  IFXOS include path:               $IFXOS_INCLUDE_PATH"
 909 -echo -e "  Driver Include Path               $DSL_DRIVER_INCL_PATH"
 910 -echo -e "  DSL device:                       $DSL_DEVICE_NAME"
 911 -echo -e "  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER"
 912 -echo -e "  Channels per line:                $DSL_CHANNELS_PER_LINE"
 913 -echo -e "  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6"
 914 -echo -e "  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz"
 915 -echo -e "  Disable debug prints:             $DSL_DEBUG_DISABLE"
 916 -echo -e "  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
 917 -echo -e "  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE"
 918 -echo -e "  Include deprecated functions:     $INCLUDE_DEPRECATED"
 919 -echo -e "  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES"
 920 -echo -e "  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT"
 921 -echo -e "  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER"
 922 -echo -e "  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB"
 923 -echo -e "  Include ADSL LED:                 $INCLUDE_ADSL_LED"
 924 -echo -e "  Include CEOC:                     $INCLUDE_DSL_CEOC"
 925 -echo -e "  Include config get support:       $INCLUDE_DSL_CONFIG_GET"
 926 -echo -e "  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
 927 -echo -e "  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS"
 928 -echo -e "  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS"
 929 -echo -e "  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY"
 930 -echo -e "  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
 931 -echo -e "  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE"
 932 -echo -e "  Include G997 status:              $INCLUDE_DSL_G997_STATUS"
 933 -echo -e "  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM"
 934 -echo -e "  Include DSL Bonding:              $INCLUDE_DSL_BONDING"
 935 -echo -e "  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
 936 -echo -e "  Include DELT:                     $INCLUDE_DSL_DELT"
 937 -echo -e "  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
 938 -echo -e "  Include PM:                       $INCLUDE_DSL_PM"
 939 -echo -e "  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG"
 940 -echo -e "  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
 941 -echo -e "  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY"
 942 -echo -e "  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
 943 -echo -e "  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
 944 -echo -e "  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
 945 -echo -e "  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
 946 -echo -e "  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
 947 -echo -e "  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
 948 -echo -e "  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
 949 -echo -e "  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
 950 -echo -e "  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
 951 -echo -e "  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
 952 -echo -e "  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
 953 -echo -e "  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
 954 -echo -e "  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
 955 -echo -e "  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
 956 -echo -e "----------------------- deprectated ! ----------------------------------"
 957 -echo -e "  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
 958 -echo -e ""
 959 -echo -e " Settings:"
 960 -echo -e "  Configure options:                $CONFIGURE_OPTIONS"
 961 -echo -e "------------------------------------------------------------------------"
 962 +echo "------------------------------------------------------------------------"
 963 +echo " Configuration for drv_dsl_cpe_api:"
 964 +echo "  Configure model type:             $DSL_CONFIG_MODEL_TYPE"
 965 +echo "  Source code location:             $srcdir"
 966 +echo "  Compiler:                         $CC"
 967 +echo "  Compiler c-flags:                 $CFLAGS"
 968 +echo "  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS"
 969 +echo "  Host System Type:                 $host"
 970 +echo "  Install path:                     $prefix"
 971 +echo "  Linux kernel include path:        $KERNEL_INCL_PATH"
 972 +echo "  Linux kernel build path:          $KERNEL_BUILD_PATH"
 973 +echo "  Linux kernel architecture:        $KERNEL_ARCH"
 974 +echo "  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
 975 +echo "  IFXOS include path:               $IFXOS_INCLUDE_PATH"
 976 +echo "  Driver Include Path               $DSL_DRIVER_INCL_PATH"
 977 +echo "  DSL device:                       $DSL_DEVICE_NAME"
 978 +echo "  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER"
 979 +echo "  Channels per line:                $DSL_CHANNELS_PER_LINE"
 980 +echo "  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6"
 981 +echo "  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz"
 982 +echo "  Disable debug prints:             $DSL_DEBUG_DISABLE"
 983 +echo "  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
 984 +echo "  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE"
 985 +echo "  Include deprecated functions:     $INCLUDE_DEPRECATED"
 986 +echo "  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES"
 987 +echo "  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT"
 988 +echo "  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER"
 989 +echo "  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB"
 990 +echo "  Include ADSL LED:                 $INCLUDE_ADSL_LED"
 991 +echo "  Include CEOC:                     $INCLUDE_DSL_CEOC"
 992 +echo "  Include config get support:       $INCLUDE_DSL_CONFIG_GET"
 993 +echo "  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
 994 +echo "  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS"
 995 +echo "  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS"
 996 +echo "  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY"
 997 +echo "  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
 998 +echo "  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE"
 999 +echo "  Include G997 status:              $INCLUDE_DSL_G997_STATUS"
1000 +echo "  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM"
1001 +echo "  Include DSL Bonding:              $INCLUDE_DSL_BONDING"
1002 +echo "  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
1003 +echo "  Include DELT:                     $INCLUDE_DSL_DELT"
1004 +echo "  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
1005 +echo "  Include PM:                       $INCLUDE_DSL_PM"
1006 +echo "  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG"
1007 +echo "  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
1008 +echo "  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY"
1009 +echo "  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
1010 +echo "  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
1011 +echo "  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
1012 +echo "  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
1013 +echo "  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
1014 +echo "  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
1015 +echo "  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
1016 +echo "  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
1017 +echo "  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
1018 +echo "  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
1019 +echo "  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
1020 +echo "  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
1021 +echo "  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
1022 +echo "  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
1023 +echo "----------------------- deprectated ! ----------------------------------"
1024 +echo "  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
1025 +echo ""
1026 +echo " Settings:"
1027 +echo "  Configure options:                $CONFIGURE_OPTIONS"
1028 +echo "------------------------------------------------------------------------"
1029  ])
1030
1031  AC_CONFIG_FILES([Makefile src/Makefile])
1032 --- a/src/Makefile.am
1033 +++ b/src/Makefile.am
1034 @@ -300,7 +300,7 @@ if KERNEL_2_6
1035  drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
1036
1037  drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
1038 -       @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1039 +       @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1040         if test ! -e common/drv_dsl_cpe_api.c ; then \
1041                 echo "copy source files (as links only!)"; \
1042                 for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
1043 @@ -308,10 +308,10 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO
1044                         cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
1045                 done \
1046         fi
1047 -       @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1048 -       @echo -e "obj-m := $(subst .ko,.o,$@)"                  >> $(PWD)/Kbuild
1049 -       @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)"        >> $(PWD)/Kbuild
1050 -       @echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include"      >> $(PWD)/Kbuild
1051 +       @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1052 +       @echo "obj-m := $(subst .ko,.o,$@)"                     >> $(PWD)/Kbuild
1053 +       @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)"   >> $(PWD)/Kbuild
1054 +       @echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
1055         $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
1056
1057  clean-generic: