3 #include <linux/interrupt.h>
6 #include <linux/ssb/ssb_embedded.h>
8 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
9 #include <linux/gpio.h>
10 #define ssb ssb_bcm47xx
12 extern struct ssb_bus ssb;
15 static inline u32 gpio_in(void)
17 return ssb_gpio_in(&ssb, ~0);
20 static inline u32 gpio_out(u32 mask, u32 value)
22 return ssb_gpio_out(&ssb, mask, value);
25 static inline u32 gpio_outen(u32 mask, u32 value)
27 return ssb_gpio_outen(&ssb, mask, value);
30 static inline u32 gpio_control(u32 mask, u32 value)
32 return ssb_gpio_control(&ssb, mask, value);
35 static inline u32 gpio_intmask(u32 mask, u32 value)
37 return ssb_gpio_intmask(&ssb, mask, value);
40 static inline u32 gpio_intpolarity(u32 mask, u32 value)
42 return ssb_gpio_polarity(&ssb, mask, value);
45 static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
49 value |= ssb_read32(dev, offset) & ~mask;
50 ssb_write32(dev, offset, value);
54 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
58 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
60 if (irq == -EINVAL) return;
63 irq = ssb_mips_irq(ssb.chipco.dev) + 2;
64 else if (ssb.extif.dev)
65 irq = ssb_mips_irq(ssb.extif.dev) + 2;
70 if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
73 free_irq(irq, handler);
77 __ssb_write32_masked(ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
88 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
94 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
95 #define sbh bcm947xx_sbh
96 #define sbh_lock bcm947xx_sbh_lock
100 extern spinlock_t sbh_lock;
102 #define gpio_in() sb_gpioin(sbh)
103 #define gpio_out(mask, value) sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
104 #define gpio_outen(mask, value) sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
105 #define gpio_control(mask, value) sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
106 #define gpio_intmask(mask, value) sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
107 #define gpio_intpolarity(mask, value) sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
109 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
111 unsigned int coreidx;
116 spin_lock_irqsave(sbh_lock, flags);
117 coreidx = sb_coreidx(sbh);
119 irq = sb_irq(sbh) + 2;
121 request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
123 free_irq(irq, handler);
125 if ((cc = sb_setcore(sbh, SB_CC, 0))) {
128 intmask = readl(&cc->intmask);
133 writel(intmask, &cc->intmask);
135 sb_setcoreidx(sbh, coreidx);
136 spin_unlock_irqrestore(sbh_lock, flags);
139 #endif /* BCMDRIVER */
141 #define EXTIF_ADDR 0x1f000000
142 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)
144 #define GPIO_TYPE_NORMAL (0x0 << 24)
145 #define GPIO_TYPE_EXTIF (0x1 << 24)
146 #define GPIO_TYPE_MASK (0xf << 24)
148 static inline void gpio_set_extif(int gpio, int value)
150 volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
157 #endif /* __DIAG_GPIO_H */