3 #include <linux/interrupt.h>
6 #include <linux/ssb/ssb_embedded.h>
8 extern struct ssb_bus ssb;
11 static inline u32 gpio_in(void)
13 return ssb_gpio_in(&ssb, ~0);
16 static inline u32 gpio_out(u32 mask, u32 value)
18 return ssb_gpio_out(&ssb, mask, value);
21 static inline u32 gpio_outen(u32 mask, u32 value)
23 return ssb_gpio_outen(&ssb, mask, value);
26 static inline u32 gpio_control(u32 mask, u32 value)
28 return ssb_gpio_control(&ssb, mask, value);
31 static inline u32 gpio_intmask(u32 mask, u32 value)
33 return ssb_gpio_intmask(&ssb, mask, value);
36 static inline u32 gpio_intpolarity(u32 mask, u32 value)
38 return ssb_gpio_polarity(&ssb, mask, value);
41 static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
45 value |= ssb_read32(dev, offset) & ~mask;
46 ssb_write32(dev, offset, value);
50 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
55 irq = ssb_mips_irq(ssb.chipco.dev) + 2;
56 else if (ssb.extif.dev)
57 irq = ssb_mips_irq(ssb.extif.dev) + 2;
61 if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
64 free_irq(irq, handler);
68 __ssb_write32_masked(ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
79 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
85 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
86 #define sbh bcm947xx_sbh
87 #define sbh_lock bcm947xx_sbh_lock
91 extern spinlock_t sbh_lock;
93 #define gpio_in() sb_gpioin(sbh)
94 #define gpio_out(mask, value) sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
95 #define gpio_outen(mask, value) sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
96 #define gpio_control(mask, value) sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
97 #define gpio_intmask(mask, value) sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
98 #define gpio_intpolarity(mask, value) sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
100 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
102 unsigned int coreidx;
107 spin_lock_irqsave(sbh_lock, flags);
108 coreidx = sb_coreidx(sbh);
110 irq = sb_irq(sbh) + 2;
112 request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
114 free_irq(irq, handler);
116 if ((cc = sb_setcore(sbh, SB_CC, 0))) {
119 intmask = readl(&cc->intmask);
124 writel(intmask, &cc->intmask);
126 sb_setcoreidx(sbh, coreidx);
127 spin_unlock_irqrestore(sbh_lock, flags);
130 #endif /* BCMDRIVER */
132 #define EXTIF_ADDR 0x1f000000
133 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)
135 #define GPIO_TYPE_NORMAL (0x0 << 24)
136 #define GPIO_TYPE_EXTIF (0x1 << 24)
137 #define GPIO_TYPE_MASK (0xf << 24)
139 static inline void gpio_set_extif(int gpio, int value)
141 volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
148 #endif /* __DIAG_GPIO_H */