1 /******************************************************************************/
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2005 Broadcom */
5 /* All rights reserved. */
7 /* This program is free software; you can redistribute it and/or modify */
8 /* it under the terms of the GNU General Public License as published by */
9 /* the Free Software Foundation, located in the file LICENSE. */
12 /******************************************************************************/
22 #include "proto/ethernet.h"
24 /******************************************************************************/
25 /* Local functions. */
26 /******************************************************************************/
28 LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
29 LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
31 static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
32 static LM_VOID LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice);
34 LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
35 LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
37 static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice);
38 static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
39 STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
40 LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
41 #ifdef INCLUDE_TBI_SUPPORT
42 STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
43 STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
45 STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
46 STATIC LM_VOID LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice);
47 STATIC LM_STATUS LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice);
48 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
49 LM_VOID LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2);
50 STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
51 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
52 STATIC LM_STATUS LM_DisableChip(PLM_DEVICE_BLOCK pDevice);
53 STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
54 STATIC LM_STATUS LM_DisableFW(PLM_DEVICE_BLOCK pDevice);
55 STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
57 STATIC LM_VOID LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice,
59 STATIC LM_VOID LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice,
61 STATIC LM_VOID LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice,
63 STATIC void LM_GetPhyId(LM_DEVICE_BLOCK *pDevice);
65 /******************************************************************************/
66 /* External functions. */
67 /******************************************************************************/
69 LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
70 #ifdef INCLUDE_TCP_SEG_SUPPORT
71 LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice);
72 LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice);
76 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
78 #ifdef PCIX_TARGET_WORKAROUND
79 if (pDevice->Flags & UNDI_FIX_FLAG)
81 return (LM_RegRdInd(pDevice, Register));
86 return (REG_RD_OFFSET(pDevice, Register));
90 /* Mainly used to flush posted write before delaying */
92 LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
96 #ifdef PCIX_TARGET_WORKAROUND
97 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
104 if (pDevice->Flags & REG_RD_BACK_FLAG)
107 dummy = REG_RD_OFFSET(pDevice, Register);
112 LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32,
115 #ifdef PCIX_TARGET_WORKAROUND
116 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
118 LM_RegWrInd(pDevice, Register, Value32);
125 REG_WR_OFFSET(pDevice, Register, Value32);
126 if (ReadBack && (pDevice->Flags & REG_RD_BACK_FLAG))
128 dummy = REG_RD_OFFSET(pDevice, Register);
133 /******************************************************************************/
137 /******************************************************************************/
140 PLM_DEVICE_BLOCK pDevice,
141 LM_UINT32 Register) {
144 MM_ACQUIRE_UNDI_LOCK(pDevice);
145 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
146 MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
147 MM_RELEASE_UNDI_LOCK(pDevice);
149 return MM_SWAP_LE32(Value32);
154 /******************************************************************************/
158 /******************************************************************************/
161 PLM_DEVICE_BLOCK pDevice,
165 MM_ACQUIRE_UNDI_LOCK(pDevice);
166 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
167 MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, MM_SWAP_LE32(Value32));
168 MM_RELEASE_UNDI_LOCK(pDevice);
173 /******************************************************************************/
177 /******************************************************************************/
180 PLM_DEVICE_BLOCK pDevice,
184 MM_ACQUIRE_UNDI_LOCK(pDevice);
185 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
186 MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
187 MM_RELEASE_UNDI_LOCK(pDevice);
189 return MM_SWAP_LE32(Value32);
194 /******************************************************************************/
198 /******************************************************************************/
201 PLM_DEVICE_BLOCK pDevice,
204 MM_ACQUIRE_UNDI_LOCK(pDevice);
205 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
206 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, MM_SWAP_LE32(Value32));
207 MM_RELEASE_UNDI_LOCK(pDevice);
211 /******************************************************************************/
215 /******************************************************************************/
218 PLM_DEVICE_BLOCK pDevice) {
221 PT3_RCV_BD pRcvBd = 0;
222 LM_UINT32 StdBdAdded = 0;
223 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
224 LM_UINT32 JumboBdAdded = 0;
225 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
226 LM_UINT32 ConIdx, Idx;
229 Lmstatus = LM_STATUS_SUCCESS;
231 if (pDevice->Flags & RX_BD_LIMIT_64_FLAG)
233 ConIdx = pDevice->pStatusBlkVirt->RcvStdConIdx;
234 Diff = (pDevice->RxStdProdIdx - ConIdx) &
235 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
238 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
240 pDevice->QueueAgain = TRUE;
242 return LM_STATUS_SUCCESS;
246 pDevice->QueueAgain = FALSE;
248 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
250 switch(pPacket->u.Rx.RcvProdRing) {
251 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
252 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
253 /* Initialize the buffer descriptor. */
254 Idx = pDevice->RxJumboProdIdx;
255 pRcvBd = &pDevice->pRxJumboBdVirt[Idx];
257 pPacket->u.Rx.RcvRingProdIdx = Idx;
258 pDevice->RxJumboRing[Idx] = pPacket;
259 /* Update the producer index. */
260 pDevice->RxJumboProdIdx = (Idx + 1) &
261 T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
265 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
267 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
268 /* Initialize the buffer descriptor. */
269 Idx = pDevice->RxStdProdIdx;
270 pRcvBd = &pDevice->pRxStdBdVirt[Idx];
272 pPacket->u.Rx.RcvRingProdIdx = Idx;
273 pDevice->RxStdRing[Idx] = pPacket;
274 /* Update the producer index. */
275 pDevice->RxStdProdIdx = (Idx + 1) &
276 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
281 case T3_UNKNOWN_RCV_PROD_RING:
283 Lmstatus = LM_STATUS_FAILURE;
287 /* Bail out if there is any error. */
288 if(Lmstatus != LM_STATUS_SUCCESS)
293 /* Initialize the receive buffer pointer */
294 MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
296 /* The opaque field may point to an offset from a fix addr. */
297 pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
298 MM_UINT_PTR(pDevice->pPacketDescBase));
300 if ((pDevice->Flags & RX_BD_LIMIT_64_FLAG) &&
301 ((Diff + StdBdAdded) >= 63))
303 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
305 pDevice->QueueAgain = TRUE;
309 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
313 /* Update the procedure index. */
316 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low,
317 pDevice->RxStdProdIdx);
318 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
320 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
323 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
326 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
327 pDevice->RxJumboProdIdx);
328 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
330 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
333 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
336 } /* LM_QueueRxPackets */
341 #define EEPROM_CMD_TIMEOUT 100000
342 #define NVRAM_CMD_TIMEOUT 100000
345 /******************************************************************************/
349 /******************************************************************************/
350 STATIC LM_STATUS LM_NVRAM_AcquireLock( PLM_DEVICE_BLOCK pDevice )
356 status = LM_STATUS_SUCCESS;
358 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
359 if (pDevice->Flags & SB_CORE_FLAG)
362 /* Request access to the flash interface. */
363 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_SET1 );
366 * The worst case wait time for Nvram arbitration
367 * using serial eprom is about 45 msec on a 5704
368 * with the other channel loading boot code.
370 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
372 value32 = REG_RD( pDevice, Nvram.SwArb );
373 if( value32 & SW_ARB_GNT1 )
382 } /* LM_NVRAM_AcquireLock */
386 /******************************************************************************/
390 /******************************************************************************/
391 STATIC LM_STATUS LM_NVRAM_ReleaseLock( PLM_DEVICE_BLOCK pDevice )
393 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
394 if (pDevice->Flags & SB_CORE_FLAG)
395 return LM_STATUS_SUCCESS;
397 /* Relinquish nvram interface. */
398 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 );
399 REG_RD_BACK( pDevice, Nvram.SwArb );
401 return LM_STATUS_SUCCESS;
402 } /* LM_NVRAM_ReleaseLock */
406 /******************************************************************************/
410 /******************************************************************************/
412 LM_EEPROM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
418 status = LM_STATUS_SUCCESS;
420 REG_WR( pDevice, Grc.EepromAddr, cmd );
422 for( i = 0; i < EEPROM_CMD_TIMEOUT; i++ )
424 value32 = REG_RD( pDevice, Grc.EepromAddr );
425 if( value32 & SEEPROM_ADDR_COMPLETE )
432 if( i == EEPROM_CMD_TIMEOUT )
434 B57_ERR(("EEPROM command (0x%x) timed out!\n", cmd));
435 status = LM_STATUS_FAILURE;
439 } /* LM_EEPROM_ExecuteCommand */
443 /******************************************************************************/
447 /******************************************************************************/
449 LM_NVRAM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
455 status = LM_STATUS_SUCCESS;
457 REG_WR( pDevice, Nvram.Cmd, cmd );
458 REG_RD_BACK( pDevice, Nvram.Cmd );
461 /* Wait for the command to complete. */
462 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
464 value32 = REG_RD( pDevice, Nvram.Cmd );
465 if( value32 & NVRAM_CMD_DONE )
472 if( i == NVRAM_CMD_TIMEOUT )
474 B57_ERR(("NVRAM command (0x%x) timed out!\n", cmd));
475 status = LM_STATUS_FAILURE;
479 } /* LM_NVRAM_ExecuteCommand */
483 /******************************************************************************/
487 /******************************************************************************/
489 LM_EEPROM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
497 Dev = offset / pDevice->flashinfo.chipsize;
498 Addr = offset % pDevice->flashinfo.chipsize;
500 value32 = REG_RD( pDevice, Grc.EepromAddr );
501 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
502 SEEPROM_ADDR_RW_MASK);
503 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
504 SEEPROM_ADDR_START | SEEPROM_ADDR_READ;
506 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
507 if( status == LM_STATUS_SUCCESS )
509 value32 = REG_RD( pDevice, Grc.EepromData );
511 /* The endianess of the eeprom and flash interface is different */
512 *data = MM_SWAP_LE32( value32 );
516 } /* LM_EEPROM_Read_UINT32 */
520 /******************************************************************************/
524 /******************************************************************************/
526 LM_NVRAM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
534 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
535 pDevice->flashinfo.buffered == TRUE )
538 * One supported flash part has 9 address bits to address a
539 * particular page and another 9 address bits to address a
540 * particular byte within that page.
544 pagenmbr = offset / pDevice->flashinfo.pagesize;
545 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
547 physaddr = pagenmbr + (offset % pDevice->flashinfo.pagesize);
554 REG_WR( pDevice, Nvram.Addr, physaddr );
556 ctrlreg = NVRAM_CMD_DONE | NVRAM_CMD_DO_IT |
557 NVRAM_CMD_LAST | NVRAM_CMD_FIRST | NVRAM_CMD_RD;
559 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
560 if( status == LM_STATUS_SUCCESS )
562 value32 = REG_RD( pDevice, Nvram.ReadData );
565 * Data is swapped so that the byte stream is the same
566 * in big and little endian systems. Caller will do
567 * additional swapping depending on how it wants to
570 *data = MM_SWAP_BE32( value32 );
574 } /* LM_NVRAM_Read_UINT32 */
577 /******************************************************************************/
581 /******************************************************************************/
583 LM_EEPROM_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
590 * Initialize the chipsize to the largest EEPROM size we support.
591 * This will intentionally restrict our sizing operations to the
594 pDevice->flashinfo.chipsize = ATMEL_AT24C512_CHIP_SIZE;
598 /* If anything fails, use the smallest chip as the default chip size. */
599 cursize = ATMEL_AT24C64_CHIP_SIZE;
601 status = LM_NvramRead(pDevice, 0, &value32);
602 if( status != LM_STATUS_SUCCESS )
607 value32 = MM_SWAP_BE32(value32);
608 if( value32 != 0x669955aa )
614 * Size the chip by reading offsets at increasing powers of two.
615 * When we encounter our validation signature, we know the addressing
616 * has wrapped around, and thus have our chip size.
618 while( cursize < ATMEL_AT24C64_CHIP_SIZE )
620 status = LM_NvramRead(pDevice, cursize, &value32);
621 if( status != LM_STATUS_SUCCESS )
623 cursize = ATMEL_AT24C64_CHIP_SIZE;
627 value32 = MM_SWAP_BE32(value32);
628 if( value32 == 0x669955aa )
638 pDevice->flashinfo.pagesize = cursize;
641 } /* LM_EEPROM_ReadSize */
643 /******************************************************************************/
647 /******************************************************************************/
649 LM_FLASH_Atmel_Buffered_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
655 /* Temporarily replace the read command with a "read ID" command. */
656 config3 = REG_RD( pDevice, Nvram.Config3 );
657 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
658 value32 |= NVRAM_READ_COMMAND(0x57);
659 REG_WR( pDevice, Nvram.Config3, value32 );
661 REG_WR( pDevice, Nvram.Addr, 0x0 );
663 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
665 /* Restore the original read command. */
666 REG_WR( pDevice, Nvram.Config3, config3 );
667 if( status == LM_STATUS_SUCCESS )
669 switch( value32 & 0x3c )
672 *size = (1 * (1<<20))/8;
675 *size = (2 * (1<<20))/8;
678 *size = (4 * (1<<20))/8;
681 *size = (8 * (1<<20))/8;
687 } /* LM_FLASH_Atmel_Buffered_ReadSize */
691 /******************************************************************************/
695 /******************************************************************************/
697 LM_FLASH_ST_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
705 /* We need to get the size through pass-thru mode. */
706 config1 = REG_RD( pDevice, Nvram.Config1 );
707 value32 = config1 | FLASH_PASS_THRU_MODE;
708 REG_WR( pDevice, Nvram.Config1, value32 );
710 /* Issue the "read ID" command. */
711 REG_WR( pDevice, Nvram.WriteData, 0x9f );
713 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_FIRST | NVRAM_CMD_WR;
714 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
715 if( status == LM_STATUS_FAILURE )
720 /* Read in the "read ID" response. */
721 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
723 /* Discard the first three bytes. */
724 for( i = 0; i < 2; i++ )
726 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
727 if( status == LM_STATUS_FAILURE )
732 value32 = REG_RD(pDevice, Nvram.ReadData);
735 ctrlreg |= NVRAM_CMD_LAST;
737 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
738 if( status == LM_STATUS_SUCCESS )
740 value32 = REG_RD(pDevice, Nvram.ReadData) & 0xff;
744 *size = (1 * (1<<20)) / 8;
747 *size = (2 * (1<<20)) / 8;
750 *size = (4 * (1<<20)) / 8;
753 *size = (8 * (1<<20)) / 8;
760 /* Restore the previous flash mode. */
761 REG_WR( pDevice, Nvram.Config1, config1 );
764 } /* LM_FLASH_ST_ReadSize */
768 /******************************************************************************/
772 /******************************************************************************/
774 LM_FLASH_Saifun_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
780 /* Temporarily replace the read command with a "read ID" command. */
781 config3 = REG_RD( pDevice, Nvram.Config3 );
782 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
783 value32 |= NVRAM_READ_COMMAND(0xab);
784 REG_WR( pDevice, Nvram.Config3, value32 );
786 REG_WR( pDevice, Nvram.Addr, 0x0 );
788 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
790 /* Restore the original read command. */
791 REG_WR( pDevice, Nvram.Config3, config3 );
793 if( status == LM_STATUS_SUCCESS )
795 switch( value32 & 0xff )
798 *size = (512 * (1<<10)/8);
801 *size = (1 * (1<<20)/8);
804 *size = (2 * (1<<20)/8);
810 } /* LM_FLASH_Saifun_ReadSize */
814 /******************************************************************************/
818 /******************************************************************************/
820 LM_FLASH_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
825 status = LM_NVRAM_AcquireLock( pDevice );
826 if( status == LM_STATUS_FAILURE )
831 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
833 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
835 value32 = REG_RD( pDevice, Nvram.NvmAccess );
836 value32 |= NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE;
837 REG_WR( pDevice, Nvram.NvmAccess, value32 );
841 switch( pDevice->flashinfo.jedecnum )
844 status = LM_FLASH_ST_ReadSize( pDevice, size );
847 if( pDevice->flashinfo.buffered == TRUE )
849 status = LM_FLASH_Atmel_Buffered_ReadSize( pDevice, size );
853 status = LM_STATUS_FAILURE;
857 status = LM_FLASH_Saifun_ReadSize( pDevice, size );
861 status = LM_STATUS_FAILURE;
864 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
866 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
868 value32 = REG_RD( pDevice, Nvram.NvmAccess );
869 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
870 REG_WR( pDevice, Nvram.NvmAccess, value32 );
874 LM_NVRAM_ReleaseLock( pDevice );
877 } /* LM_FLASH_ReadSize */
879 STATIC LM_VOID LM_NVRAM_Detect_570X( PLM_DEVICE_BLOCK pDevice )
883 value32 = REG_RD(pDevice, Nvram.Config1);
885 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
887 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
892 * 5705 and older products do not have bits 24 and 25 defined.
893 * If we've gotten here, then we can guarantee the flash is
894 * an Atmel AT45DB011DB.
896 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
897 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
898 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
899 pDevice->flashinfo.buffered = TRUE;
901 } /* LM_NVRAM_Detect_570X */
903 STATIC LM_VOID LM_NVRAM_Detect_5750( PLM_DEVICE_BLOCK pDevice )
907 value32 = REG_RD(pDevice, Nvram.Config1);
909 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
911 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
915 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
917 switch( value32 & FLASH_PART_5750_TYPEMASK )
919 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
920 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
921 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
922 pDevice->flashinfo.buffered = TRUE;
924 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
925 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
926 pDevice->flashinfo.pagesize = ATMEL_AT25F512_PAGE_SIZE;
927 pDevice->flashinfo.buffered = FALSE;
929 case FLASH_VENDOR_ST:
930 pDevice->flashinfo.jedecnum = JEDEC_ST;
931 pDevice->flashinfo.pagesize = ST_M45PEX0_PAGE_SIZE;
932 pDevice->flashinfo.buffered = TRUE;
934 case FLASH_VENDOR_SAIFUN:
935 pDevice->flashinfo.jedecnum = JEDEC_SAIFUN;
936 pDevice->flashinfo.pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
937 pDevice->flashinfo.buffered = FALSE;
939 case FLASH_VENDOR_SST_SMALL:
940 case FLASH_VENDOR_SST_LARGE:
941 pDevice->flashinfo.jedecnum = JEDEC_SST;
942 pDevice->flashinfo.pagesize = SST_25VF0X0_PAGE_SIZE;
943 pDevice->flashinfo.buffered = FALSE;
946 B57_ERR(("bcm57xx : Unknown NVRAM type.\n"));
947 pDevice->flashinfo.jedecnum = 0;
948 pDevice->flashinfo.romtype = 0;
949 pDevice->flashinfo.buffered = FALSE;
950 pDevice->flashinfo.pagesize = 0;
952 } /* LM_NVRAM_Detect_5750 */
954 STATIC LM_VOID LM_NVRAM_Detect_5752( PLM_DEVICE_BLOCK pDevice )
961 value32 = REG_RD(pDevice, Nvram.Config1);
964 pDevice->Flags |= PROTECTED_NVRAM_FLAG;
966 switch( value32 & FLASH_PART_5752_TYPEMASK )
968 case FLASH_PART_5752_EEPROM_ATMEL_64K:
969 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
970 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
971 pDevice->flashinfo.buffered = FALSE;
972 pDevice->flashinfo.chipsize = (64 * (1<<10)/8);
976 case FLASH_PART_5752_EEPROM_ATMEL_376K:
977 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
978 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
979 pDevice->flashinfo.buffered = FALSE;
980 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
984 case FLASH_PART_5752_FLASH_ATMEL_AT45DB041:
985 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
986 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
987 pDevice->flashinfo.buffered = TRUE;
988 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
992 case FLASH_PART_5752_FLASH_ATMEL_AT25F512:
993 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
994 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
995 pDevice->flashinfo.buffered = FALSE;
996 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1000 case FLASH_PART_5752_FLASH_ST_M25P10A:
1001 pDevice->flashinfo.jedecnum = JEDEC_ST;
1002 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1003 pDevice->flashinfo.buffered = TRUE;
1004 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1007 case FLASH_PART_5752_FLASH_ST_M25P05A:
1008 pDevice->flashinfo.jedecnum = JEDEC_ST;
1009 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1010 pDevice->flashinfo.buffered = TRUE;
1011 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1015 case FLASH_PART_5752_FLASH_ST_M45PE10:
1016 pDevice->flashinfo.jedecnum = JEDEC_ST;
1017 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1018 pDevice->flashinfo.buffered = TRUE;
1019 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1023 case FLASH_PART_5752_FLASH_ST_M45PE20:
1024 pDevice->flashinfo.jedecnum = JEDEC_ST;
1025 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1026 pDevice->flashinfo.buffered = TRUE;
1027 pDevice->flashinfo.chipsize = (2 * (1<<20)) / 8;
1031 case FLASH_PART_5752_FLASH_ST_M45PE40:
1032 pDevice->flashinfo.jedecnum = JEDEC_ST;
1033 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1034 pDevice->flashinfo.buffered = TRUE;
1035 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
1039 B57_ERR(("bcm57xx : Unknown NVRAM type.\n"));
1042 if( pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1044 switch( value32 & FLASH_PART_5752_PAGEMASK )
1046 case FLASH_PART_5752_PAGE_SIZE_256B:
1047 pDevice->flashinfo.pagesize = 256;
1049 case FLASH_PART_5752_PAGE_SIZE_512B:
1050 pDevice->flashinfo.pagesize = 512;
1052 case FLASH_PART_5752_PAGE_SIZE_1K:
1053 pDevice->flashinfo.pagesize = 1024;
1055 case FLASH_PART_5752_PAGE_SIZE_2K:
1056 pDevice->flashinfo.pagesize = 2048;
1058 case FLASH_PART_5752_PAGE_SIZE_4K:
1059 pDevice->flashinfo.pagesize = 4096;
1061 case FLASH_PART_5752_PAGE_SIZE_264B:
1062 pDevice->flashinfo.pagesize = 264;
1065 B57_ERR(("bcm57xx : Unknown NVRAM page size.\n"));
1070 if( supported != TRUE )
1072 B57_ERR(("Flash type unsupported!!!\n"));
1073 pDevice->flashinfo.jedecnum = 0;
1074 pDevice->flashinfo.romtype = 0;
1075 pDevice->flashinfo.buffered = FALSE;
1076 pDevice->flashinfo.pagesize = 0;
1080 } /* LM_NVRAM_Detect_5752 */
1083 /******************************************************************************/
1087 /******************************************************************************/
1088 STATIC LM_VOID LM_NVRAM_Init( PLM_DEVICE_BLOCK pDevice )
1092 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1093 if (pDevice->Flags & SB_CORE_FLAG)
1096 pDevice->NvramSize = 0;
1098 /* Intialize clock period and state machine. */
1099 Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
1100 SEEPROM_ADDR_FSM_RESET;
1101 REG_WR(pDevice, Grc.EepromAddr, Value32);
1102 REG_RD_BACK(pDevice, Grc.EepromAddr);
1106 /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
1107 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
1108 REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
1110 switch( T3_ASIC_REV(pDevice->ChipRevId) )
1112 case T3_ASIC_REV_5700:
1113 case T3_ASIC_REV_5701:
1114 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1116 case T3_ASIC_REV_5752:
1117 LM_NVRAM_Detect_5752(pDevice);
1119 case T3_ASIC_REV_5714_A0:
1120 case T3_ASIC_REV_5780:
1121 case T3_ASIC_REV_5714:
1122 case T3_ASIC_REV_5750:
1123 LM_NVRAM_Detect_5750(pDevice);
1126 LM_NVRAM_Detect_570X(pDevice);
1129 /* Set the 5701 compatibility mode if we are using EEPROM. */
1130 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1131 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 &&
1132 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1134 Value32 = REG_RD(pDevice, Nvram.Config1);
1136 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1138 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1140 REG_WR(pDevice, Nvram.NvmAccess,
1141 REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN);
1145 /* Use the new interface to read EEPROM. */
1146 Value32 &= ~FLASH_COMPAT_BYPASS;
1148 REG_WR(pDevice, Nvram.Config1, Value32);
1150 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1152 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1154 REG_WR(pDevice, Nvram.NvmAccess,
1155 REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN);
1160 if( !(T3_ASIC_5752(pDevice->ChipRevId)) )
1162 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1164 /* The only EEPROM we support is an ATMEL */
1165 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1166 pDevice->flashinfo.pagesize = 0;
1167 pDevice->flashinfo.buffered = FALSE;
1169 LM_EEPROM_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1173 LM_FLASH_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1174 pDevice->Flags |= FLASH_DETECTED_FLAG;
1178 pDevice->NvramSize = pDevice->flashinfo.chipsize;
1180 B57_INFO(("*nvram:size=0x%x jnum=0x%x page=0x%x buff=0x%x \n",
1181 pDevice->NvramSize, pDevice->flashinfo.jedecnum,
1182 pDevice->flashinfo.pagesize, pDevice->flashinfo.buffered));
1184 } /* LM_NVRAM_Init */
1188 /******************************************************************************/
1192 /******************************************************************************/
1194 LM_NvramRead( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset, LM_UINT32 * data )
1199 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1200 if (pDevice->Flags & SB_CORE_FLAG) {
1202 return LM_STATUS_FAILURE;
1205 if( offset >= pDevice->flashinfo.chipsize )
1207 return LM_STATUS_FAILURE;
1210 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1211 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1213 status = LM_EEPROM_Read_UINT32( pDevice, offset, data );
1217 status = LM_NVRAM_AcquireLock( pDevice );
1218 if( status == LM_STATUS_FAILURE )
1223 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1225 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1227 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1228 value32 |= NVRAM_ACCESS_ENABLE;
1229 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1233 status = LM_NVRAM_Read_UINT32(pDevice, offset, data);
1235 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1237 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1239 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1240 value32 &= ~NVRAM_ACCESS_ENABLE;
1241 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1245 LM_NVRAM_ReleaseLock( pDevice );
1249 } /* LM_NvramRead */
1253 #ifdef ETHTOOL_SEEPROM
1255 /******************************************************************************/
1259 /******************************************************************************/
1261 LM_NVRAM_ReadBlock(PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1262 LM_UINT8 *data, LM_UINT32 size)
1269 status = LM_STATUS_SUCCESS;
1273 /* Make sure the read is word aligned. */
1274 value32 = offset & 0x3;
1277 bytecnt = sizeof(LM_UINT32) - value32;
1279 srcptr = (LM_UINT8 *)(&value32) + value32;
1283 bytecnt = sizeof(LM_UINT32);
1284 srcptr = (LM_UINT8 *)(&value32);
1287 if( bytecnt > size )
1292 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1293 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 )
1295 status = LM_NVRAM_Read_UINT32( pDevice, offset, &value32 );
1299 status = LM_EEPROM_Read_UINT32( pDevice, offset, &value32 );
1302 if( status != LM_STATUS_SUCCESS )
1307 memcpy( data, srcptr, bytecnt );
1309 offset += sizeof(LM_UINT32);
1315 } /* LM_NVRAM_ReadBlock */
1317 /******************************************************************************/
1321 /******************************************************************************/
1323 LM_EEPROM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1324 LM_UINT8 * data, LM_UINT32 size )
1335 if( offset > pDevice->flashinfo.chipsize )
1337 return LM_STATUS_FAILURE;
1340 status = LM_STATUS_SUCCESS;
1350 * If our initial offset does not fall on a word boundary, we
1351 * have to do a read / modify / write to preserve the
1352 * preceding bits we are not interested in.
1354 status = LM_EEPROM_Read_UINT32(pDevice, offset & ~0x3, &subword1);
1355 if( status == LM_STATUS_FAILURE )
1361 if( (offset + size) & 0x3 )
1364 * Likewise, if our ending offset does not fall on a word
1365 * boundary, we have to do a read / modify / write to
1366 * preserve the trailing bits we are not interested in.
1368 status = LM_EEPROM_Read_UINT32( pDevice, (offset + size) & ~0x3,
1370 if( status == LM_STATUS_FAILURE )
1376 /* Enable EEPROM write. */
1377 if( pDevice->Flags & EEPROM_WP_FLAG )
1379 REG_WR( pDevice, Grc.LocalCtrl,
1380 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1 );
1381 REG_RD_BACK( pDevice, Grc.LocalCtrl );
1384 value32 = REG_RD( pDevice, Grc.LocalCtrl );
1385 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1387 return LM_STATUS_FAILURE;
1393 value32 = offset & 0x3;
1397 * We have to read / modify / write the data to
1398 * preserve the flash contents preceding the offset.
1402 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1403 bytecnt = sizeof(LM_UINT32) - value32;
1406 else if( size < sizeof(LM_UINT32) )
1408 dstptr = (LM_UINT8 *)(&value32);
1414 dstptr = (LM_UINT8 *)(&value32);
1415 bytecnt = sizeof(LM_UINT32);
1418 if( size < bytecnt )
1423 memcpy( dstptr, (void *)data, bytecnt );
1429 * Swap the data so that the byte stream will be
1430 * written the same in little and big endian systems.
1432 value32 = MM_SWAP_LE32(value32);
1434 /* Set the write value to the eeprom */
1435 REG_WR( pDevice, Grc.EepromData, value32 );
1437 Dev = offset / pDevice->flashinfo.chipsize;
1438 Addr = offset % pDevice->flashinfo.chipsize;
1440 value32 = REG_RD( pDevice, Grc.EepromAddr );
1441 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
1442 SEEPROM_ADDR_RW_MASK);
1443 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
1444 SEEPROM_ADDR_START | SEEPROM_ADDR_WRITE;
1446 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
1447 if( status != LM_STATUS_SUCCESS )
1452 offset += sizeof(LM_UINT32);
1455 /* Write-protect EEPROM. */
1456 if( pDevice->Flags & EEPROM_WP_FLAG )
1458 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1459 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1460 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1461 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1466 } /* LM_EEPROM_WriteBlock */
1470 /******************************************************************************/
1474 /******************************************************************************/
1476 LM_NVRAM_WriteBlockUnBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1477 LM_UINT8 * data, LM_UINT32 size )
1488 /* Cache the pagesize. */
1489 pagesize = pDevice->flashinfo.pagesize;
1491 if( pDevice->flashinfo.jedecnum == JEDEC_SAIFUN )
1493 /* Config2 = 0x500d8 */
1494 /* Config3 = 0x3840253 */
1495 /* Write1 = 0xaf000400 */
1497 /* Configure the erase command to be "page erase". */
1498 /* Configure the status command to be "read status register". */
1499 value32 = REG_RD( pDevice, Nvram.Config2 );
1500 value32 &= ~(NVRAM_STATUS_COMMAND( NVRAM_COMMAND_MASK ) |
1501 NVRAM_ERASE_COMMAND( NVRAM_COMMAND_MASK ));
1502 value32 |= NVRAM_STATUS_COMMAND( SAIFUN_SA25F0XX_READ_STATUS_CMD ) |
1503 NVRAM_ERASE_COMMAND( SAIFUN_SA25F0XX_PAGE_ERASE_CMD );
1504 REG_WR( pDevice, Nvram.Config2, value32 );
1506 /* Configure the write command to be "page write". */
1507 value32 = REG_RD( pDevice, Nvram.Config3 );
1508 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1509 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( SAIFUN_SA25F0XX_PAGE_WRITE_CMD );
1510 REG_WR( pDevice, Nvram.Config3, value32 );
1512 /* Make sure the "write enable" command is correct. */
1513 value32 = REG_RD( pDevice, Nvram.Write1 );
1514 value32 &= ~NVRAM_WRITE1_WRENA_CMD( NVRAM_COMMAND_MASK );
1515 value32 |= NVRAM_WRITE1_WRENA_CMD( SAIFUN_SA25F0XX_WRENA_CMD );
1516 REG_WR( pDevice, Nvram.Write1, value32 );
1518 pagemask = SAIFUN_SA25F0XX_PAGE_MASK;
1522 /* Unsupported flash type */
1523 return LM_STATUS_FAILURE;
1528 status = LM_STATUS_SUCCESS;
1534 /* Align the offset to a page boundary. */
1535 physaddr = offset & ~pagemask;
1537 status = LM_NVRAM_ReadBlock( pDevice, physaddr,
1538 pDevice->flashbuffer,
1540 if( status == LM_STATUS_FAILURE )
1545 /* Calculate the target index. */
1546 tgtoff = offset & pagemask;
1548 /* Copy the new data into the save buffer. */
1549 for( i = tgtoff; i < pagesize && size > 0; i++ )
1551 pDevice->flashbuffer[i] = *data++;
1555 /* Move the offset to the next page. */
1556 offset = offset + (pagesize - tgtoff);
1559 * The LM_NVRAM_ReadBlock() function releases
1560 * the access enable bit. Reacquire it.
1562 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1563 REG_WR(pDevice, Nvram.NvmAccess, NVRAM_ACCESS_ENABLE);
1567 * Before we can erase the flash page, we need
1568 * to issue a special "write enable" command.
1570 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1572 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1573 if( status == LM_STATUS_FAILURE )
1578 /* Erase the target page */
1579 REG_WR(pDevice, Nvram.Addr, physaddr);
1581 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR |
1582 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
1584 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1585 if( status == LM_STATUS_FAILURE )
1590 /* Issue another write enable to start the write. */
1591 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1593 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1594 if( status == LM_STATUS_FAILURE )
1599 /* Copy the data into our NIC's buffers. */
1600 for( i = 0; i < pagesize; i+= 4 )
1602 value32 = *((LM_UINT32 *)(&pDevice->flashbuffer[i]));
1603 value32 = MM_SWAP_BE32( value32 );
1605 /* Write the location we wish to write to. */
1606 REG_WR( pDevice, Nvram.Addr, physaddr );
1608 /* Write the data we wish to write. */
1609 REG_WR( pDevice, Nvram.WriteData, value32 );
1611 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR;
1615 ctrlreg |= NVRAM_CMD_FIRST;
1617 else if( i == (pagesize - 4) )
1619 ctrlreg |= NVRAM_CMD_LAST;
1622 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1623 if( status == LM_STATUS_FAILURE )
1629 physaddr += sizeof(LM_UINT32);
1633 /* Paranoia. Turn off the "write enable" flag. */
1634 ctrlreg = NVRAM_CMD_WRITE_DISABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1636 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1641 } /* LM_NVRAM_WriteBlockUnBuffered */
1645 /******************************************************************************/
1649 /******************************************************************************/
1651 LM_NVRAM_WriteBlockBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1652 LM_UINT8 * data, LM_UINT32 size )
1664 if(T3_ASIC_5752(pDevice->ChipRevId) &&
1665 (pDevice->flashinfo.jedecnum == JEDEC_ST ||
1666 pDevice->flashinfo.jedecnum == JEDEC_ATMEL ))
1668 /* Do nothing as the 5752 does will take care of it */
1670 else if( pDevice->flashinfo.jedecnum == JEDEC_ST )
1673 * Program our chip to look at bit0 of the NVRAM's status
1674 * register when polling the write or erase operation status.
1676 value32 = REG_RD(pDevice, Nvram.Config1);
1677 value32 &= ~FLASH_STATUS_BITS_MASK;
1678 REG_WR( pDevice, Nvram.Config1, value32 );
1680 /* Program the "read status" and "page erase" commands. */
1681 value32 = NVRAM_STATUS_COMMAND( ST_M45PEX0_READ_STATUS_CMD ) |
1682 NVRAM_ERASE_COMMAND( ST_M45PEX0_PAGE_ERASE_CMD );
1683 REG_WR( pDevice, Nvram.Config2, value32 );
1685 /* Set the write command to be "page program". */
1686 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1687 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1688 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ST_M45PEX0_PAGE_PRGM_CMD );
1689 REG_WR( pDevice, Nvram.Config3, value32 );
1691 /* Set the "write enable" and "write disable" commands. */
1692 value32 = NVRAM_WRITE1_WRENA_CMD( ST_M45PEX0_WRENA_CMD ) |
1693 NVRAM_WRITE1_WRDIS_CMD( ST_M45PEX0_WRDIS_CMD );
1694 REG_WR( pDevice, Nvram.Write1, value32 );
1696 else if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL )
1698 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1703 Config3 = 0xa184a053
1707 else if( pDevice->flashinfo.buffered == TRUE )
1710 * Program our chip to look at bit7 of the NVRAM's status
1711 * register when polling the write operation status.
1713 value32 = REG_RD(pDevice, Nvram.Config1);
1714 value32 |= FLASH_STATUS_BITS_MASK;
1715 REG_WR( pDevice, Nvram.Config1, value32 );
1717 /* Set the write command to be "page program". */
1718 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1719 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1720 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD );
1721 REG_WR( pDevice, Nvram.Config3, value32 );
1722 /* Config1 = 0x2008273 */
1723 /* Config2 = 0x00570081 */
1724 /* Config3 = 0x68848353 */
1728 /* NVRAM type unsupported. */
1729 return LM_STATUS_FAILURE;
1734 /* NVRAM type unsupported. */
1735 return LM_STATUS_FAILURE;
1738 status = LM_STATUS_SUCCESS;
1743 * If our initial offset does not fall on a word boundary, we
1744 * have to do a read / modify / write to preserve the
1745 * preceding bits we are not interested in.
1747 status = LM_NVRAM_ReadBlock( pDevice, offset & ~0x3,
1748 (LM_UINT8 *)&subword1,
1750 if( status == LM_STATUS_FAILURE )
1756 if( (offset + size) & 0x3 )
1759 * Likewise, if our ending offset does not fall on a word
1760 * boundary, we have to do a read / modify / write to
1761 * preserve the trailing bits we are not interested in.
1763 status = LM_NVRAM_ReadBlock( pDevice, (offset + size) & ~0x3,
1764 (LM_UINT8 *)&subword2,
1766 if( status == LM_STATUS_FAILURE )
1772 ctrlreg = NVRAM_CMD_FIRST;
1776 value32 = offset & 0x3;
1780 * We have to read / modify / write the data to
1781 * preserve the flash contents preceding the offset.
1785 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1786 bytecnt = sizeof(LM_UINT32) - value32;
1789 else if( size < sizeof(LM_UINT32) )
1791 dstptr = (LM_UINT8 *)(&value32);
1797 dstptr = (LM_UINT8 *)(&value32);
1798 bytecnt = sizeof(LM_UINT32);
1801 if( size < bytecnt )
1806 memcpy( dstptr, (void *)data, bytecnt );
1812 * Swap the data so that the byte stream will be
1813 * written the same in little and big endian systems.
1815 value32 = MM_SWAP_BE32(value32);
1817 /* Set the desired write data value to the flash. */
1818 REG_WR(pDevice, Nvram.WriteData, value32);
1820 pageoff = offset % pDevice->flashinfo.pagesize;
1822 /* Set the target address. */
1823 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
1824 pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1827 * If we're dealing with the special ATMEL part, we need to
1828 * convert the submitted offset before it can be considered
1829 * a physical address.
1833 pagenmbr = offset / pDevice->flashinfo.pagesize;
1834 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
1836 physaddr = pagenmbr + pageoff;
1843 REG_WR(pDevice, Nvram.Addr, physaddr);
1845 ctrlreg |= (NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR);
1849 /* Set CMD_FIRST when we are at the beginning of a page. */
1850 ctrlreg |= NVRAM_CMD_FIRST;
1852 else if( pageoff == (pDevice->flashinfo.pagesize - 4) )
1855 * Enable the write to the current page
1856 * before moving on to the next one.
1858 ctrlreg |= NVRAM_CMD_LAST;
1863 ctrlreg |= NVRAM_CMD_LAST;
1866 if( pDevice->flashinfo.jedecnum == JEDEC_ST &&
1867 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) ||
1868 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714)) &&
1869 (ctrlreg & NVRAM_CMD_FIRST) )
1873 REG_WR(pDevice, Nvram.Write1, ST_M45PEX0_WRENA_CMD);
1875 /* We need to issue a special "write enable" command first. */
1876 wrencmd = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1878 status = LM_NVRAM_ExecuteCommand( pDevice, wrencmd );
1879 if( status == LM_STATUS_FAILURE )
1885 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1887 /* We always do complete word writes to eeprom. */
1888 ctrlreg |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
1891 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1892 if( status == LM_STATUS_FAILURE )
1897 offset += sizeof(LM_UINT32);
1902 } /* LM_NVRAM_WriteBlockBuffered */
1906 /******************************************************************************/
1910 /******************************************************************************/
1911 LM_STATUS LM_NVRAM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1912 LM_UINT8 * data, LM_UINT32 size )
1917 if( offset > pDevice->flashinfo.chipsize ||
1918 (offset + size) > pDevice->flashinfo.chipsize )
1920 return LM_STATUS_FAILURE;
1925 return LM_STATUS_SUCCESS;
1928 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1929 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1931 status = LM_EEPROM_WriteBlock( pDevice, offset, data, size );
1935 status = LM_NVRAM_AcquireLock( pDevice );
1936 if( status == LM_STATUS_FAILURE )
1941 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1943 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1945 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1946 value32 |= (NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1947 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1951 /* Enable EEPROM write. */
1952 if( pDevice->Flags & EEPROM_WP_FLAG )
1954 REG_WR(pDevice, Grc.LocalCtrl,
1955 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1);
1956 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1959 value32 = REG_RD(pDevice, Grc.LocalCtrl);
1960 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1962 status = LM_STATUS_FAILURE;
1967 value32 = REG_RD(pDevice, Grc.Mode);
1968 value32 |= GRC_MODE_NVRAM_WRITE_ENABLE;
1969 REG_WR(pDevice, Grc.Mode, value32);
1971 if( pDevice->flashinfo.buffered == TRUE ||
1972 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1974 status = LM_NVRAM_WriteBlockBuffered(pDevice, offset, data, size);
1978 status = LM_NVRAM_WriteBlockUnBuffered(pDevice, offset, data, size);
1981 value32 = REG_RD(pDevice, Grc.Mode);
1982 value32 &= ~GRC_MODE_NVRAM_WRITE_ENABLE;
1983 REG_WR(pDevice, Grc.Mode, value32);
1985 if( pDevice->Flags & EEPROM_WP_FLAG )
1987 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1988 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1989 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1990 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1996 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1998 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
2000 value32 = REG_RD(pDevice, Nvram.NvmAccess);
2001 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
2002 REG_WR(pDevice, Nvram.NvmAccess, value32);
2006 LM_NVRAM_ReleaseLock( pDevice );
2010 } /* LM_NVRAM_WriteBlock */
2013 LM_STATUS LM_NvramWriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
2014 LM_UINT32 * data, LM_UINT32 size )
2016 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
2017 if (pDevice->Flags & SB_CORE_FLAG)
2018 return LM_STATUS_FAILURE;
2020 return LM_NVRAM_WriteBlock( pDevice, offset, (LM_UINT8 *)data, size * 4 );
2023 #endif /* ETHTOOL_SEEPROM */
2027 bcm_ether_atoe(char *p, struct ether_addr *ea)
2032 ea->octet[i++] = (char) simple_strtoul(p, &p, 16);
2033 if (!*p++ || i == 6)
2040 /******************************************************************************/
2042 /* This routine initializes default parameters and reads the PCI */
2043 /* configurations. */
2046 /* LM_STATUS_SUCCESS */
2047 /******************************************************************************/
2050 PLM_DEVICE_BLOCK pDevice)
2052 PLM_ADAPTER_INFO pAdapterInfo;
2053 LM_UINT32 Value32, LedCfg, Ver;
2055 LM_UINT32 EeSigFound;
2056 LM_UINT32 EePhyTypeSerdes = 0;
2057 LM_UINT32 EePhyId = 0;
2059 /* Get Device Id and Vendor Id */
2060 Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
2061 if(Status != LM_STATUS_SUCCESS)
2065 pDevice->PciVendorId = (LM_UINT16) Value32;
2066 pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
2068 Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
2069 if(Status != LM_STATUS_SUCCESS)
2073 pDevice->PciRevId = (LM_UINT8) Value32;
2075 /* Get chip revision id. */
2076 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2077 pDevice->ChipRevId = Value32 >> 16;
2079 /* determine if it is PCIE system */
2080 if( (Value32 = MM_FindCapability(pDevice, T3_PCIE_CAPABILITY_ID)) != 0)
2082 pDevice->Flags |= PCI_EXPRESS_FLAG;
2085 /* Get subsystem vendor. */
2086 Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
2087 if(Status != LM_STATUS_SUCCESS)
2091 pDevice->SubsystemVendorId = (LM_UINT16) Value32;
2093 /* Get PCI subsystem id. */
2094 pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
2096 /* Read bond id for baxter A0 since it has same rev id as hamilton A0*/
2098 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714_A0) {
2099 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 | MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2101 Value32 = LM_RegRdInd(pDevice, 0x6804);
2102 Value32 &= GRC_MISC_BD_ID_MASK;
2104 if((Value32 == 0)||(Value32 == 0x8000)) {
2105 pDevice->ChipRevId = T3_CHIP_ID_5752_A0;
2107 pDevice->ChipRevId = T3_CHIP_ID_5714_A0;
2110 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2111 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 & ~ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2115 /* Get the cache line size. */
2116 MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
2117 pDevice->CacheLineSize = (LM_UINT8) Value32;
2118 pDevice->SavedCacheLineReg = Value32;
2120 if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
2121 pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
2122 pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
2124 pDevice->Flags &= ~UNDI_FIX_FLAG;
2126 #ifndef PCIX_TARGET_WORKAROUND
2127 pDevice->Flags &= ~UNDI_FIX_FLAG;
2129 /* Map the memory base to system address space. */
2130 if (!(pDevice->Flags & UNDI_FIX_FLAG))
2132 Status = MM_MapMemBase(pDevice);
2133 if(Status != LM_STATUS_SUCCESS)
2137 /* Initialize the memory view pointer. */
2138 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
2141 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) ||
2142 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2144 pDevice->Flags |= TX_4G_WORKAROUND_FLAG;
2146 if ( (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
2147 (pDevice->Flags == PCI_EXPRESS_FLAG))
2149 pDevice->Flags |= REG_RD_BACK_FLAG;
2152 if(pDevice->ChipRevId==T3_CHIP_ID_5750_A0)
2153 return LM_STATUS_UNKNOWN_ADAPTER;
2155 #ifdef PCIX_TARGET_WORKAROUND
2156 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2157 if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
2159 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
2161 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2164 if (pDevice->Flags & UNDI_FIX_FLAG)
2166 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2169 /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
2170 /* management register may be clobbered which may cause the */
2171 /* BCM5700 to go into D3 state. While in this state, we will */
2172 /* need to restore the device to D0 state. */
2173 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
2174 Value32 |= T3_PM_PME_ASSERTED;
2175 Value32 &= ~T3_PM_POWER_STATE_MASK;
2176 Value32 |= T3_PM_POWER_STATE_D0;
2177 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
2179 /* read the current PCI command word */
2180 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
2182 /* Make sure bus-mastering is enabled. */
2183 Value32 |= PCI_BUSMASTER_ENABLE;
2185 #ifdef PCIX_TARGET_WORKAROUND
2186 /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
2188 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) {
2189 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
2190 PCI_PARITY_ERROR_ENABLE);
2192 if (pDevice->Flags & UNDI_FIX_FLAG)
2194 Value32 &= ~PCI_MEM_SPACE_ENABLE;
2199 if (pDevice->Flags & ENABLE_MWI_FLAG)
2201 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
2204 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
2207 /* save the value we are going to write into the PCI command word */
2208 pDevice->PciCommandStatusWords = Value32;
2210 Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
2211 if(Status != LM_STATUS_SUCCESS)
2216 /* Setup the mode registers. */
2217 pDevice->MiscHostCtrl =
2218 MISC_HOST_CTRL_MASK_PCI_INT |
2219 MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
2220 #ifdef BIG_ENDIAN_HOST
2221 MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
2222 #endif /* BIG_ENDIAN_HOST */
2223 MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
2224 MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
2225 /* write to PCI misc host ctr first in order to enable indirect accesses */
2226 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
2228 /* Set power state to D0. */
2229 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
2231 /* Preserve HOST_STACK_UP bit in case ASF firmware is running */
2232 Value32 = REG_RD(pDevice, Grc.Mode) & GRC_MODE_HOST_STACK_UP;
2233 #ifdef BIG_ENDIAN_HOST
2234 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2235 GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
2237 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
2239 REG_WR(pDevice, Grc.Mode, Value32);
2241 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
2243 REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
2244 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
2245 REG_RD_BACK(pDevice, Grc.LocalCtrl);
2249 /* Enable memory arbiter*/
2250 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
2252 Value32 = REG_RD(pDevice,MemArbiter.Mode);
2253 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
2257 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
2261 LM_SwitchClocks(pDevice);
2263 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
2265 /* Check to see if PXE ran and did not shutdown properly */
2266 if ((REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE) ||
2267 !(REG_RD(pDevice, PciCfg.MiscHostCtrl) & MISC_HOST_CTRL_MASK_PCI_INT))
2269 LM_DisableInterrupt(pDevice);
2270 /* assume ASF is enabled */
2271 pDevice->AsfFlags = ASF_ENABLED;
2272 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2274 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2276 LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET);
2277 pDevice->AsfFlags = 0;
2279 #ifdef PCIX_TARGET_WORKAROUND
2280 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2281 if (!(pDevice->Flags & ENABLE_PCIX_FIX_FLAG) &&
2282 ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
2284 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
2285 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
2286 pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
2287 pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
2289 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]), 0);
2290 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), 0);
2291 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]),
2293 if (MM_MEMREADL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
2295 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2301 LM_NVRAM_Init(pDevice);
2303 Status = LM_STATUS_FAILURE;
2305 /* BCM4785: Use the MAC address stored in the main flash. */
2306 if (pDevice->Flags & SB_CORE_FLAG) {
2307 bcm_ether_atoe(getvar(NULL, "et0macaddr"), (struct ether_addr *)pDevice->NodeAddress);
2308 Status = LM_STATUS_SUCCESS;
2310 /* Get the node address. First try to get in from the shared memory. */
2311 /* If the signature is not present, then get it from the NVRAM. */
2312 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
2313 if((Value32 >> 16) == 0x484b)
2317 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
2318 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
2320 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
2322 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
2323 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
2324 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
2325 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
2327 /* Check for null MAC address which can happen with older boot code */
2328 for (i = 0; i < 6; i++)
2330 if (pDevice->NodeAddress[i] != 0)
2332 Status = LM_STATUS_SUCCESS;
2339 if (Status != LM_STATUS_SUCCESS)
2344 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
2345 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)) )
2347 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
2351 /* the boot code is not running */
2352 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS)
2354 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
2358 LM_NVRAM_ReleaseLock(pDevice);
2362 Status = LM_NvramRead(pDevice, MacOffset, &Value32);
2363 if(Status == LM_STATUS_SUCCESS)
2365 LM_UINT8 *c = (LM_UINT8 *) &Value32;
2367 pDevice->NodeAddress[0] = c[2];
2368 pDevice->NodeAddress[1] = c[3];
2370 Status = LM_NvramRead(pDevice, MacOffset + 4, &Value32);
2372 c = (LM_UINT8 *) &Value32;
2373 pDevice->NodeAddress[2] = c[0];
2374 pDevice->NodeAddress[3] = c[1];
2375 pDevice->NodeAddress[4] = c[2];
2376 pDevice->NodeAddress[5] = c[3];
2380 if(Status != LM_STATUS_SUCCESS)
2382 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].High);
2383 pDevice->NodeAddress[0] = (Value32 >> 8) & 0xff;
2384 pDevice->NodeAddress[1] = Value32 & 0xff;
2385 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].Low);
2386 pDevice->NodeAddress[2] = (Value32 >> 24) & 0xff;
2387 pDevice->NodeAddress[3] = (Value32 >> 16) & 0xff;
2388 pDevice->NodeAddress[4] = (Value32 >> 8) & 0xff;
2389 pDevice->NodeAddress[5] = Value32 & 0xff;
2390 B57_ERR(("WARNING: Cannot get MAC addr from NVRAM, using %2.2x%2.2x%2.2x%2.2x%2.2x%2.2x\n",
2391 pDevice->NodeAddress[0], pDevice->NodeAddress[1],
2392 pDevice->NodeAddress[2], pDevice->NodeAddress[3],
2393 pDevice->NodeAddress[4], pDevice->NodeAddress[5]));
2396 memcpy(pDevice->PermanentNodeAddress, pDevice->NodeAddress, 6);
2398 /* Initialize the default values. */
2399 pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
2400 pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
2401 pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
2402 pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
2403 pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
2404 pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
2405 pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2406 pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2407 pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2408 pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2409 pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
2410 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2411 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2412 pDevice->DisableAutoNeg = FALSE;
2413 pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
2414 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
2416 pDevice->PhyFlags = 0;
2418 if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
2419 pDevice->Flags |= DELAY_PCI_GRANT_FLAG;
2421 pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO;
2422 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
2423 pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
2424 pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
2425 #ifdef INCLUDE_TBI_SUPPORT
2426 pDevice->TbiFlags = 0;
2427 pDevice->IgnoreTbiLinkChange = FALSE;
2429 #ifdef INCLUDE_TCP_SEG_SUPPORT
2430 pDevice->LargeSendMaxSize = T3_TCP_SEG_MAX_OFFLOAD_SIZE;
2431 pDevice->LargeSendMinNumSeg = T3_TCP_SEG_MIN_NUM_SEG;
2434 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2435 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2436 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
2438 pDevice->PhyFlags |= PHY_RESET_ON_LINKDOWN;
2439 pDevice->PhyFlags |= PHY_CHECK_TAPS_AFTER_RESET;
2441 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5703_AX) ||
2442 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2444 pDevice->PhyFlags |= PHY_ADC_FIX;
2446 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
2448 pDevice->PhyFlags |= PHY_5704_A0_FIX;
2450 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
2452 pDevice->PhyFlags |= PHY_5705_5750_FIX;
2454 /* Ethernet@Wirespeed is supported on 5701,5702,5703,5704,5705a0,5705a1 */
2455 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2456 !((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
2457 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0) &&
2458 (pDevice->ChipRevId != T3_CHIP_ID_5705_A1)))
2460 pDevice->PhyFlags |= PHY_ETHERNET_WIRESPEED;
2463 switch (T3_ASIC_REV(pDevice->ChipRevId))
2465 case T3_ASIC_REV_5704:
2466 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2467 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
2470 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2471 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
2475 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
2476 pDevice->QueueRxPackets = TRUE;
2478 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2480 if(T3_ASIC_IS_JUMBO_CAPABLE(pDevice->ChipRevId)){
2481 if( ! T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
2482 pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
2483 pDevice->Flags |= JUMBO_CAPABLE_FLAG;
2486 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2488 pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
2490 if(((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
2491 ((pDevice->BondId == 0x10000) || (pDevice->BondId == 0x18000))) ||
2492 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) &&
2493 ((pDevice->BondId == 0x14000) || (pDevice->BondId == 0x1c000))))
2495 return LM_STATUS_UNKNOWN_ADAPTER;
2497 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
2499 if ((pDevice->BondId == 0x8000) || (pDevice->BondId == 0x4000))
2501 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2504 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
2506 if ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
2507 (pDevice->BondId == GRC_MISC_BD_ID_5788M))
2509 pDevice->Flags |= BCM5788_FLAG;
2512 if ((pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901)) ||
2513 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901A2)) ||
2514 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5705F)))
2516 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2520 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750)
2522 if ( (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5751F))||
2523 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5753F)))
2525 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2529 /* CIOBE multisplit has a bug */
2531 /* Get Eeprom info. */
2532 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
2533 if (Value32 == T3_NIC_DATA_SIG)
2536 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
2538 /* For now the 5753 cannot drive gpio2 or ASF will blow */
2539 if(Value32 & T3_NIC_GPIO2_NOT_AVAILABLE)
2541 pDevice->Flags |= GPIO2_DONOT_OUTPUT;
2544 if (Value32 & T3_NIC_MINI_PCI)
2546 pDevice->Flags |= MINI_PCI_FLAG;
2548 /* Determine PHY type. */
2549 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
2551 case T3_NIC_CFG_PHY_TYPE_COPPER:
2552 EePhyTypeSerdes = FALSE;
2555 case T3_NIC_CFG_PHY_TYPE_FIBER:
2556 EePhyTypeSerdes = TRUE;
2560 EePhyTypeSerdes = FALSE;
2564 if ( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2566 LedCfg = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2567 LedCfg = LedCfg & (T3_NIC_CFG_LED_MODE_MASK |
2568 T3_SHASTA_EXT_LED_MODE_MASK);
2572 /* Determine PHY led mode. for legacy devices */
2573 LedCfg = Value32 & T3_NIC_CFG_LED_MODE_MASK;
2579 case T3_NIC_CFG_LED_PHY_MODE_1:
2580 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
2583 case T3_NIC_CFG_LED_PHY_MODE_2:
2584 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2587 case T3_NIC_CFG_LED_MAC_MODE:
2588 pDevice->LedCtrl = LED_CTRL_MAC_MODE;
2591 case T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE:
2592 pDevice->LedCtrl = LED_CTRL_SHARED_TRAFFIC_LINK;
2593 if ((pDevice->ChipRevId != T3_CHIP_ID_5750_A0) &&
2594 (pDevice->ChipRevId != T3_CHIP_ID_5750_A1))
2596 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2597 LED_CTRL_PHY_MODE_2;
2601 case T3_SHASTA_EXT_LED_MAC_MODE:
2602 pDevice->LedCtrl = LED_CTRL_SHASTA_MAC_MODE;
2605 case T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE:
2606 pDevice->LedCtrl = LED_CTRL_WIRELESS_COMBO;
2607 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
2609 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2610 LED_CTRL_PHY_MODE_2;
2616 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2617 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)) &&
2618 (pDevice->SubsystemVendorId == T3_SVID_DELL))
2620 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2623 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2624 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2625 (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId)) )
2627 /* Enable EEPROM write protection. */
2628 if(Value32 & T3_NIC_EEPROM_WP)
2630 pDevice->Flags |= EEPROM_WP_FLAG;
2633 pDevice->AsfFlags = 0;
2635 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
2637 pDevice->AsfFlags |= ASF_ENABLED;
2638 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2640 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2644 if (Value32 & T3_NIC_FIBER_WOL_CAPABLE)
2646 pDevice->Flags |= FIBER_WOL_CAPABLE_FLAG;
2648 if (Value32 & T3_NIC_WOL_LIMIT_10)
2650 pDevice->Flags |= WOL_LIMIT_10MBPS_FLAG;
2653 /* Get the PHY Id. */
2654 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
2657 EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
2658 PHY_ID1_OUI_MASK) << 10;
2660 Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
2662 EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
2663 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
2668 if (!EePhyTypeSerdes && !(pDevice->AsfFlags & ASF_ENABLED))
2670 /* reset PHY if boot code couldn't read the PHY ID */
2671 LM_ResetPhy(pDevice);
2675 Ver = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_VER);
2676 Ver >>= T3_NIC_DATA_VER_SHIFT;
2679 if((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2680 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2681 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703) &&
2682 (Ver > 0) && (Ver < 0x100)){
2684 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2686 if (Value32 & T3_NIC_CFG_CAPACITIVE_COUPLING)
2688 pDevice->PhyFlags |= PHY_CAPACITIVE_COUPLING;
2691 if (Value32 & T3_NIC_CFG_PRESERVE_PREEMPHASIS)
2693 pDevice->TbiFlags |= TBI_DO_PREEMPHASIS;
2704 /* Set the PHY address. */
2705 pDevice->PhyAddr = PHY_DEVICE_ID;
2707 /* Disable auto polling. */
2708 pDevice->MiMode = 0xc0000;
2709 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
2710 REG_RD_BACK(pDevice, MacCtrl.MiMode);
2713 if (pDevice->AsfFlags & ASF_ENABLED)
2715 /* Reading PHY registers will contend with ASF */
2720 /* Get the PHY id. */
2721 LM_GetPhyId(pDevice);
2724 /* Set the EnableTbi flag to false if we have a copper PHY. */
2725 switch(pDevice->PhyId & PHY_ID_MASK)
2727 case PHY_BCM5400_PHY_ID:
2728 case PHY_BCM5401_PHY_ID:
2729 case PHY_BCM5411_PHY_ID:
2730 case PHY_BCM5461_PHY_ID:
2731 case PHY_BCM5701_PHY_ID:
2732 case PHY_BCM5703_PHY_ID:
2733 case PHY_BCM5704_PHY_ID:
2734 case PHY_BCM5705_PHY_ID:
2735 case PHY_BCM5750_PHY_ID:
2737 case PHY_BCM5714_PHY_ID:
2738 case PHY_BCM5780_PHY_ID:
2739 if(EePhyTypeSerdes == TRUE)
2741 pDevice->PhyFlags |= PHY_IS_FIBER;
2744 case PHY_BCM5752_PHY_ID:
2747 case PHY_BCM8002_PHY_ID:
2748 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
2755 pDevice->PhyId = EePhyId;
2757 if (EePhyTypeSerdes && ((pDevice->PhyId == PHY_BCM5780_PHY_ID)) )
2759 pDevice->PhyFlags |= PHY_IS_FIBER;
2761 else if (EePhyTypeSerdes)
2763 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
2766 else if ((pAdapterInfo = LM_GetAdapterInfoBySsid(
2767 pDevice->SubsystemVendorId,
2768 pDevice->SubsystemId)))
2770 pDevice->PhyId = pAdapterInfo->PhyId;
2771 if (pAdapterInfo->Serdes)
2773 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
2778 if (UNKNOWN_PHY_ID(pDevice->PhyId))
2780 LM_ResetPhy(pDevice);
2781 LM_GetPhyId(pDevice);
2787 if(UNKNOWN_PHY_ID(pDevice->PhyId) &&
2788 !(pDevice->TbiFlags & ENABLE_TBI_FLAG))
2790 if (pDevice->Flags & ROBO_SWITCH_FLAG) {
2791 B57_ERR(("PHY ID unknown, assume it is a copper PHY.\n"));
2793 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
2794 B57_ERR(("PHY ID unknown, assume it is SerDes\n"));
2798 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
2800 if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
2802 pDevice->SavedCacheLineReg &= 0xffff00ff;
2803 pDevice->SavedCacheLineReg |= 0x4000;
2807 pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
2810 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
2811 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM | LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
2812 LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
2814 if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
2816 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
2817 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
2820 #ifdef INCLUDE_TCP_SEG_SUPPORT
2821 pDevice->TaskOffloadCap |= LM_TASK_OFFLOAD_TCP_SEGMENTATION;
2823 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
2824 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
2825 (pDevice->ChipRevId == T3_CHIP_ID_5705_A0))
2827 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
2832 if (pDevice->AsfFlags & ASF_ENABLED)
2834 if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2836 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
2841 /* Change driver parameters. */
2842 Status = MM_GetConfig(pDevice);
2843 if(Status != LM_STATUS_SUCCESS)
2848 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
2850 pDevice->Flags &= ~NIC_SEND_BD_FLAG;
2853 /* Save the current phy link status. */
2854 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
2855 !(pDevice->AsfFlags & ASF_ENABLED))
2857 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
2858 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
2860 /* If we don't have link reset the PHY. */
2861 if(!(Value32 & PHY_STATUS_LINK_PASS) ||
2862 (pDevice->PhyFlags & PHY_RESET_ON_INIT))
2865 LM_ResetPhy(pDevice);
2867 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
2869 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
2870 PHY_AN_AD_ALL_SPEEDS;
2871 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
2872 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
2874 if(!(pDevice->PhyFlags & PHY_NO_GIGABIT))
2875 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS ;
2879 #ifdef INCLUDE_5701_AX_FIX
2880 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
2881 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
2883 Value32 |= BCM540X_CONFIG_AS_MASTER |
2884 BCM540X_ENABLE_CONFIG_AS_MASTER;
2887 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
2889 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
2890 PHY_CTRL_RESTART_AUTO_NEG);
2894 LM_SetEthWireSpeed(pDevice);
2896 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &pDevice->advertising);
2897 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG,
2898 &pDevice->advertising1000);
2901 /* Currently 5401 phy only */
2902 LM_PhyTapPowerMgmt(pDevice);
2904 #ifdef INCLUDE_TBI_SUPPORT
2905 if(pDevice->TbiFlags & ENABLE_TBI_FLAG)
2907 if (!(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG))
2909 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
2911 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
2912 if (pDevice->TbiFlags & TBI_PURE_POLLING_FLAG)
2914 pDevice->IgnoreTbiLinkChange = TRUE;
2919 pDevice->TbiFlags = 0;
2922 #endif /* INCLUDE_TBI_SUPPORT */
2924 /* UseTaggedStatus is only valid for 5701 and later. */
2925 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
2926 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
2927 ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
2928 (pDevice->BondId == GRC_MISC_BD_ID_5788M))))
2930 pDevice->Flags &= ~USE_TAGGED_STATUS_FLAG;
2931 pDevice->CoalesceMode = 0;
2935 pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
2936 HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
2939 /* Set the status block size. */
2940 if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
2941 T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
2943 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
2946 /* Check the DURING_INT coalescing ticks parameters. */
2947 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
2949 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
2951 pDevice->RxCoalescingTicksDuringInt =
2952 DEFAULT_RX_COALESCING_TICKS_DURING_INT;
2955 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
2957 pDevice->TxCoalescingTicksDuringInt =
2958 DEFAULT_TX_COALESCING_TICKS_DURING_INT;
2961 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
2963 pDevice->RxMaxCoalescedFramesDuringInt =
2964 DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
2967 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
2969 pDevice->TxMaxCoalescedFramesDuringInt =
2970 DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
2975 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
2977 pDevice->RxCoalescingTicksDuringInt = 0;
2980 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
2982 pDevice->TxCoalescingTicksDuringInt = 0;
2985 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
2987 pDevice->RxMaxCoalescedFramesDuringInt = 0;
2990 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
2992 pDevice->TxMaxCoalescedFramesDuringInt = 0;
2996 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2997 if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
2999 pDevice->RxJumboDescCnt = 0;
3000 if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3002 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3005 else if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
3007 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3008 pDevice->RxJumboDescCnt = 0;
3012 pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
3013 COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
3015 if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
3017 pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
3018 pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
3020 pDevice->TxMtu = pDevice->RxMtu;
3023 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3024 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3026 pDevice->RxPacketDescCnt =
3027 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3028 pDevice->RxJumboDescCnt +
3029 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3030 pDevice->RxStdDescCnt;
3032 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3034 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3037 if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
3039 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
3042 /* Configure the proper ways to get link change interrupt. */
3043 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
3045 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3047 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3051 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3054 else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
3056 /* Auto-polling does not work on 5700_AX and 5700_BX. */
3057 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3059 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3063 /* Determine the method to get link change status. */
3064 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
3066 /* The link status bit in the status block does not work on 5700_AX */
3067 /* and 5700_BX chips. */
3068 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3070 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3074 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
3078 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
3079 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3081 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3086 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3089 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3090 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
3092 /* bug? 5701 in LINK10 mode does not seem to work when */
3093 /* PhyIntMode is LINK_READY. */
3094 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
3095 #ifdef INCLUDE_TBI_SUPPORT
3096 !(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3098 pDevice->LedCtrl == LED_CTRL_PHY_MODE_2)
3100 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3101 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3103 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
3105 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3110 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3111 pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3112 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
3113 pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
3115 pDevice->WolSpeed = WOL_SPEED_10MB;
3119 if (pDevice->Flags & WOL_LIMIT_10MBPS_FLAG)
3121 pDevice->WolSpeed = WOL_SPEED_10MB;
3125 pDevice->WolSpeed = WOL_SPEED_100MB;
3130 pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
3132 pDevice->DmaReadFifoSize = 0;
3133 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3134 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0)) ||
3135 T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) )
3137 #ifdef INCLUDE_TCP_SEG_SUPPORT
3138 if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) &&
3139 ((pDevice->ChipRevId == T3_CHIP_ID_5705_A1) ||
3140 (pDevice->ChipRevId == T3_CHIP_ID_5705_A2)))
3142 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_SIZE_128;
3147 if (!(pDevice->PciState & T3_PCI_STATE_HIGH_BUS_SPEED) &&
3148 !(pDevice->Flags & BCM5788_FLAG) &&
3149 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3151 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3152 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A1)
3154 pDevice->Flags |= RX_BD_LIMIT_64_FLAG;
3156 pDevice->Flags |= DMA_WR_MODE_RX_ACCELERATE_FLAG;
3158 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3160 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3165 pDevice->Flags &= ~T3_HAS_TWO_CPUS;
3166 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3167 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
3168 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
3169 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3171 pDevice->Flags |= T3_HAS_TWO_CPUS;
3174 return LM_STATUS_SUCCESS;
3175 } /* LM_GetAdapterInfo */
3177 STATIC PLM_ADAPTER_INFO
3178 LM_GetAdapterInfoBySsid(
3182 static LM_ADAPTER_INFO AdapterArr[] =
3184 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
3185 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
3186 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
3187 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
3188 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
3189 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
3190 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
3191 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
3192 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
3193 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5703_PHY_ID, 0},
3194 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5703_PHY_ID, 0},
3196 { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
3197 { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
3198 { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
3199 { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
3200 { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
3202 { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
3203 { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
3204 { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3205 { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3207 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
3208 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
3209 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
3210 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
3211 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
3213 { 0x1014, 0x0281, 0, 1 },
3217 for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
3219 if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
3221 return &AdapterArr[j];
3230 /******************************************************************************/
3232 /* This routine sets up receive/transmit buffer descriptions queues. */
3235 /* LM_STATUS_SUCCESS */
3236 /******************************************************************************/
3238 LM_InitializeAdapter(
3239 PLM_DEVICE_BLOCK pDevice)
3241 LM_PHYSICAL_ADDRESS MemPhy;
3246 LM_UINT32 Value32, j;
3247 LM_UINT32 DmaWrCmd, DmaRdCmd, DmaWrBdry, DmaRdBdry;
3249 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3251 while (((Value32 & 0x3ff) != (pDevice->PciCommandStatusWords & 0x3ff)) &&
3254 /* On PCIE devices, there are some rare cases where the device */
3255 /* is in the process of link-training at this point */
3257 MM_WriteConfig32(pDevice, PCI_COMMAND_REG, pDevice->PciCommandStatusWords);
3258 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3261 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
3262 /* Set power state to D0. */
3263 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
3265 /* Intialize the queues. */
3266 QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
3267 MAX_RX_PACKET_DESC_COUNT);
3268 QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
3269 MAX_RX_PACKET_DESC_COUNT);
3271 QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
3272 QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
3274 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
3276 pDevice->RcvRetRcbEntryCount = 512;
3277 pDevice->RcvRetRcbEntryCountMask = 511;
3281 pDevice->RcvRetRcbEntryCount = T3_RCV_RETURN_RCB_ENTRY_COUNT;
3282 pDevice->RcvRetRcbEntryCountMask = T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
3285 /* Allocate shared memory for: status block, the buffers for receive */
3286 /* rings -- standard, mini, jumbo, and return rings. */
3287 Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
3288 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3289 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3290 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3291 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3292 (pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3294 /* Memory for host based Send BD. */
3295 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3297 Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3300 /* Allocate the memory block. */
3301 Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
3302 if(Status != LM_STATUS_SUCCESS)
3307 DmaWrCmd = DMA_CTRL_WRITE_CMD;
3308 DmaRdCmd = DMA_CTRL_READ_CMD;
3309 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_DISABLE;
3310 DmaRdBdry = DMA_CTRL_READ_BOUNDARY_DISABLE;
3311 #ifdef BCM_DISCONNECT_AT_CACHELINE
3312 /* This code is intended for PPC64 and other similar architectures */
3313 /* Only the following chips support this */
3314 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3315 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3316 (pDevice->Flags & PCI_EXPRESS_FLAG))
3318 switch(pDevice->CacheLineSize * 4)
3324 if (!(pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3325 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3328 /* use 384 which is a multiple of 16,32,64,128 */
3329 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_384_PCIX;
3332 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3335 /* use 128 which is a multiple of 16,32,64,128 */
3336 DmaWrCmd = DMA_CTRL_WRITE_BOUNDARY_128_PCIE;
3341 /* use 256 which is a multiple of 16,32,64,128,256 */
3342 if ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3343 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3346 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256;
3348 else if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
3351 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256_PCIX;
3357 pDevice->DmaReadWriteCtrl = DmaWrCmd | DmaRdCmd | DmaWrBdry | DmaRdBdry;
3358 /* Program DMA Read/Write */
3359 if (pDevice->Flags & PCI_EXPRESS_FLAG)
3362 /* !=0 is 256 max or greater payload size so set water mark accordingly*/
3363 Value32 = (REG_RD(pDevice, PciCfg.DeviceCtrl) & MAX_PAYLOAD_SIZE_MASK);
3366 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_256;
3369 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_128;
3373 else if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
3375 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3377 pDevice->DmaReadWriteCtrl |= 0x003f0000;
3381 pDevice->DmaReadWriteCtrl |= 0x003f000f;
3386 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3388 pDevice->DmaReadWriteCtrl |= 0x009f0000;
3391 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3393 pDevice->DmaReadWriteCtrl |= 0x009C0000;
3396 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
3397 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 )
3399 Value32 = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
3400 if ((Value32 == 0x6) || (Value32 == 0x7))
3402 pDevice->Flags |= ONE_DMA_AT_ONCE_FLAG;
3405 else if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
3407 pDevice->DmaReadWriteCtrl &= ~DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3408 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
3409 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | DMA_CTRL_WRITE_ONE_DMA_AT_ONCE);
3411 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | BIT_15);
3412 /* bit 15 is the current CQ 13140 Fix */
3416 pDevice->DmaReadWriteCtrl |= 0x001b000f;
3419 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
3420 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
3422 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
3425 if (pDevice->Flags & ONE_DMA_AT_ONCE_FLAG)
3427 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3430 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
3432 LM_SwitchClocks(pDevice);
3434 if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
3436 return LM_STATUS_FAILURE;
3440 pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
3441 pDevice->StatusBlkPhy = MemPhy;
3442 pMemVirt += T3_STATUS_BLOCK_SIZE;
3443 LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
3445 /* Statistics block. */
3446 pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
3447 pDevice->StatsBlkPhy = MemPhy;
3448 pMemVirt += sizeof(T3_STATS_BLOCK);
3449 LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
3451 /* Receive standard BD buffer. */
3452 pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
3453 pDevice->RxStdBdPhy = MemPhy;
3455 pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3456 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3457 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3459 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3460 /* Receive jumbo BD buffer. */
3461 pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
3462 pDevice->RxJumboBdPhy = MemPhy;
3464 pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3465 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3466 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3467 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3469 /* Receive return BD buffer. */
3470 pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
3471 pDevice->RcvRetBdPhy = MemPhy;
3473 pMemVirt += pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD);
3474 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3475 pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3477 /* Set up Send BD. */
3478 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3480 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
3481 pDevice->SendBdPhy = MemPhy;
3483 pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3484 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3485 sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
3487 #ifdef BCM_NIC_SEND_BD
3490 pDevice->pSendBdVirt = (PT3_SND_BD)
3491 pDevice->pMemView->uIntMem.First32k.BufferDesc;
3492 pDevice->SendBdPhy.High = 0;
3493 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
3497 /* Allocate memory for packet descriptors. */
3498 Size = (pDevice->RxPacketDescCnt +
3499 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
3500 Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
3501 if(Status != LM_STATUS_SUCCESS)
3505 pDevice->pPacketDescBase = (PLM_VOID) pPacket;
3507 /* Create transmit packet descriptors from the memory block and add them */
3508 /* to the TxPacketFreeQ for each send ring. */
3509 for(j = 0; j < pDevice->TxPacketDescCnt; j++)
3514 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
3515 QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
3517 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3518 /* is the total size of the packet descriptor including the */
3519 /* os-specific extensions in the UM_PACKET structure. */
3520 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3523 /* Create receive packet descriptors from the memory block and add them */
3524 /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
3525 for(j = 0; j < pDevice->RxStdDescCnt; j++)
3527 /* Receive producer ring. */
3528 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
3530 /* Receive buffer size. */
3531 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
3532 (pDevice->RxJumboBufferSize) )
3534 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3536 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
3539 /* Add the descriptor to RxPacketFreeQ. */
3540 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3542 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3543 /* is the total size of the packet descriptor including the */
3544 /* os-specific extensions in the UM_PACKET structure. */
3545 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3549 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3550 /* Create the Jumbo packet descriptors. */
3551 for(j = 0; j < pDevice->RxJumboDescCnt; j++)
3553 /* Receive producer ring. */
3554 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
3556 /* Receive buffer size. */
3557 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3559 /* Add the descriptor to RxPacketFreeQ. */
3560 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3562 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3563 /* is the total size of the packet descriptor including the */
3564 /* os-specific extensions in the UM_PACKET structure. */
3565 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3567 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3569 /* Initialize the rest of the packet descriptors. */
3570 Status = MM_InitializeUmPackets(pDevice);
3571 if(Status != LM_STATUS_SUCCESS)
3576 /* Default receive mask. */
3577 pDevice->ReceiveMask &= LM_KEEP_VLAN_TAG;
3578 pDevice->ReceiveMask |= LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3581 /* Make sure we are in the first 32k memory window or NicSendBd. */
3582 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
3584 /* Initialize the hardware. */
3585 Status = LM_ResetAdapter(pDevice);
3586 if(Status != LM_STATUS_SUCCESS)
3591 /* We are done with initialization. */
3592 pDevice->InitDone = TRUE;
3594 return LM_STATUS_SUCCESS;
3595 } /* LM_InitializeAdapter */
3599 LM_DisableChip(PLM_DEVICE_BLOCK pDevice)
3603 pDevice->RxMode &= ~RX_MODE_ENABLE;
3604 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
3605 if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
3609 data = REG_RD(pDevice, RcvBdIn.Mode);
3610 data &= ~RCV_BD_IN_MODE_ENABLE;
3611 REG_WR(pDevice, RcvBdIn.Mode,data);
3612 if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
3616 data = REG_RD(pDevice, RcvListPlmt.Mode);
3617 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
3618 REG_WR(pDevice, RcvListPlmt.Mode,data);
3619 if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
3623 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3625 data = REG_RD(pDevice, RcvListSel.Mode);
3626 data &= ~RCV_LIST_SEL_MODE_ENABLE;
3627 REG_WR(pDevice, RcvListSel.Mode,data);
3628 if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
3633 data = REG_RD(pDevice, RcvDataBdIn.Mode);
3634 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
3635 REG_WR(pDevice, RcvDataBdIn.Mode,data);
3636 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
3640 data = REG_RD(pDevice, RcvDataComp.Mode);
3641 data &= ~RCV_DATA_COMP_MODE_ENABLE;
3642 REG_WR(pDevice, RcvDataComp.Mode,data);
3643 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
3647 data = REG_RD(pDevice, RcvBdComp.Mode);
3648 data &= ~RCV_BD_COMP_MODE_ENABLE;
3649 REG_WR(pDevice, RcvBdComp.Mode,data);
3650 if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
3654 data = REG_RD(pDevice, SndBdSel.Mode);
3655 data &= ~SND_BD_SEL_MODE_ENABLE;
3656 REG_WR(pDevice, SndBdSel.Mode, data);
3657 if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
3661 data = REG_RD(pDevice, SndBdIn.Mode);
3662 data &= ~SND_BD_IN_MODE_ENABLE;
3663 REG_WR(pDevice, SndBdIn.Mode, data);
3664 if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
3668 data = REG_RD(pDevice, SndDataIn.Mode);
3669 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
3670 REG_WR(pDevice, SndDataIn.Mode,data);
3671 if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
3675 data = REG_RD(pDevice, DmaRead.Mode);
3676 data &= ~DMA_READ_MODE_ENABLE;
3677 REG_WR(pDevice, DmaRead.Mode, data);
3678 if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
3682 data = REG_RD(pDevice, SndDataComp.Mode);
3683 data &= ~SND_DATA_COMP_MODE_ENABLE;
3684 REG_WR(pDevice, SndDataComp.Mode, data);
3685 if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
3690 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3692 data = REG_RD(pDevice,DmaComp.Mode);
3693 data &= ~DMA_COMP_MODE_ENABLE;
3694 REG_WR(pDevice, DmaComp.Mode, data);
3695 if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
3700 data = REG_RD(pDevice, SndBdComp.Mode);
3701 data &= ~SND_BD_COMP_MODE_ENABLE;
3702 REG_WR(pDevice, SndBdComp.Mode, data);
3703 if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
3708 pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
3709 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
3710 pDevice->TxMode &= ~TX_MODE_ENABLE;
3711 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
3712 if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
3716 data = REG_RD(pDevice, HostCoalesce.Mode);
3717 data &= ~HOST_COALESCE_ENABLE;
3718 REG_WR(pDevice, HostCoalesce.Mode, data);
3719 if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
3723 data = REG_RD(pDevice, DmaWrite.Mode);
3724 data &= ~DMA_WRITE_MODE_ENABLE;
3725 REG_WR(pDevice, DmaWrite.Mode,data);
3726 if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
3731 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3733 data = REG_RD(pDevice, MbufClusterFree.Mode);
3734 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
3735 REG_WR(pDevice, MbufClusterFree.Mode,data);
3736 if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
3741 /* Reset all FTQs */
3742 REG_WR(pDevice, Ftq.Reset, 0xffffffff);
3743 REG_WR(pDevice, Ftq.Reset, 0x0);
3745 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3747 data = REG_RD(pDevice, BufMgr.Mode);
3748 data &= ~BUFMGR_MODE_ENABLE;
3749 REG_WR(pDevice, BufMgr.Mode,data);
3750 if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
3754 data = REG_RD(pDevice, MemArbiter.Mode);
3755 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
3756 REG_WR(pDevice, MemArbiter.Mode, data);
3757 if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
3762 return LM_STATUS_SUCCESS;
3766 LM_DisableFW(PLM_DEVICE_BLOCK pDevice)
3772 if (pDevice->AsfFlags & ASF_ENABLED)
3774 MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, T3_CMD_NICDRV_PAUSE_FW);
3775 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
3776 REG_WR(pDevice, Grc.RxCpuEvent, Value32 | BIT_14);
3777 for (j = 0; j < 100; j++)
3779 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
3780 if (!(Value32 & BIT_14))
3788 return LM_STATUS_SUCCESS;
3791 /******************************************************************************/
3793 /* This function reinitializes the adapter. */
3796 /* LM_STATUS_SUCCESS */
3797 /******************************************************************************/
3800 PLM_DEVICE_BLOCK pDevice)
3804 int reset_count = 0;
3806 /* Disable interrupt. */
3807 LM_DisableInterrupt(pDevice);
3810 LM_DisableFW(pDevice);
3812 /* May get a spurious interrupt */
3813 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
3815 LM_WritePreResetSignatures(pDevice, LM_INIT_RESET);
3816 /* Disable transmit and receive DMA engines. Abort all pending requests. */
3817 if(pDevice->InitDone)
3822 pDevice->ShuttingDown = FALSE;
3824 LM_ResetChip(pDevice);
3826 LM_WriteLegacySignatures(pDevice, LM_INIT_RESET);
3828 /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
3829 /* in other chip revisions except 5750 */
3830 if ((pDevice->Flags & DELAY_PCI_GRANT_FLAG) &&
3831 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3833 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | BIT_31);
3836 if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
3838 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
3840 Value32 = REG_RD(pDevice, PciCfg.PciState);
3841 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
3842 REG_WR(pDevice, PciCfg.PciState, Value32);
3845 if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_BX)
3847 /* New bits defined in register 0x64 to enable some h/w fixes */
3848 /* These new bits are 'write-only' */
3849 Value32 = REG_RD(pDevice, PciCfg.MsiData);
3850 REG_WR(pDevice, PciCfg.MsiData, Value32 | BIT_26 | BIT_28 | BIT_29);
3853 /* Enable TaggedStatus mode. */
3854 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
3856 pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
3859 /* Restore PCI configuration registers. */
3860 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
3861 pDevice->SavedCacheLineReg);
3862 MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
3863 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
3865 /* Initialize the statistis Block */
3866 pDevice->pStatusBlkVirt->Status = 0;
3867 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
3868 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
3869 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
3871 for(j = 0; j < 16; j++)
3873 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
3874 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
3877 for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
3879 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
3880 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
3881 pDevice->pRxStdBdVirt[k].Flags = RCV_BD_FLAG_END;
3882 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
3883 (pDevice->RxJumboBufferSize) )
3884 pDevice->pRxStdBdVirt[k].Len = pDevice->RxJumboBufferSize;
3886 pDevice->pRxStdBdVirt[k].Len = MAX_STD_RCV_BUFFER_SIZE;
3889 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3890 /* Receive jumbo BD buffer. */
3891 for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
3893 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
3894 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
3895 pDevice->pRxJumboBdVirt[k].Flags = RCV_BD_FLAG_END |
3896 RCV_BD_FLAG_JUMBO_RING;
3897 pDevice->pRxJumboBdVirt[k].Len = (LM_UINT16) pDevice->RxJumboBufferSize;
3901 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
3903 /* GRC mode control register. */
3905 #ifdef BIG_ENDIAN_HOST
3906 GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
3907 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
3908 GRC_MODE_BYTE_SWAP_DATA |
3909 GRC_MODE_WORD_SWAP_DATA |
3911 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
3912 GRC_MODE_BYTE_SWAP_DATA |
3913 GRC_MODE_WORD_SWAP_DATA |
3915 GRC_MODE_INT_ON_MAC_ATTN |
3916 GRC_MODE_HOST_STACK_UP;
3918 /* Configure send BD mode. */
3919 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3921 Value32 |= GRC_MODE_HOST_SEND_BDS;
3923 #ifdef BCM_NIC_SEND_BD
3926 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
3930 /* Configure pseudo checksum mode. */
3931 if (pDevice->Flags & NO_TX_PSEUDO_HDR_CSUM_FLAG)
3933 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
3936 if (pDevice->Flags & NO_RX_PSEUDO_HDR_CSUM_FLAG)
3938 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
3941 pDevice->GrcMode = Value32;
3942 REG_WR(pDevice, Grc.Mode, Value32);
3944 /* Setup the timer prescalar register. */
3945 Value32 = REG_RD(pDevice, Grc.MiscCfg) & ~0xff;
3946 /* Clock is always 66Mhz. */
3947 REG_WR(pDevice, Grc.MiscCfg, Value32 | (65 << 1));
3949 /* Set up the MBUF pool base address and size. */
3950 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
3952 #ifdef INCLUDE_TCP_SEG_SUPPORT
3953 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
3955 Value32 = LM_GetStkOffLdFirmwareSize(pDevice);
3956 Value32 = (Value32 + 0x7f) & ~0x7f;
3957 pDevice->MbufBase = T3_NIC_BCM5705_MBUF_POOL_ADDR + Value32;
3958 pDevice->MbufSize = T3_NIC_BCM5705_MBUF_POOL_SIZE - Value32 - 0xa00;
3959 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
3960 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
3964 else if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
3966 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
3967 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
3969 /* Set up the DMA descriptor pool base address and size. */
3970 REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
3971 REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
3975 /* Configure MBUF and Threshold watermarks */
3976 /* Configure the DMA read MBUF low water mark. */
3977 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
3979 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3981 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
3982 T3_DEF_DMA_MBUF_LOW_WMARK_5705);
3983 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
3984 T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705);
3985 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
3986 T3_DEF_MBUF_HIGH_WMARK_5705);
3990 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
3991 T3_DEF_DMA_MBUF_LOW_WMARK);
3992 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
3993 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
3994 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
3995 T3_DEF_MBUF_HIGH_WMARK);
3997 }else if( T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
3999 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,0);
4000 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,0x4b);
4001 REG_WR(pDevice, BufMgr.MbufHighWaterMark,0x96);
4005 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4006 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
4007 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4008 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
4009 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4010 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
4013 REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
4014 REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
4016 /* Enable buffer manager. */
4017 REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
4019 for(j = 0 ;j < 2000; j++)
4021 if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
4028 return LM_STATUS_FAILURE;
4031 /* GRC reset will reset FTQ */
4033 /* Receive BD Ring replenish threshold. */
4034 REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
4036 /* Initialize the Standard Receive RCB. */
4037 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
4038 pDevice->RxStdBdPhy.High);
4039 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
4040 pDevice->RxStdBdPhy.Low);
4041 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
4042 (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
4044 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4046 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4051 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4052 MAX_STD_RCV_BUFFER_SIZE << 16);
4054 /* Initialize the Jumbo Receive RCB. */
4055 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
4056 T3_RCB_FLAG_RING_DISABLED);
4057 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4058 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
4059 pDevice->RxJumboBdPhy.High);
4060 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
4061 pDevice->RxJumboBdPhy.Low);
4062 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
4063 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
4064 (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
4066 REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
4068 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
4070 /* Initialize the Mini Receive RCB. */
4071 REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
4072 T3_RCB_FLAG_RING_DISABLED);
4074 /* Disable all the unused rings. */
4075 for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
4076 MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags,
4077 T3_RCB_FLAG_RING_DISABLED);
4082 /* Initialize the indices. */
4083 pDevice->SendProdIdx = 0;
4084 pDevice->SendConIdx = 0;
4086 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
4087 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
4088 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
4089 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
4091 /* Set up host or NIC based send RCB. */
4092 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4094 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
4095 pDevice->SendBdPhy.High);
4096 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
4097 pDevice->SendBdPhy.Low);
4099 /* Setup the RCB. */
4100 MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
4101 T3_SEND_RCB_ENTRY_COUNT << 16);
4103 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4105 /* Set up the NIC ring address in the RCB. */
4106 MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
4108 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4110 pDevice->pSendBdVirt[k].HostAddr.High = 0;
4111 pDevice->pSendBdVirt[k].HostAddr.Low = 0;
4114 #ifdef BCM_NIC_SEND_BD
4117 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
4118 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
4119 MEM_WR(pDevice, SendRcb[0].NicRingAddr,
4120 pDevice->SendBdPhy.Low);
4122 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4124 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.High), 0);
4125 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.Low), 0);
4126 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].u1.Len_Flags), 0);
4127 pDevice->ShadowSendBd[k].HostAddr.High = 0;
4128 pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
4132 MM_ATOMIC_SET(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
4134 /* Configure the receive return rings. */
4135 for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
4137 MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
4140 pDevice->RcvRetConIdx = 0;
4142 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
4143 pDevice->RcvRetBdPhy.High);
4144 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
4145 pDevice->RcvRetBdPhy.Low);
4147 MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
4149 /* Setup the RCB. */
4150 MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
4151 pDevice->RcvRetRcbEntryCount << 16);
4153 /* Reinitialize RX ring producer index */
4154 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
4155 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
4156 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
4157 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
4158 MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
4159 MB_REG_RD(pDevice, Mailbox.RcvMiniProdIdx.Low);
4161 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4162 pDevice->RxJumboProdIdx = 0;
4163 pDevice->RxJumboQueuedCnt = 0;
4166 /* Reinitialize our copy of the indices. */
4167 pDevice->RxStdProdIdx = 0;
4168 pDevice->RxStdQueuedCnt = 0;
4170 #if T3_JUMBO_RCV_ENTRY_COUNT
4171 pDevice->RxJumboProdIdx = 0;
4172 #endif /* T3_JUMBO_RCV_ENTRY_COUNT */
4174 /* Configure the MAC address. */
4175 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
4177 /* Initialize the transmit random backoff seed. */
4178 Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
4179 pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
4180 pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
4181 MAC_TX_BACKOFF_SEED_MASK;
4182 REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
4184 /* Receive MTU. Frames larger than the MTU is marked as oversized. */
4185 REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
4187 /* Configure Time slot/IPG per 802.3 */
4188 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
4191 * Configure Receive Rules so that packets don't match
4192 * Programmble rule will be queued to Return Ring 1
4194 REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
4197 * Configure to have 16 Classes of Services (COS) and one
4198 * queue per class. Bad frames are queued to RRR#1.
4199 * And frames don't match rules are also queued to COS#1.
4201 REG_WR(pDevice, RcvListPlmt.Config, 0x181);
4203 /* Enable Receive Placement Statistics */
4204 if ((pDevice->DmaReadFifoSize == DMA_READ_MODE_FIFO_LONG_BURST) &&
4205 (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION))
4207 Value32 = REG_RD(pDevice, RcvListPlmt.StatsEnableMask);
4208 Value32 &= ~T3_DISABLE_LONG_BURST_READ_DYN_FIX;
4209 REG_WR(pDevice, RcvListPlmt.StatsEnableMask, Value32);
4213 REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
4215 REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
4217 /* Enable Send Data Initator Statistics */
4218 REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
4219 REG_WR(pDevice, SndDataIn.StatsCtrl,
4220 T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
4221 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
4223 /* Disable the host coalescing state machine before configuring it's */
4225 REG_WR(pDevice, HostCoalesce.Mode, 0);
4226 for(j = 0; j < 2000; j++)
4228 Value32 = REG_RD(pDevice, HostCoalesce.Mode);
4229 if(!(Value32 & HOST_COALESCE_ENABLE))
4236 /* Host coalescing configurations. */
4237 REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
4238 REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
4239 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
4240 pDevice->RxMaxCoalescedFrames);
4241 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
4242 pDevice->TxMaxCoalescedFrames);
4244 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4246 REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
4247 pDevice->RxCoalescingTicksDuringInt);
4248 REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
4249 pDevice->TxCoalescingTicksDuringInt);
4251 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
4252 pDevice->RxMaxCoalescedFramesDuringInt);
4253 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
4254 pDevice->TxMaxCoalescedFramesDuringInt);
4256 /* Initialize the address of the status block. The NIC will DMA */
4257 /* the status block to this memory which resides on the host. */
4258 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
4259 pDevice->StatusBlkPhy.High);
4260 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
4261 pDevice->StatusBlkPhy.Low);
4263 /* Initialize the address of the statistics block. The NIC will DMA */
4264 /* the statistics to this block of memory. */
4265 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4267 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
4268 pDevice->StatsBlkPhy.High);
4269 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
4270 pDevice->StatsBlkPhy.Low);
4272 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
4273 pDevice->StatsCoalescingTicks);
4275 REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
4276 REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
4279 /* Enable Host Coalesing state machine */
4280 REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
4281 pDevice->CoalesceMode);
4283 /* Enable the Receive BD Completion state machine. */
4284 REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
4285 RCV_BD_COMP_MODE_ATTN_ENABLE);
4287 /* Enable the Receive List Placement state machine. */
4288 REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
4290 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4292 /* Enable the Receive List Selector state machine. */
4293 REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
4294 RCV_LIST_SEL_MODE_ATTN_ENABLE);
4297 /* Reset the Rx MAC State Machine.
4299 * The Rx MAC State Machine must be reset when using fiber to prevent the
4300 * first packet being lost. This is needed primarily so that the loopback
4301 * test (which currently only sends one packet) doesn't fail.
4303 * Also note that the Rx MAC State Machine (0x468) should be reset _before_
4304 * writting to the MAC Mode register (0x400). Failures have been seen on
4305 * 5780/5714's using fiber where they stopped receiving packets in a simple
4306 * ping test when the Rx MAC State Machine was reset _after_ the MAC Mode
4310 if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) ||
4311 (pDevice->PhyFlags & PHY_IS_FIBER))
4313 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
4314 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4316 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4317 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4320 /* Clear the statistics block. */
4321 for(j = 0x0300; j < 0x0b00; j = j + 4)
4323 MEM_WR_OFFSET(pDevice, j, 0);
4327 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4329 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
4331 else if(pDevice->PhyFlags & PHY_IS_FIBER)
4333 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
4337 pDevice->MacMode = 0;
4340 /* Enable transmit DMA, clear statistics. */
4341 pDevice->MacMode |= MAC_MODE_ENABLE_TX_STATISTICS |
4342 MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
4343 MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
4344 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
4345 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
4347 /* GRC miscellaneous local control register. */
4348 pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
4349 GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
4351 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
4353 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
4354 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
4356 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
4357 !(pDevice->Flags & EEPROM_WP_FLAG))
4359 /* Make sure we're on Vmain */
4360 /* The other port may cause us to be on Vaux */
4361 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
4362 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2;
4365 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4368 /* Reset RX counters. */
4369 for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
4371 ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
4374 /* Reset TX counters. */
4375 for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
4377 ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
4380 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
4381 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4382 pDevice->LastTag = 0;
4384 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4386 /* Enable the DMA Completion state machine. */
4387 REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
4390 /* Enable the DMA Write state machine. */
4391 Value32 = DMA_WRITE_MODE_ENABLE |
4392 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
4393 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
4394 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
4395 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4396 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4397 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4398 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4399 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
4401 if (pDevice->Flags & DMA_WR_MODE_RX_ACCELERATE_FLAG)
4403 Value32 |= DMA_WRITE_MODE_RECEIVE_ACCELERATE;
4406 if (pDevice->Flags & HOST_COALESCING_BUG_FIX)
4408 Value32 |= (1 << 29);
4411 REG_WR(pDevice, DmaWrite.Mode, Value32);
4413 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4415 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
4417 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4418 Value32 &= ~PCIX_CMD_MAX_BURST_MASK;
4419 Value32 |= PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL;
4420 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4422 else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4424 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4425 Value32 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
4426 Value32 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
4427 PCIX_CMD_MAX_BURST_MASK);
4428 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4430 Value32 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
4431 & PCIX_CMD_MAX_SPLIT_MASK;
4433 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4437 /* Enable the Read DMA state machine. */
4438 Value32 = DMA_READ_MODE_ENABLE |
4439 DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
4440 DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
4441 DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
4442 DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4443 DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4444 DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4445 DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4446 DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
4448 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4450 Value32 |= DMA_READ_MODE_MULTI_SPLIT_ENABLE;
4453 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4455 Value32 |= pDevice->DmaReadFifoSize;
4457 #ifdef INCLUDE_TCP_SEG_SUPPORT
4458 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4465 REG_WR(pDevice, DmaRead.Mode, Value32);
4467 /* Enable the Receive Data Completion state machine. */
4468 REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
4469 RCV_DATA_COMP_MODE_ATTN_ENABLE);
4471 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4473 /* Enable the Mbuf Cluster Free state machine. */
4474 REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
4477 /* Enable the Send Data Completion state machine. */
4478 REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
4480 /* Enable the Send BD Completion state machine. */
4481 REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
4482 SND_BD_COMP_MODE_ATTN_ENABLE);
4484 /* Enable the Receive BD Initiator state machine. */
4485 REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
4486 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
4488 /* Enable the Receive Data and Receive BD Initiator state machine. */
4489 REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
4490 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
4492 /* Enable the Send Data Initiator state machine. */
4493 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
4495 #ifdef INCLUDE_TCP_SEG_SUPPORT
4496 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4498 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE | 0x8);
4502 /* Enable the Send BD Initiator state machine. */
4503 REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
4504 SND_BD_IN_MODE_ATTN_ENABLE);
4506 /* Enable the Send BD Selector state machine. */
4507 REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
4508 SND_BD_SEL_MODE_ATTN_ENABLE);
4510 #ifdef INCLUDE_5701_AX_FIX
4511 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
4513 LM_LoadRlsFirmware(pDevice);
4517 /* Queue Rx packet buffers. */
4518 if(pDevice->QueueRxPackets)
4520 LM_QueueRxPackets(pDevice);
4523 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
4525 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4527 while ((Value32 != MAX_STD_RCV_BUFFER_SIZE) && (j < 10))
4530 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4537 if (reset_count > 5)
4538 return LM_STATUS_FAILURE;
4543 /* Enable the transmitter. */
4544 pDevice->TxMode = TX_MODE_ENABLE;
4545 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4547 /* Enable the receiver. */
4548 pDevice->RxMode = (pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) |
4550 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4553 if (pDevice->RestoreOnWakeUp)
4555 pDevice->RestoreOnWakeUp = FALSE;
4556 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
4557 pDevice->RequestedLineSpeed = pDevice->WakeUpRequestedLineSpeed;
4558 pDevice->RequestedDuplexMode = pDevice->WakeUpRequestedDuplexMode;
4562 /* Disable auto polling. */
4563 pDevice->MiMode = 0xc0000;
4564 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
4566 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
4568 /* Activate Link to enable MAC state machine */
4569 REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
4571 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4573 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
4575 REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
4577 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4580 if(!(pDevice->TbiFlags & TBI_DO_PREEMPHASIS))
4582 /* Set SerDes drive transmission level to 1.2V */
4583 Value32 = REG_RD(pDevice, MacCtrl.SerdesCfg) & 0xfffff000;
4584 REG_WR(pDevice, MacCtrl.SerdesCfg, Value32 | 0x880);
4589 REG_WR(pDevice, MacCtrl.LowWaterMarkMaxRxFrame, 2);
4591 if(pDevice->PhyFlags & PHY_IS_FIBER)
4593 Value32 = REG_RD_OFFSET(pDevice, 0x5b0);
4594 REG_WR_OFFSET(pDevice, 0x5b0, Value32 | BIT_10 );
4596 pDevice->GrcLocalCtrl |= BIT_4 ;
4597 pDevice->GrcLocalCtrl &= ~BIT_5 ;
4599 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4600 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
4604 if (!pDevice->InitDone)
4606 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
4607 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
4609 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
4613 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
4614 ( ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5401_PHY_ID)&&
4615 ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) ))
4617 /* 5401/5411 PHY needs a delay of about 1 second after PHY reset */
4618 /* Without the delay, it has problem linking at forced 10 half */
4619 /* So skip the reset... */
4620 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
4621 for(j =0; j<0x5000; j++)
4624 LM_ResetPhy(pDevice);
4627 /* Setup the phy chip. */
4628 LM_SetupPhy(pDevice);
4630 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)){
4631 /* Clear CRC stats */
4632 LM_ReadPhy(pDevice, 0x1e, &Value32);
4633 LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
4634 LM_ReadPhy(pDevice, 0x14, &Value32);
4637 /* Set up the receive mask. */
4638 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
4640 #ifdef INCLUDE_TCP_SEG_SUPPORT
4641 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4643 if (LM_LoadStkOffLdFirmware(pDevice) == LM_STATUS_FAILURE)
4645 return LM_STATUS_FAILURE;
4649 LM_WritePostResetSignatures(pDevice, LM_INIT_RESET);
4651 return LM_STATUS_SUCCESS;
4652 } /* LM_ResetAdapter */
4655 /******************************************************************************/
4657 /* This routine disables the adapter from generating interrupts. */
4660 /* LM_STATUS_SUCCESS */
4661 /******************************************************************************/
4663 LM_DisableInterrupt(
4664 PLM_DEVICE_BLOCK pDevice)
4666 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
4667 MISC_HOST_CTRL_MASK_PCI_INT);
4668 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
4669 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4671 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4674 return LM_STATUS_SUCCESS;
4679 /******************************************************************************/
4681 /* This routine enables the adapter to generate interrupts. */
4684 /* LM_STATUS_SUCCESS */
4685 /******************************************************************************/
4688 PLM_DEVICE_BLOCK pDevice)
4690 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, pDevice->LastTag << 24);
4691 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4693 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4696 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
4697 ~MISC_HOST_CTRL_MASK_PCI_INT);
4699 REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode |
4700 HOST_COALESCE_ENABLE | HOST_COALESCE_NOW);
4702 return LM_STATUS_SUCCESS;
4707 /******************************************************************************/
4709 /* This routine puts a packet on the wire if there is a transmit DMA */
4710 /* descriptor available; otherwise the packet is queued for later */
4711 /* transmission. If the second argue is NULL, this routine will put */
4712 /* the queued packet on the wire if possible. */
4715 /* LM_STATUS_SUCCESS */
4716 /******************************************************************************/
4718 LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
4720 LM_UINT32 FragCount;
4721 PT3_SND_BD pSendBd, pTmpSendBd;
4722 #ifdef BCM_NIC_SEND_BD
4723 PT3_SND_BD pShadowSendBd;
4724 T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
4726 LM_UINT32 StartIdx, Idx;
4730 /* Initalize the send buffer descriptors. */
4731 StartIdx = Idx = pDevice->SendProdIdx;
4733 #ifdef BCM_NIC_SEND_BD
4734 if (pDevice->Flags & NIC_SEND_BD_FLAG)
4736 pTmpSendBd = pSendBd = &NicSendBdArr[0];
4741 pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
4744 /* Next producer index. */
4745 for(FragCount = 0; ; )
4747 LM_UINT32 Value32, Len;
4749 /* Initialize the pointer to the send buffer fragment. */
4750 MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
4752 pSendBd->u2.VlanTag = pPacket->VlanTag;
4754 /* Setup the control flags and send buffer size. */
4755 Value32 = (Len << 16) | pPacket->Flags;
4757 #ifdef INCLUDE_TCP_SEG_SUPPORT
4758 if (Value32 & (SND_BD_FLAG_CPU_PRE_DMA | SND_BD_FLAG_CPU_POST_DMA))
4760 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4762 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
4764 else if (FragCount == 0)
4766 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
4770 pSendBd->u2.s2.Reserved = 0;
4771 Value32 &= 0xffff0fff;
4775 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
4778 if (FragCount >= pPacket->u.Tx.FragCount)
4780 pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
4785 pSendBd->u1.Len_Flags = Value32;
4790 !(pDevice->Flags & NIC_SEND_BD_FLAG))
4792 pSendBd = &pDevice->pSendBdVirt[0];
4795 pDevice->SendRing[Idx] = 0;
4798 if (pDevice->Flags & TX_4G_WORKAROUND_FLAG)
4800 if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
4803 if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
4805 QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
4806 return LM_STATUS_FAILURE;
4813 /* Put the packet descriptor in the ActiveQ. */
4814 pDevice->SendRing[StartIdx] = pPacket;
4816 #ifdef BCM_NIC_SEND_BD
4817 if (pDevice->Flags & NIC_SEND_BD_FLAG)
4819 pSendBd = &pDevice->pSendBdVirt[StartIdx];
4820 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
4822 while (StartIdx != Idx)
4826 if ((Value32 = pTmpSendBd->HostAddr.High) !=
4827 pShadowSendBd->HostAddr.High)
4829 MM_MEMWRITEL(&(pSendBd->HostAddr.High), Value32);
4830 pShadowSendBd->HostAddr.High = Value32;
4833 MM_MEMWRITEL(&(pSendBd->HostAddr.Low), pTmpSendBd->HostAddr.Low);
4835 if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
4836 pShadowSendBd->u1.Len_Flags)
4838 MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), Value32);
4839 pShadowSendBd->u1.Len_Flags = Value32;
4842 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
4844 MM_MEMWRITEL(&(pSendBd->u2.VlanTag), pTmpSendBd->u2.VlanTag);
4847 StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
4850 pSendBd = &pDevice->pSendBdVirt[0];
4851 pShadowSendBd = &pDevice->ShadowSendBd[0];
4861 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
4863 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
4865 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
4867 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4869 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
4880 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
4882 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
4884 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
4886 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4888 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
4896 /* Update the SendBdLeft count. */
4897 MM_ATOMIC_SUB(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
4899 /* Update the producer index. */
4900 pDevice->SendProdIdx = Idx;
4902 return LM_STATUS_SUCCESS;
4906 LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
4910 LM_UINT32 Idx, Base, Len;
4912 Idx = pDevice->SendProdIdx;
4913 for(FragCount = 0; ; )
4915 Len = pSendBd->u1.Len_Flags >> 16;
4916 if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
4917 ((Base + 8 + Len) < Base))
4919 return LM_STATUS_SUCCESS;
4922 if (FragCount >= pPacket->u.Tx.FragCount)
4927 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4929 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
4932 pSendBd = &pDevice->pSendBdVirt[0];
4936 return LM_STATUS_FAILURE;
4939 /******************************************************************************/
4943 /******************************************************************************/
4945 ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize)
4953 for(j = 0; j < BufferSize; j++)
4957 for(k = 0; k < 8; k++)
4971 } /* ComputeCrc32 */
4975 /******************************************************************************/
4977 /* This routine sets the receive control register according to ReceiveMask */
4980 /* LM_STATUS_SUCCESS */
4981 /******************************************************************************/
4983 LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
4985 LM_UINT32 ReceiveMask;
4991 RxMode = pDevice->RxMode;
4993 if(Mask & LM_ACCEPT_UNICAST)
4995 Mask &= ~LM_ACCEPT_UNICAST;
4998 if(Mask & LM_ACCEPT_MULTICAST)
5000 Mask &= ~LM_ACCEPT_MULTICAST;
5003 if(Mask & LM_ACCEPT_ALL_MULTICAST)
5005 Mask &= ~LM_ACCEPT_ALL_MULTICAST;
5008 if(Mask & LM_ACCEPT_BROADCAST)
5010 Mask &= ~LM_ACCEPT_BROADCAST;
5013 RxMode &= ~RX_MODE_KEEP_VLAN_TAG;
5014 if (Mask & LM_KEEP_VLAN_TAG)
5016 RxMode |= RX_MODE_KEEP_VLAN_TAG;
5017 Mask &= ~LM_KEEP_VLAN_TAG;
5020 RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
5021 if(Mask & LM_PROMISCUOUS_MODE)
5023 RxMode |= RX_MODE_PROMISCUOUS_MODE;
5024 Mask &= ~LM_PROMISCUOUS_MODE;
5027 RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
5028 if(Mask & LM_ACCEPT_ERROR_PACKET)
5030 RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
5031 Mask &= ~LM_ACCEPT_ERROR_PACKET;
5034 /* Make sure all the bits are valid before committing changes. */
5037 return LM_STATUS_FAILURE;
5040 /* Commit the new filter. */
5041 pDevice->ReceiveMask = ReceiveMask;
5043 pDevice->RxMode = RxMode;
5045 if (pDevice->PowerLevel != LM_POWER_STATE_D0)
5047 return LM_STATUS_SUCCESS;
5050 REG_WR(pDevice, MacCtrl.RxMode, RxMode);
5052 /* Set up the MC hash table. */
5053 if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
5055 for(k = 0; k < 4; k++)
5057 REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
5060 else if(ReceiveMask & LM_ACCEPT_MULTICAST)
5062 for(k = 0; k < 4; k++)
5064 REG_WR(pDevice, MacCtrl.HashReg[k], pDevice->MulticastHash[k]);
5069 /* Reject all multicast frames. */
5070 for(j = 0; j < 4; j++)
5072 REG_WR(pDevice, MacCtrl.HashReg[j], 0);
5076 /* By default, Tigon3 will accept broadcast frames. We need to setup */
5077 if(ReceiveMask & LM_ACCEPT_BROADCAST)
5079 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5080 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5081 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5082 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5083 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5084 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5085 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5086 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5090 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5091 REJECT_BROADCAST_RULE1_RULE);
5092 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5093 REJECT_BROADCAST_RULE1_VALUE);
5094 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5095 REJECT_BROADCAST_RULE2_RULE);
5096 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5097 REJECT_BROADCAST_RULE2_VALUE);
5100 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5104 else if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5113 if (pDevice->AsfFlags & ASF_ENABLED)
5119 /* disable the rest of the rules. */
5120 for(j = RCV_LAST_RULE_IDX; j < k; j++)
5122 REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
5123 REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
5126 return LM_STATUS_SUCCESS;
5127 } /* LM_SetReceiveMask */
5131 /******************************************************************************/
5133 /* Disable the interrupt and put the transmitter and receiver engines in */
5134 /* an idle state. Also aborts all pending send requests and receive */
5138 /* LM_STATUS_SUCCESS */
5139 /******************************************************************************/
5142 PLM_DEVICE_BLOCK pDevice)
5147 LM_DisableInterrupt(pDevice);
5149 LM_DisableChip(pDevice);
5152 * If we do not have a status block pointer, then
5153 * the device hasn't really been opened. Do not
5154 * attempt to clean up packets.
5156 if (pDevice->pStatusBlkVirt == NULL)
5157 return LM_STATUS_SUCCESS;
5159 /* Abort packets that have already queued to go out. */
5160 Idx = pDevice->SendConIdx;
5163 if ((pPacket = pDevice->SendRing[Idx]))
5165 pDevice->SendRing[Idx] = 0;
5166 pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
5167 pDevice->TxCounters.TxPacketAbortedCnt++;
5169 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5170 Idx = (Idx + pPacket->u.Tx.FragCount) &
5171 T3_SEND_RCB_ENTRY_COUNT_MASK;
5173 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5181 /* Cleanup the receive return rings. */
5182 #ifdef BCM_NAPI_RXPOLL
5183 LM_ServiceRxPoll(pDevice, T3_RCV_RETURN_RCB_ENTRY_COUNT);
5185 LM_ServiceRxInterrupt(pDevice);
5188 /* Indicate packets to the protocol. */
5189 MM_IndicateTxPackets(pDevice);
5191 #ifdef BCM_NAPI_RXPOLL
5193 /* Move the receive packet descriptors in the ReceivedQ to the */
5197 pPacket = (PLM_PACKET) QQ_PopHead(
5198 &pDevice->RxPacketReceivedQ.Container);
5203 MM_UnmapRxDma(pDevice, pPacket);
5204 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5207 /* Indicate received packets to the protocols. */
5208 MM_IndicateRxPackets(pDevice);
5211 /* Clean up the Std Receive Producer ring. */
5212 /* Don't always trust the consumer idx in the status block in case of */
5216 while(Idx < T3_STD_RCV_RCB_ENTRY_COUNT)
5218 if ((pPacket = pDevice->RxStdRing[Idx]))
5220 MM_UnmapRxDma(pDevice, pPacket);
5221 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5222 pDevice->RxStdRing[Idx] = 0;
5228 /* Reinitialize our copy of the indices. */
5229 pDevice->RxStdProdIdx = 0;
5231 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5232 /* Clean up the Jumbo Receive Producer ring. */
5235 while(Idx < T3_JUMBO_RCV_RCB_ENTRY_COUNT)
5237 if ((pPacket = pDevice->RxJumboRing[Idx]))
5239 MM_UnmapRxDma(pDevice, pPacket);
5240 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5241 pDevice->RxJumboRing[Idx] = 0;
5246 /* Reinitialize our copy of the indices. */
5247 pDevice->RxJumboProdIdx = 0;
5248 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
5250 /* Initialize the statistis Block */
5251 pDevice->pStatusBlkVirt->Status = 0;
5252 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
5253 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
5254 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
5256 return LM_STATUS_SUCCESS;
5261 /******************************************************************************/
5263 /* Disable the interrupt and put the transmitter and receiver engines in */
5264 /* an idle state. Aborts all pending send requests and receive buffers. */
5265 /* Also free all the receive buffers. */
5268 /* LM_STATUS_SUCCESS */
5269 /******************************************************************************/
5271 LM_DoHalt(LM_DEVICE_BLOCK *pDevice)
5276 LM_DisableFW(pDevice);
5278 LM_WritePreResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5281 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
5282 LM_WritePhy(pDevice, BCM546X_1c_SHADOW_REG,
5283 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN));
5285 /* Get the number of entries in the queue. */
5286 EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
5288 /* Make sure all the packets have been accounted for. */
5289 for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
5291 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
5295 MM_FreeRxBuffer(pDevice, pPacket);
5297 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5300 LM_ResetChip(pDevice);
5301 LM_WriteLegacySignatures(pDevice, LM_SHUTDOWN_RESET);
5303 /* Restore PCI configuration registers. */
5304 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
5305 pDevice->SavedCacheLineReg);
5306 LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
5307 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
5309 /* Reprogram the MAC address. */
5310 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
5312 return LM_STATUS_SUCCESS;
5317 LM_Halt(LM_DEVICE_BLOCK *pDevice)
5321 status = LM_DoHalt(pDevice);
5322 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5328 LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5330 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,T3_MAGIC_NUM_FIRMWARE_INIT_DONE);
5332 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5334 if (Mode == LM_INIT_RESET)
5336 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5338 else if (Mode == LM_SHUTDOWN_RESET)
5340 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5342 else if (Mode == LM_SUSPEND_RESET)
5344 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5351 LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5354 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5356 if (Mode == LM_INIT_RESET)
5358 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5359 T3_DRV_STATE_START_DONE);
5361 else if (Mode == LM_SHUTDOWN_RESET)
5363 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5364 T3_DRV_STATE_UNLOAD_DONE);
5371 LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5374 if (pDevice->AsfFlags & ASF_ENABLED)
5376 if (Mode == LM_INIT_RESET)
5378 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5380 else if (Mode == LM_SHUTDOWN_RESET)
5382 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5384 else if (Mode == LM_SUSPEND_RESET)
5386 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5393 LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
5396 LM_UINT32 j, tmp1 = 0, tmp2 = 0;
5398 /* Wait for access to the nvram interface before resetting. This is */
5399 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
5400 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
5402 /* Request access to the flash interface. */
5403 LM_NVRAM_AcquireLock(pDevice);
5406 Value32 = GRC_MISC_CFG_CORE_CLOCK_RESET;
5407 if (pDevice->Flags & PCI_EXPRESS_FLAG)
5409 if (REG_RD_OFFSET(pDevice, 0x7e2c) == 0x60) /* PCIE 1.0 system */
5411 REG_WR_OFFSET(pDevice, 0x7e2c, 0x20);
5413 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
5415 /* This bit prevents PCIE link training during GRC reset */
5416 REG_WR(pDevice, Grc.MiscCfg, BIT_29); /* Write bit 29 first */
5417 Value32 |= BIT_29; /* and keep bit 29 set during GRC reset */
5420 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5422 Value32 |= GRC_MISC_GPHY_KEEP_POWER_DURING_RESET;
5425 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5427 /* Save the MSI ENABLE bit (may need to save the message as well) */
5428 tmp1 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5432 RAW_REG_WR(pDevice, Grc.MiscCfg, Value32);
5435 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
5439 /* make sure we re-enable indirect accesses */
5440 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
5441 pDevice->MiscHostCtrl);
5443 /* Set MAX PCI retry to zero. */
5444 Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
5445 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
5447 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
5449 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
5452 MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
5454 /* Restore PCI command register. */
5455 MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
5456 pDevice->PciCommandStatusWords);
5458 /* Disable PCI-X relaxed ordering bit. */
5459 MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
5460 Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
5461 MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
5463 /* Enable memory arbiter */
5464 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5466 Value32 = REG_RD(pDevice,MemArbiter.Mode);
5467 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
5471 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
5474 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5476 /* restore the MSI ENABLE bit (may need to restore the message also) */
5477 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5478 tmp2 |= (tmp1 & (1 << 16));
5479 LM_RegWr( pDevice, T3_PCI_MSI_ENABLE, tmp2, TRUE );
5480 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5484 if (pDevice->ChipRevId == T3_CHIP_ID_5750_A3)
5486 /* Because of chip bug on A3, we need to kill the CPU */
5487 LM_DisableFW(pDevice);
5488 REG_WR_OFFSET(pDevice, 0x5000, 0x400);
5492 * BCM4785: In order to avoid repercussions from using potentially
5493 * defective internal ROM, stop the Rx RISC CPU, which is not
5496 if (pDevice->Flags & SB_CORE_FLAG) {
5497 LM_DisableFW(pDevice);
5498 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
5501 #ifdef BIG_ENDIAN_HOST
5502 /* Reconfigure the mode register. */
5503 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
5504 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
5505 GRC_MODE_BYTE_SWAP_DATA |
5506 GRC_MODE_WORD_SWAP_DATA;
5508 /* Reconfigure the mode register. */
5509 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
5511 REG_WR(pDevice, Grc.Mode, Value32);
5513 if ((pDevice->Flags & MINI_PCI_FLAG) &&
5514 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
5516 pDevice->ClockCtrl |= T3_PCI_CLKRUN_OUTPUT_EN;
5517 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
5519 pDevice->ClockCtrl |= T3_PCI_FORCE_CLKRUN;
5521 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
5524 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
5526 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
5528 else if(pDevice->PhyFlags & PHY_IS_FIBER)
5530 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
5534 pDevice->MacMode = 0;
5537 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
5538 REG_RD_BACK(pDevice, MacCtrl.Mode);
5541 /* BCM4785: Don't use any firmware, so don't wait */
5542 if (!pDevice->Flags & SB_CORE_FLAG) {
5543 /* Wait for the firmware to finish initialization. */
5544 for(j = 0; j < 100000; j++) {
5550 Value32 = MEM_RD_OFFSET(pDevice, T3_FIRMWARE_MAILBOX);
5551 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE) {
5555 if ((j >= 0x100000) && (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) {
5556 /* if the boot code is not running */
5557 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS) {
5558 LM_DEVICE_BLOCK *pDevice2;
5560 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
5561 pDevice2 = MM_FindPeerDev(pDevice);
5562 if (pDevice2 && !pDevice2->InitDone)
5563 REG_WR(pDevice2, Nvram.Cmd, NVRAM_CMD_RESET);
5565 LM_NVRAM_ReleaseLock(pDevice);
5570 if ((pDevice->Flags & PCI_EXPRESS_FLAG) &&
5571 (pDevice->ChipRevId != T3_CHIP_ID_5750_A0))
5573 /* Enable PCIE bug fix */
5574 Value32 = REG_RD_OFFSET(pDevice, 0x7c00);
5575 REG_WR_OFFSET(pDevice, 0x7c00, Value32 | BIT_25 | BIT_29);
5579 pDevice->AsfFlags = 0;
5580 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
5582 if (Value32 == T3_NIC_DATA_SIG)
5584 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
5585 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
5587 pDevice->AsfFlags = ASF_ENABLED;
5588 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5590 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
5596 return LM_STATUS_SUCCESS;
5601 LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode)
5603 LM_DisableFW(pDevice);
5604 LM_WritePreResetSignatures(pDevice, Mode);
5605 if (pDevice->InitDone)
5611 LM_DisableChip(pDevice);
5613 LM_ResetChip(pDevice);
5614 LM_WriteLegacySignatures(pDevice, Mode);
5615 LM_WritePostResetSignatures(pDevice, Mode);
5616 return LM_STATUS_SUCCESS;
5619 /******************************************************************************/
5623 /******************************************************************************/
5625 LM_ServiceTxInterrupt(
5626 PLM_DEVICE_BLOCK pDevice) {
5631 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5633 /* Get our copy of the consumer index. The buffer descriptors */
5634 /* that are in between the consumer indices are freed. */
5635 SwConIdx = pDevice->SendConIdx;
5637 /* Move the packets from the TxPacketActiveQ that are sent out to */
5638 /* the TxPacketXmittedQ. Packets that are sent use the */
5639 /* descriptors that are between SwConIdx and HwConIdx. */
5640 while(SwConIdx != HwConIdx)
5642 pPacket = pDevice->SendRing[SwConIdx];
5643 pDevice->SendRing[SwConIdx] = 0;
5645 /* Set the return status. */
5646 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5648 /* Put the packet in the TxPacketXmittedQ for indication later. */
5649 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5651 /* Move to the next packet's BD. */
5652 SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
5653 T3_SEND_RCB_ENTRY_COUNT_MASK;
5655 /* Update the number of unused BDs. */
5656 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5658 /* Get the new updated HwConIdx. */
5659 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5662 /* Save the new SwConIdx. */
5663 pDevice->SendConIdx = SwConIdx;
5665 } /* LM_ServiceTxInterrupt */
5668 #ifdef BCM_NAPI_RXPOLL
5669 /******************************************************************************/
5673 /******************************************************************************/
5675 LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit)
5677 PLM_PACKET pPacket=NULL;
5679 LM_UINT32 HwRcvRetProdIdx;
5680 LM_UINT32 SwRcvRetConIdx;
5683 /* Loop thru the receive return rings for received packets. */
5684 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
5686 SwRcvRetConIdx = pDevice->RcvRetConIdx;
5688 while (SwRcvRetConIdx != HwRcvRetProdIdx)
5690 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
5692 /* Get the received packet descriptor. */
5693 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
5694 MM_UINT_PTR(pRcvBd->Opaque));
5696 switch(pPacket->u.Rx.RcvProdRing) {
5697 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5698 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
5699 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5702 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
5703 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5707 /* Check the error flag. */
5708 if(pRcvBd->ErrorFlag &&
5709 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5711 pPacket->PacketStatus = LM_STATUS_FAILURE;
5713 pDevice->RxCounters.RxPacketErrCnt++;
5715 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
5717 pDevice->RxCounters.RxErrCrcCnt++;
5720 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
5722 pDevice->RxCounters.RxErrCollCnt++;
5725 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
5727 pDevice->RxCounters.RxErrLinkLostCnt++;
5730 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
5732 pDevice->RxCounters.RxErrPhyDecodeCnt++;
5735 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5737 pDevice->RxCounters.RxErrOddNibbleCnt++;
5740 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
5742 pDevice->RxCounters.RxErrMacAbortCnt++;
5745 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
5747 pDevice->RxCounters.RxErrShortPacketCnt++;
5750 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
5752 pDevice->RxCounters.RxErrNoResourceCnt++;
5755 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
5757 pDevice->RxCounters.RxErrLargePacketCnt++;
5762 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5763 pPacket->PacketSize = pRcvBd->Len - 4;
5765 pPacket->Flags = pRcvBd->Flags;
5766 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
5768 pPacket->VlanTag = pRcvBd->VlanTag;
5771 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
5774 /* Put the packet descriptor containing the received packet */
5775 /* buffer in the RxPacketReceivedQ for indication later. */
5776 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
5778 /* Go to the next buffer descriptor. */
5779 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
5780 pDevice->RcvRetRcbEntryCountMask;
5782 if (++received >= limit)
5788 pDevice->RcvRetConIdx = SwRcvRetConIdx;
5790 /* Update the receive return ring consumer index. */
5791 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
5792 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5794 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
5801 } /* LM_ServiceRxPoll */
5802 #endif /* BCM_NAPI_RXPOLL */
5805 /******************************************************************************/
5809 /******************************************************************************/
5811 LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice)
5813 #ifndef BCM_NAPI_RXPOLL
5817 LM_UINT32 HwRcvRetProdIdx;
5818 LM_UINT32 SwRcvRetConIdx;
5820 /* Loop thru the receive return rings for received packets. */
5821 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
5823 SwRcvRetConIdx = pDevice->RcvRetConIdx;
5824 #ifdef BCM_NAPI_RXPOLL
5825 if (!pDevice->RxPoll)
5827 if (SwRcvRetConIdx != HwRcvRetProdIdx)
5829 if (MM_ScheduleRxPoll(pDevice) == LM_STATUS_SUCCESS)
5831 pDevice->RxPoll = TRUE;
5832 REG_WR(pDevice, Grc.Mode,
5833 pDevice->GrcMode | GRC_MODE_NO_INTERRUPT_ON_RECEIVE);
5839 while(SwRcvRetConIdx != HwRcvRetProdIdx)
5841 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
5843 /* Get the received packet descriptor. */
5844 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
5845 MM_UINT_PTR(pRcvBd->Opaque));
5847 switch(pPacket->u.Rx.RcvProdRing) {
5848 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5849 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
5850 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5853 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
5854 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5858 /* Check the error flag. */
5859 if(pRcvBd->ErrorFlag &&
5860 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5862 pPacket->PacketStatus = LM_STATUS_FAILURE;
5864 pDevice->RxCounters.RxPacketErrCnt++;
5866 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
5868 pDevice->RxCounters.RxErrCrcCnt++;
5871 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
5873 pDevice->RxCounters.RxErrCollCnt++;
5876 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
5878 pDevice->RxCounters.RxErrLinkLostCnt++;
5881 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
5883 pDevice->RxCounters.RxErrPhyDecodeCnt++;
5886 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5888 pDevice->RxCounters.RxErrOddNibbleCnt++;
5891 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
5893 pDevice->RxCounters.RxErrMacAbortCnt++;
5896 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
5898 pDevice->RxCounters.RxErrShortPacketCnt++;
5901 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
5903 pDevice->RxCounters.RxErrNoResourceCnt++;
5906 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
5908 pDevice->RxCounters.RxErrLargePacketCnt++;
5913 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5914 pPacket->PacketSize = pRcvBd->Len - 4;
5916 pPacket->Flags = pRcvBd->Flags;
5917 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
5919 pPacket->VlanTag = pRcvBd->VlanTag;
5922 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
5925 /* Put the packet descriptor containing the received packet */
5926 /* buffer in the RxPacketReceivedQ for indication later. */
5927 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
5929 /* Go to the next buffer descriptor. */
5930 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
5931 pDevice->RcvRetRcbEntryCountMask;
5935 pDevice->RcvRetConIdx = SwRcvRetConIdx;
5937 /* Update the receive return ring consumer index. */
5938 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
5939 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5941 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
5949 } /* LM_ServiceRxInterrupt */
5953 /******************************************************************************/
5955 /* This is the interrupt event handler routine. It acknowledges all */
5956 /* pending interrupts and process all pending events. */
5959 /* LM_STATUS_SUCCESS */
5960 /******************************************************************************/
5962 LM_ServiceInterrupts(
5963 PLM_DEVICE_BLOCK pDevice)
5966 int ServicePhyInt = FALSE;
5968 /* Setup the phy chip whenever the link status changes. */
5969 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
5971 Value32 = REG_RD(pDevice, MacCtrl.Status);
5972 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
5974 if (Value32 & MAC_STATUS_MI_INTERRUPT)
5976 ServicePhyInt = TRUE;
5979 else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
5981 ServicePhyInt = TRUE;
5986 if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
5988 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
5989 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
5990 ServicePhyInt = TRUE;
5993 #ifdef INCLUDE_TBI_SUPPORT
5994 if (pDevice->IgnoreTbiLinkChange == TRUE)
5996 ServicePhyInt = FALSE;
5999 if (ServicePhyInt == TRUE)
6001 MM_ACQUIRE_PHY_LOCK_IN_IRQ(pDevice);
6002 LM_SetupPhy(pDevice);
6003 MM_RELEASE_PHY_LOCK_IN_IRQ(pDevice);
6006 /* Service receive and transmit interrupts. */
6007 LM_ServiceRxInterrupt(pDevice);
6008 LM_ServiceTxInterrupt(pDevice);
6010 #ifndef BCM_NAPI_RXPOLL
6011 /* No spinlock for this queue since this routine is serialized. */
6012 if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
6014 /* Indicate receive packets. */
6015 MM_IndicateRxPackets(pDevice);
6019 /* No spinlock for this queue since this routine is serialized. */
6020 if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
6022 MM_IndicateTxPackets(pDevice);
6025 return LM_STATUS_SUCCESS;
6026 } /* LM_ServiceInterrupts */
6029 /******************************************************************************/
6030 /* Description: Add a Multicast address. Note that MC addresses, once added, */
6031 /* cannot be individually deleted. All addresses must be */
6035 /******************************************************************************/
6037 LM_MulticastAdd(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6044 Crc32 = ComputeCrc32(pMcAddress, ETHERNET_ADDRESS_SIZE);
6046 /* The most significant 7 bits of the CRC32 (no inversion), */
6047 /* are used to index into one of the possible 128 bit positions. */
6048 Bitpos = ~Crc32 & 0x7f;
6050 /* Hash register index. */
6051 RegIndex = (Bitpos & 0x60) >> 5;
6053 /* Bit to turn on within a hash register. */
6056 /* Enable the multicast bit. */
6057 pDevice->MulticastHash[RegIndex] |= (1 << Bitpos);
6059 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
6061 return LM_STATUS_SUCCESS;
6065 /******************************************************************************/
6069 /******************************************************************************/
6071 LM_MulticastDel(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6073 return LM_STATUS_FAILURE;
6074 } /* LM_MulticastDel */
6078 /******************************************************************************/
6082 /******************************************************************************/
6084 LM_MulticastClear(LM_DEVICE_BLOCK *pDevice)
6088 for (i = 0; i < 4; i++)
6090 pDevice->MulticastHash[i] = 0;
6092 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
6094 return LM_STATUS_SUCCESS;
6095 } /* LM_MulticastClear */
6099 /******************************************************************************/
6103 /******************************************************************************/
6106 PLM_DEVICE_BLOCK pDevice,
6107 PLM_UINT8 pMacAddress)
6111 for(j = 0; j < 4; j++)
6113 REG_WR(pDevice, MacCtrl.MacAddr[j].High,
6114 (pMacAddress[0] << 8) | pMacAddress[1]);
6115 REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
6116 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6117 (pMacAddress[4] << 8) | pMacAddress[5]);
6120 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
6121 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
6123 for (j = 0; j < 12; j++)
6125 REG_WR(pDevice, MacCtrl.MacAddrExt[j].High,
6126 (pMacAddress[0] << 8) | pMacAddress[1]);
6127 REG_WR(pDevice, MacCtrl.MacAddrExt[j].Low,
6128 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6129 (pMacAddress[4] << 8) | pMacAddress[5]);
6132 return LM_STATUS_SUCCESS;
6136 LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice)
6138 /* Turn off tap power management. */
6139 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6141 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
6142 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
6143 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
6144 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
6145 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
6146 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6147 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
6148 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6149 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
6150 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
6151 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
6157 /******************************************************************************/
6161 /* LM_STATUS_LINK_ACTIVE */
6162 /* LM_STATUS_LINK_DOWN */
6163 /******************************************************************************/
6166 PLM_DEVICE_BLOCK pDevice)
6168 LM_LINE_SPEED CurrentLineSpeed;
6169 LM_DUPLEX_MODE CurrentDuplexMode;
6170 LM_STATUS CurrentLinkStatus;
6175 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
6177 if ((pDevice->PhyFlags & PHY_RESET_ON_LINKDOWN) &&
6178 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE))
6180 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6181 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6182 if(!(Value32 & PHY_STATUS_LINK_PASS))
6184 LM_ResetPhy(pDevice);
6187 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6189 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6190 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6192 if(!pDevice->InitDone)
6197 if(!(Value32 & PHY_STATUS_LINK_PASS))
6199 LM_PhyTapPowerMgmt(pDevice);
6201 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6202 for(j = 0; j < 1000; j++)
6206 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6207 if(Value32 & PHY_STATUS_LINK_PASS)
6214 if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
6216 if(!(Value32 & PHY_STATUS_LINK_PASS) &&
6217 (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
6219 LM_ResetPhy(pDevice);
6224 else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
6225 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
6227 LM_WritePhy(pDevice, 0x15, 0x0a75);
6228 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6229 LM_WritePhy(pDevice, 0x1c, 0x8d68);
6230 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6233 /* Acknowledge interrupts. */
6234 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6235 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6237 /* Configure the interrupt mask. */
6238 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6240 LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
6243 /* Configure PHY led mode. */
6244 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
6245 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
6247 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_1)
6249 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
6250 BCM540X_EXT_CTRL_LINK3_LED_MODE);
6254 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
6257 else if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
6260 ** Set up the 'link' LED for the 4785+5461 combo,
6261 ** using the INTR/ENERGYDET pin (on the BCM4785 bringup board).
6263 LM_WritePhy( pDevice,
6264 BCM546X_1c_SHADOW_REG,
6265 (BCM546X_1c_SPR_CTRL_2 | BCM546X_1c_WR_EN | BCM546X_1c_SP2_NRG_DET) );
6268 ** Set up the LINK LED mode for the 4785+5461 combo,
6269 ** using the 5461 SLAVE/ANEN pin (on the BCM4785 bringup board) as
6270 ** active low link status (phy ready) feedback to the 4785
6272 LM_WritePhy( pDevice,
6273 BCM546X_1c_SHADOW_REG,
6274 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN | BCM546X_1c_SP1_LINK_LED) );
6277 if (pDevice->PhyFlags & PHY_CAPACITIVE_COUPLING)
6279 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4007);
6280 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &Value32);
6281 if (!(Value32 & BIT_10))
6283 /* set the bit and re-link */
6284 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, Value32 | BIT_10);
6285 return LM_STATUS_LINK_SETTING_MISMATCH;
6289 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6291 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
6292 B57_INFO(("Force to active link of 1000 MBPS and full duplex mod.\n"));
6293 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6295 /* Set the line speed based on the robo switch type */
6296 robo = ((PUM_DEVICE_BLOCK)pDevice)->robo;
6297 if (robo->devid == DEVID5325)
6299 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6303 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6305 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6307 /* Save line settings. */
6308 pDevice->LineSpeed = CurrentLineSpeed;
6309 pDevice->DuplexMode = CurrentDuplexMode;
6312 /* Get current link and duplex mode. */
6313 for(j = 0; j < 100; j++)
6315 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6316 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6318 if(Value32 & PHY_STATUS_LINK_PASS)
6325 if(Value32 & PHY_STATUS_LINK_PASS)
6328 /* Determine the current line and duplex settings. */
6329 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6330 for(j = 0; j < 2000; j++)
6334 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6341 switch(Value32 & BCM540X_AUX_SPEED_MASK)
6343 case BCM540X_AUX_10BASET_HD:
6344 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6345 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6348 case BCM540X_AUX_10BASET_FD:
6349 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6350 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6353 case BCM540X_AUX_100BASETX_HD:
6354 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6355 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6358 case BCM540X_AUX_100BASETX_FD:
6359 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6360 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6363 case BCM540X_AUX_100BASET_HD:
6364 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6365 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6368 case BCM540X_AUX_100BASET_FD:
6369 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6370 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6375 CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
6376 CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
6380 /* Make sure we are in auto-neg mode. */
6381 for (j = 0; j < 200; j++)
6383 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6384 if(Value32 && Value32 != 0x7fff)
6390 pDevice->RequestedLineSpeed == LM_LINE_SPEED_10MBPS &&
6391 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_HALF)
6399 /* Use the current line settings for "auto" mode. */
6400 if(pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
6402 if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
6404 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6406 /* We may be exiting low power mode and the link is in */
6407 /* 10mb. In this case, we need to restart autoneg. */
6409 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
6411 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6416 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6421 /* Force line settings. */
6422 /* Use the current setting if it matches the user's requested */
6424 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6425 if((pDevice->LineSpeed == CurrentLineSpeed) &&
6426 (pDevice->DuplexMode == CurrentDuplexMode))
6428 if ((pDevice->DisableAutoNeg &&
6429 !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
6430 (!pDevice->DisableAutoNeg &&
6431 (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
6433 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6437 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6442 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6446 /* Save line settings. */
6447 pDevice->LineSpeed = CurrentLineSpeed;
6448 pDevice->DuplexMode = CurrentDuplexMode;
6452 return CurrentLinkStatus;
6453 } /* LM_InitBcm540xPhy */
6455 /******************************************************************************/
6459 /******************************************************************************/
6462 PLM_DEVICE_BLOCK pDevice,
6463 LM_UINT32 LocalPhyAd,
6464 LM_UINT32 RemotePhyAd)
6466 LM_FLOW_CONTROL FlowCap;
6468 /* Resolve flow control. */
6469 FlowCap = LM_FLOW_CONTROL_NONE;
6471 /* See Table 28B-3 of 802.3ab-1999 spec. */
6472 if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
6474 if(pDevice->PhyFlags & PHY_IS_FIBER){
6475 LocalPhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6476 PHY_AN_AD_PAUSE_CAPABLE);
6477 RemotePhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6478 PHY_AN_AD_PAUSE_CAPABLE);
6480 if (LocalPhyAd & PHY_AN_AD_1000XPAUSE)
6481 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
6482 if (LocalPhyAd & PHY_AN_AD_1000XPSE_ASYM)
6483 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
6484 if (RemotePhyAd & PHY_AN_AD_1000XPAUSE)
6485 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6486 if (RemotePhyAd & PHY_AN_AD_1000XPSE_ASYM)
6487 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6490 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6492 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6494 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6496 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6497 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6499 else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
6501 FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
6506 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6508 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6509 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6513 else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6515 if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
6516 (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
6518 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6524 FlowCap = pDevice->FlowControlCap;
6527 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
6529 /* Enable/disable rx PAUSE. */
6530 pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
6531 if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
6532 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6533 pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
6535 pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
6536 pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
6539 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
6541 /* Enable/disable tx PAUSE. */
6542 pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
6543 if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
6544 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6545 pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
6547 pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6548 pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
6551 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
6553 return LM_STATUS_SUCCESS;
6557 #ifdef INCLUDE_TBI_SUPPORT
6558 /******************************************************************************/
6562 /******************************************************************************/
6565 PLM_DEVICE_BLOCK pDevice)
6571 Value32 = REG_RD(pDevice, MacCtrl.Status);
6573 /* Reset the SERDES during init and when we have link. */
6574 if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
6576 /* Set PLL lock range. */
6577 LM_WritePhy(pDevice, 0x16, 0x8007);
6579 /* Software reset. */
6580 LM_WritePhy(pDevice, 0x00, 0x8000);
6582 /* Wait for reset to complete. */
6583 for(j = 0; j < 500; j++)
6588 /* Config mode; seletct PMA/Ch 1 regs. */
6589 LM_WritePhy(pDevice, 0x10, 0x8411);
6591 /* Enable auto-lock and comdet, select txclk for tx. */
6592 LM_WritePhy(pDevice, 0x11, 0x0a10);
6594 LM_WritePhy(pDevice, 0x18, 0x00a0);
6595 LM_WritePhy(pDevice, 0x16, 0x41ff);
6597 /* Assert and deassert POR. */
6598 LM_WritePhy(pDevice, 0x13, 0x0400);
6600 LM_WritePhy(pDevice, 0x13, 0x0000);
6602 LM_WritePhy(pDevice, 0x11, 0x0a50);
6604 LM_WritePhy(pDevice, 0x11, 0x0a10);
6606 /* Delay for signal to stabilize. */
6607 for(j = 0; j < 15000; j++)
6612 /* Deselect the channel register so we can read the PHY id later. */
6613 LM_WritePhy(pDevice, 0x10, 0x8011);
6616 return LM_STATUS_SUCCESS;
6621 /******************************************************************************/
6625 /******************************************************************************/
6628 PLM_DEVICE_BLOCK pDevice)
6630 LM_STATUS CurrentLinkStatus;
6631 AUTONEG_STATUS AnStatus = 0;
6635 LM_UINT32 MacStatus, RemotePhyAd, LocalPhyAd;
6636 LM_FLOW_CONTROL PreviousFlowControl = pDevice->FlowControl;
6639 if (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE)
6641 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
6642 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
6643 return LM_STATUS_SUCCESS;
6647 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
6648 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && pDevice->InitDone)
6650 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6651 if ((MacStatus & (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED |
6652 MAC_STATUS_CFG_CHANGED | MAC_STATUS_RECEIVING_CFG))
6653 == (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED))
6656 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
6657 MAC_STATUS_CFG_CHANGED);
6658 return LM_STATUS_SUCCESS;
6661 pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
6663 /* Initialize the send_config register. */
6664 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
6666 pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
6667 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
6670 /* Initialize the BCM8002 SERDES PHY. */
6671 switch(pDevice->PhyId & PHY_ID_MASK)
6673 case PHY_BCM8002_PHY_ID:
6674 LM_InitBcm800xPhy(pDevice);
6681 /* Enable link change interrupt. */
6682 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
6684 /* Default to link down. */
6685 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6687 /* Get the link status. */
6688 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6690 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
6692 LM_UINT32 SgDigCtrl, SgDigStatus;
6693 LM_UINT32 SerdesCfg = 0;
6694 LM_UINT32 ExpectedSgDigCtrl = 0;
6695 LM_UINT32 WorkAround = 0;
6696 LM_UINT32 PortA = 1;
6698 if ((pDevice->ChipRevId != T3_CHIP_ID_5704_A0) &&
6699 (pDevice->ChipRevId != T3_CHIP_ID_5704_A1))
6702 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
6707 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6709 /* Save voltage reg bits & bits 14:0 */
6710 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
6711 (BIT_23 | BIT_22 | BIT_21 | BIT_20 | 0x7fff );
6716 /* preserve the voltage regulator bits */
6717 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
6718 (BIT_23 | BIT_22 | BIT_21 | BIT_20);
6721 SgDigCtrl = REG_RD(pDevice, MacCtrl.SgDigControl);
6722 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
6723 (pDevice->DisableAutoNeg == FALSE))
6726 ExpectedSgDigCtrl = 0x81388400;
6727 LocalPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
6728 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6730 ExpectedSgDigCtrl |= BIT_11;
6732 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6734 ExpectedSgDigCtrl |= BIT_12;
6736 if (SgDigCtrl != ExpectedSgDigCtrl)
6740 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6742 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011000 | SerdesCfg);
6746 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011880 | SerdesCfg);
6749 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl |
6751 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
6753 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl);
6754 pDevice->AutoNegJustInited = TRUE;
6756 /* If autoneg is off, you only get SD when link is up */
6757 else if(MacStatus & (MAC_STATUS_PCS_SYNCED |
6758 MAC_STATUS_SIGNAL_DETECTED))
6760 SgDigStatus = REG_RD(pDevice, MacCtrl.SgDigStatus);
6761 if ((SgDigStatus & BIT_1) &&
6762 (MacStatus & MAC_STATUS_PCS_SYNCED))
6764 /* autoneg. completed */
6766 if(SgDigStatus & BIT_19)
6768 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6771 if(SgDigStatus & BIT_20)
6773 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6776 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
6777 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6778 pDevice->AutoNegJustInited = FALSE;
6780 else if (!(SgDigStatus & BIT_1))
6782 if (pDevice->AutoNegJustInited == TRUE)
6784 /* we may be checking too soon, so check again */
6785 /* at the next poll interval */
6786 pDevice->AutoNegJustInited = FALSE;
6790 /* autoneg. failed */
6795 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6797 REG_WR(pDevice, MacCtrl.SerdesCfg,
6798 0xc010000 | (SerdesCfg & ~0x00001000));
6802 REG_WR(pDevice, MacCtrl.SerdesCfg,
6803 0xc010880 | SerdesCfg);
6808 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6810 REG_WR(pDevice, MacCtrl.SerdesCfg,
6811 0x4010000 | (SerdesCfg & ~0x00001000));
6815 REG_WR(pDevice, MacCtrl.SerdesCfg,
6816 0x4010880 | SerdesCfg);
6820 /* turn off autoneg. to allow traffic to pass */
6821 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
6822 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
6824 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6825 if ((MacStatus & MAC_STATUS_PCS_SYNCED) && !(MacStatus & MAC_STATUS_RECEIVING_CFG))
6827 LM_SetFlowControl(pDevice, 0, 0);
6828 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6836 if (SgDigCtrl & BIT_31) {
6842 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6844 REG_WR(pDevice, MacCtrl.SerdesCfg,
6845 0xc010000 | (SerdesCfg & ~0x00001000));
6849 REG_WR(pDevice, MacCtrl.SerdesCfg,
6850 0xc010880 | SerdesCfg);
6855 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6857 REG_WR(pDevice, MacCtrl.SerdesCfg,
6858 0x4010000 | (SerdesCfg & ~0x00001000));
6862 REG_WR(pDevice, MacCtrl.SerdesCfg,
6863 0x4010880 | SerdesCfg);
6867 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
6869 if(MacStatus & MAC_STATUS_PCS_SYNCED)
6871 LM_SetFlowControl(pDevice, 0, 0);
6872 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6876 else if(MacStatus & MAC_STATUS_PCS_SYNCED)
6878 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
6879 (pDevice->DisableAutoNeg == FALSE))
6881 /* auto-negotiation mode. */
6882 /* Initialize the autoneg default capaiblities. */
6883 AutonegInit(&pDevice->AnInfo);
6885 /* Set the context pointer to point to the main device structure. */
6886 pDevice->AnInfo.pContext = pDevice;
6888 /* Setup flow control advertisement register. */
6889 Value32 = GetPhyAdFlowCntrlSettings(pDevice);
6890 if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
6892 pDevice->AnInfo.mr_adv_sym_pause = 1;
6896 pDevice->AnInfo.mr_adv_sym_pause = 0;
6899 if(Value32 & PHY_AN_AD_ASYM_PAUSE)
6901 pDevice->AnInfo.mr_adv_asym_pause = 1;
6905 pDevice->AnInfo.mr_adv_asym_pause = 0;
6908 /* Try to autoneg up to six times. */
6909 if (pDevice->IgnoreTbiLinkChange)
6917 for (j = 0; j < Cnt; j++)
6919 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
6921 Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
6922 REG_WR(pDevice, MacCtrl.Mode, Value32);
6923 REG_RD_BACK(pDevice, MacCtrl.Mode);
6926 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
6927 MAC_MODE_SEND_CONFIGS);
6928 REG_RD_BACK(pDevice, MacCtrl.Mode);
6932 pDevice->AnInfo.State = AN_STATE_UNKNOWN;
6933 pDevice->AnInfo.CurrentTime_us = 0;
6935 REG_WR(pDevice, Grc.Timer, 0);
6936 for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
6939 AnStatus = Autoneg8023z(&pDevice->AnInfo);
6941 if((AnStatus == AUTONEG_STATUS_DONE) ||
6942 (AnStatus == AUTONEG_STATUS_FAILED))
6947 pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
6950 if((AnStatus == AUTONEG_STATUS_DONE) ||
6951 (AnStatus == AUTONEG_STATUS_FAILED))
6957 if (!(REG_RD(pDevice, MacCtrl.Status) &
6958 MAC_STATUS_PCS_SYNCED)) {
6964 /* Stop sending configs. */
6965 MM_AnTxIdle(&pDevice->AnInfo);
6967 /* Resolve flow control settings. */
6968 if((AnStatus == AUTONEG_STATUS_DONE) &&
6969 pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
6970 pDevice->AnInfo.mr_lp_adv_full_duplex)
6972 LM_UINT32 RemotePhyAd;
6973 LM_UINT32 LocalPhyAd;
6976 if(pDevice->AnInfo.mr_adv_sym_pause)
6978 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
6981 if(pDevice->AnInfo.mr_adv_asym_pause)
6983 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
6987 if(pDevice->AnInfo.mr_lp_adv_sym_pause)
6989 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6992 if(pDevice->AnInfo.mr_lp_adv_asym_pause)
6994 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6997 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
6999 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7003 LM_SetFlowControl(pDevice, 0, 0);
7005 for (j = 0; j < 30; j++)
7008 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7009 MAC_STATUS_CFG_CHANGED);
7010 REG_RD_BACK(pDevice, MacCtrl.Status);
7012 if ((REG_RD(pDevice, MacCtrl.Status) &
7013 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7016 if (pDevice->TbiFlags & TBI_POLLING_FLAGS)
7018 Value32 = REG_RD(pDevice, MacCtrl.Status);
7019 if (Value32 & MAC_STATUS_RECEIVING_CFG)
7021 pDevice->IgnoreTbiLinkChange = TRUE;
7023 else if (pDevice->TbiFlags & TBI_POLLING_INTR_FLAG)
7025 pDevice->IgnoreTbiLinkChange = FALSE;
7028 Value32 = REG_RD(pDevice, MacCtrl.Status);
7029 if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
7030 (Value32 & MAC_STATUS_PCS_SYNCED) &&
7031 ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
7033 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7038 /* We are forcing line speed. */
7039 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7040 LM_SetFlowControl(pDevice, 0, 0);
7042 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7043 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7044 MAC_MODE_SEND_CONFIGS);
7047 /* Set the link polarity bit. */
7048 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7049 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7051 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7052 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7054 for (j = 0; j < 100; j++)
7056 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7057 MAC_STATUS_CFG_CHANGED);
7058 REG_RD_BACK(pDevice, MacCtrl.Status);
7060 if ((REG_RD(pDevice, MacCtrl.Status) &
7061 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7065 Value32 = REG_RD(pDevice, MacCtrl.Status);
7066 if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
7068 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7069 if (pDevice->DisableAutoNeg == FALSE)
7071 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7072 MAC_MODE_SEND_CONFIGS);
7073 REG_RD_BACK(pDevice, MacCtrl.Mode);
7075 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7079 /* Initialize the current link status. */
7080 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7082 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7083 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7084 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7085 LED_CTRL_OVERRIDE_LINK_LED |
7086 LED_CTRL_1000MBPS_LED_ON);
7090 pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
7091 pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
7092 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7093 LED_CTRL_OVERRIDE_LINK_LED |
7094 LED_CTRL_OVERRIDE_TRAFFIC_LED);
7097 /* Indicate link status. */
7098 if ((pDevice->LinkStatus != CurrentLinkStatus) ||
7099 ((CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7100 (PreviousFlowControl != pDevice->FlowControl)))
7102 pDevice->LinkStatus = CurrentLinkStatus;
7103 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7106 return LM_STATUS_SUCCESS;
7108 #endif /* INCLUDE_TBI_SUPPORT */
7111 /******************************************************************************/
7115 /******************************************************************************/
7118 PLM_DEVICE_BLOCK pDevice)
7120 LM_STATUS CurrentLinkStatus;
7123 /* Assume there is not link first. */
7124 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7126 /* Disable phy link change attention. */
7127 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7129 /* Clear link change attention. */
7130 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7131 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7132 MAC_STATUS_LINK_STATE_CHANGED);
7134 /* Disable auto-polling for the moment. */
7135 pDevice->MiMode = 0xc0000;
7136 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7137 REG_RD_BACK(pDevice, MacCtrl.MiMode);
7140 /* Determine the requested line speed and duplex. */
7141 pDevice->OldLineSpeed = pDevice->LineSpeed;
7142 /* Set line and duplex only if we don't have a Robo switch */
7143 if (!(pDevice->Flags & ROBO_SWITCH_FLAG)) {
7144 pDevice->LineSpeed = pDevice->RequestedLineSpeed;
7145 pDevice->DuplexMode = pDevice->RequestedDuplexMode;
7148 /* Set the phy to loopback mode. */
7149 if ((pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE) ||
7150 (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE))
7152 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7153 if(!(Value32 & PHY_CTRL_LOOPBACK_MODE) &&
7154 (pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE))
7156 /* Disable link change and PHY interrupts. */
7157 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7159 /* Clear link change attention. */
7160 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7161 MAC_STATUS_CFG_CHANGED);
7163 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7166 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7167 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7168 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
7169 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
7170 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705 ||
7171 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 &&
7172 (pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID))
7174 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7177 /* Prevent the interrupt handling from being called. */
7178 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7179 (pDevice->pStatusBlkVirt->Status &
7180 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7182 /* GMII interface. */
7183 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7184 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7185 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7186 REG_RD_BACK(pDevice, MacCtrl.Mode);
7189 /* Configure PHY led mode. */
7190 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7191 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
7193 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
7194 BCM540X_EXT_CTRL_LINK3_LED_MODE);
7198 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7202 while (REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)
7210 Value32 = DMA_WRITE_MODE_ENABLE |
7211 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
7212 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
7213 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
7214 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
7215 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
7216 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
7217 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
7218 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
7219 REG_WR(pDevice, DmaWrite.Mode, Value32);
7223 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7224 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7226 return LM_STATUS_SUCCESS;
7229 /* For Robo switch read PHY_CTRL_REG value as zero */
7230 if (pDevice->Flags & ROBO_SWITCH_FLAG)
7233 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7235 if(Value32 & PHY_CTRL_LOOPBACK_MODE)
7237 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7239 /* Re-enable link change interrupt. This was disabled when we */
7240 /* enter loopback mode. */
7241 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7243 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7247 REG_WR(pDevice, MacCtrl.MacEvent,
7248 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7253 /* Initialize the phy chip. */
7254 CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
7257 if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
7259 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7262 /* Setup flow control. */
7263 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
7264 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7266 LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
7268 FlowCap = LM_FLOW_CONTROL_NONE;
7270 if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
7272 if(pDevice->DisableAutoNeg == FALSE ||
7273 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
7275 LM_UINT32 ExpectedPhyAd;
7276 LM_UINT32 LocalPhyAd;
7277 LM_UINT32 RemotePhyAd;
7279 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
7280 pDevice->advertising = LocalPhyAd;
7281 LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
7283 ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7285 if(LocalPhyAd != ExpectedPhyAd)
7287 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7291 LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
7294 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7299 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7300 LM_SetFlowControl(pDevice, 0, 0);
7305 if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
7307 LM_ForceAutoNeg(pDevice);
7309 /* If we force line speed, we make get link right away. */
7310 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7311 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7312 if(Value32 & PHY_STATUS_LINK_PASS)
7314 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7318 /* GMII interface. */
7319 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7320 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7322 if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
7323 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7325 pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
7329 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7333 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7336 /* In order for the 5750 core in BCM4785 chip to work properly
7337 * in RGMII mode, the Led Control Register must be set up.
7339 if (pDevice->Flags & RGMII_MODE_FLAG)
7341 LM_UINT32 LedCtrl_Reg;
7343 LedCtrl_Reg = REG_RD(pDevice, MacCtrl.LedCtrl);
7344 LedCtrl_Reg &= ~(LED_CTRL_1000MBPS_LED_ON | LED_CTRL_100MBPS_LED_ON);
7346 if(pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7347 LedCtrl_Reg |= LED_CTRL_OVERRIDE_LINK_LED;
7348 else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS)
7349 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_100MBPS_LED_ON);
7350 else /* LM_LINE_SPEED_1000MBPS */
7351 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON);
7353 REG_WR(pDevice, MacCtrl.LedCtrl, LedCtrl_Reg);
7358 /* Set the MAC to operate in the appropriate duplex mode. */
7359 pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
7360 if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
7362 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7365 /* Set the link polarity bit. */
7366 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7367 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7369 if((pDevice->LedCtrl == LED_CTRL_PHY_MODE_2) ||
7370 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
7371 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
7373 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7378 if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7380 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7384 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7386 /* Enable auto polling. */
7387 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
7389 pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
7390 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7392 /* if using MAC led mode and not using auto polling, need to configure */
7393 /* mi status register */
7394 else if ((pDevice->LedCtrl &
7395 (LED_CTRL_PHY_MODE_1 | LED_CTRL_PHY_MODE_2)) == 0)
7397 if (CurrentLinkStatus != LM_STATUS_LINK_ACTIVE)
7399 REG_WR(pDevice, MacCtrl.MiStatus, 0);
7401 else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7403 REG_WR(pDevice, MacCtrl.MiStatus,
7404 MI_STATUS_ENABLE_LINK_STATUS_ATTN | MI_STATUS_10MBPS);
7408 REG_WR(pDevice, MacCtrl.MiStatus,
7409 MI_STATUS_ENABLE_LINK_STATUS_ATTN);
7413 /* Enable phy link change attention. */
7414 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7416 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7420 REG_WR(pDevice, MacCtrl.MacEvent,
7421 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7423 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
7424 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7425 (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7426 (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
7427 (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
7428 !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
7431 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7432 MAC_STATUS_CFG_CHANGED);
7433 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
7434 T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
7437 /* Indicate link status. */
7438 if (pDevice->LinkStatus != CurrentLinkStatus) {
7439 pDevice->LinkStatus = CurrentLinkStatus;
7440 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7443 return LM_STATUS_SUCCESS;
7444 } /* LM_SetupCopperPhy */
7448 LM_5714_FamForceFiber(
7449 PLM_DEVICE_BLOCK pDevice)
7451 LM_UINT32 Creg, new_bmcr;
7452 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7454 new_bmcr = Creg & ~PHY_CTRL_AUTO_NEG_ENABLE;
7456 if ( pDevice->RequestedDuplexMode == 0 ||
7457 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_FULL){
7459 new_bmcr |= PHY_CTRL_FULL_DUPLEX_MODE;
7462 if(Creg == new_bmcr)
7465 new_bmcr |= PHY_CTRL_SPEED_SELECT_1000MBPS; /* Reserve bit */
7467 /* Force a linkdown */
7468 LM_WritePhy(pDevice, PHY_AN_AD_REG, 0);
7469 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr |
7470 PHY_CTRL_RESTART_AUTO_NEG |
7471 PHY_CTRL_AUTO_NEG_ENABLE |
7472 PHY_CTRL_SPEED_SELECT_1000MBPS);
7476 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr);
7481 }/* LM_5714_FamForceFiber */
7485 LM_5714_FamGoFiberAutoNeg(
7486 PLM_DEVICE_BLOCK pDevice)
7488 LM_UINT32 adv,Creg,new;
7490 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7491 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &adv);
7493 new = adv & ~( PHY_AN_AD_1000XFULL |
7494 PHY_AN_AD_1000XHALF |
7495 PHY_AN_AD_1000XPAUSE |
7496 PHY_AN_AD_1000XPSE_ASYM |
7499 new |= PHY_AN_AD_1000XPAUSE;
7501 new |= PHY_AN_AD_1000XFULL;
7502 new |= PHY_AN_AD_1000XHALF;
7504 if ((new != adv) || !(Creg & PHY_CTRL_AUTO_NEG_ENABLE)){
7505 LM_WritePhy(pDevice, PHY_AN_AD_REG, new);
7507 pDevice->AutoNegJustInited=1;
7508 LM_WritePhy(pDevice, PHY_CTRL_REG, (Creg |
7509 PHY_CTRL_RESTART_AUTO_NEG |
7510 PHY_CTRL_SPEED_SELECT_1000MBPS |
7511 PHY_CTRL_AUTO_NEG_ENABLE) );
7515 } /* 5714_FamGoFiberAutoNeg */
7519 LM_5714_FamDoFiberLoopback(PLM_DEVICE_BLOCK pDevice)
7523 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7525 if( !(Value32 & PHY_CTRL_LOOPBACK_MODE) )
7527 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7529 /* Prevent the interrupt handling from being called. */
7530 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7531 (pDevice->pStatusBlkVirt->Status &
7532 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7535 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7536 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7540 }/* 5714_FamDoFiberLoopBack */
7543 /******************************************************************************/
7547 /******************************************************************************/
7550 LM_SetupNewFiberPhy(
7551 PLM_DEVICE_BLOCK pDevice)
7553 LM_STATUS LmStatus = LM_STATUS_SUCCESS;
7554 LM_UINT32 Creg,Sreg,rsav;
7556 rsav = pDevice->LinkStatus;
7558 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7559 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7562 /* Disable phy link change attention. */
7563 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7565 /* Clear link change attention. */
7566 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7567 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7568 MAC_STATUS_LINK_STATE_CHANGED);
7571 if( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7572 ( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ){
7575 }else if ( pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE){
7577 LM_5714_FamDoFiberLoopback(pDevice);
7578 goto fiberloopbackreturn;
7580 } else if( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) {
7582 LM_5714_FamGoFiberAutoNeg(pDevice);
7587 LM_5714_FamForceFiber(pDevice);
7589 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7590 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7592 if(Sreg & PHY_STATUS_LINK_PASS){
7594 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7595 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7597 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7599 if(Creg & PHY_CTRL_FULL_DUPLEX_MODE) {
7600 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7602 pDevice->DuplexMode = LM_DUPLEX_MODE_HALF;
7603 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7604 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7607 if(Creg & PHY_CTRL_AUTO_NEG_ENABLE){
7608 LM_UINT32 ours,partner;
7610 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &ours);
7611 LM_ReadPhy(pDevice,PHY_LINK_PARTNER_ABILITY_REG, &partner);
7612 LM_SetFlowControl(pDevice, ours, partner);
7616 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
7617 pDevice->LineSpeed = 0;
7620 if(rsav != pDevice->LinkStatus)
7621 MM_IndicateStatus(pDevice, pDevice->LinkStatus);
7623 fiberloopbackreturn:
7624 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7625 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7627 /* Enable link change interrupt. */
7628 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7631 } /* Setup New phy */
7634 LM_5714_FamFiberCheckLink(
7635 PLM_DEVICE_BLOCK pDevice)
7638 if(pDevice->AutoNegJustInited){
7639 pDevice->AutoNegJustInited=0;
7643 if ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) &&
7644 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) &&
7645 !(pDevice->PhyFlags & PHY_FIBER_FALLBACK)){
7648 LM_ReadPhy(pDevice, PHY_CTRL_REG, &bmcr);
7649 if (bmcr & PHY_CTRL_AUTO_NEG_ENABLE) {
7650 LM_UINT32 phy1, phy2;
7652 LM_WritePhy(pDevice, 0x1c, 0x7c00);
7653 LM_ReadPhy(pDevice, 0x1c, &phy1);
7655 LM_WritePhy(pDevice, 0x17, 0x0f01);
7656 LM_ReadPhy(pDevice, 0x15, &phy2);
7657 LM_ReadPhy(pDevice, 0x15, &phy2);
7659 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
7661 /* We have signal detect and not receiving
7665 pDevice->PhyFlags |= PHY_FIBER_FALLBACK;
7666 LM_5714_FamForceFiber(pDevice);
7670 else if ( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7671 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)) {
7674 LM_WritePhy(pDevice, 0x17, 0x0f01);
7675 LM_ReadPhy(pDevice, 0x15, &phy2);
7677 /* Receiving configs. */
7679 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
7680 LM_5714_FamGoFiberAutoNeg(pDevice);
7684 } /* LM_5714_FamFiberCheckLink */
7687 /******************************************************************************/
7691 /******************************************************************************/
7694 PLM_DEVICE_BLOCK pDevice)
7699 if(pDevice->PhyFlags & PHY_IS_FIBER)
7701 LmStatus = LM_SetupNewFiberPhy(pDevice);
7703 #ifdef INCLUDE_TBI_SUPPORT
7704 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
7706 LmStatus = LM_SetupFiberPhy(pDevice);
7709 #endif /* INCLUDE_TBI_SUPPORT */
7711 LmStatus = LM_SetupCopperPhy(pDevice);
7713 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
7715 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
7717 Value32 = REG_RD(pDevice, PciCfg.PciState);
7718 REG_WR(pDevice, PciCfg.PciState,
7719 Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
7722 if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7723 (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
7725 REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
7729 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
7731 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
7733 if (pDevice->LinkStatus == LM_STATUS_LINK_DOWN)
7735 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, 0);
7739 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
7740 pDevice->StatsCoalescingTicks);
7748 /* test data pattern */
7749 static LM_UINT32 pattern[4][6] = {
7750 /* For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6)
7751 For 5705 , each DFE TAP has 19-bits (low word 15, hi word 4)
7752 For simplicity, we check only 19-bits, so we don't have to
7753 distinguish which chip it is.
7754 the LO word contains 15 bits, make sure pattern data is < 0x7fff
7755 the HI word contains 6 bits, make sure pattern data is < 0x003f */
7756 {0x00005555, 0x00000005, /* ch0, TAP 0, LO/HI pattern */
7757 0x00002aaa, 0x0000000a, /* ch0, TAP 1, LO/HI pattern */
7758 0x00003456, 0x00000003}, /* ch0, TAP 2, LO/HI pattern */
7760 {0x00002aaa, 0x0000000a, /* ch1, TAP 0, LO/HI pattern */
7761 0x00003333, 0x00000003, /* ch1, TAP 1, LO/HI pattern */
7762 0x0000789a, 0x00000005}, /* ch1, TAP 2, LO/HI pattern */
7764 {0x00005a5a, 0x00000005, /* ch2, TAP 0, LO/HI pattern */
7765 0x00002a6a, 0x0000000a, /* ch2, TAP 1, LO/HI pattern */
7766 0x00001bcd, 0x00000003}, /* ch2, TAP 2, LO/HI pattern */
7768 {0x00002a5a, 0x0000000a, /* ch3, TAP 0, LO/HI pattern */
7769 0x000033c3, 0x00000003, /* ch3, TAP 1, LO/HI pattern */
7770 0x00002ef1, 0x00000005}, /* ch3, TAP 2, LO/HI pattern */
7773 /********************************************************/
7774 /* Routine to wait for PHY Macro Command to complete */
7776 /* If PHY's Macro operation keeps stay busy, nothing we */
7777 /* can do anyway. The timeout is there so we won't */
7778 /* stay in this routine indefinitly. */
7779 /********************************************************/
7780 static LM_UINT32 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice);
7783 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice)
7791 /* make sure the MACRO operation is complete */
7792 LM_ReadPhy(pDevice, 0x16, &val32);
7793 if ((val32 & 0x1000) == 0) break;
7796 return( timeout > 0 );
7799 /********************************************************/
7800 /* This routine resets the PHY on following chips: */
7801 /* 5703, 04, CIOB-E and 5705 */
7803 /* This routine will issue PHY_RESET and check if */
7804 /* the reset is sucessful. If not, another PHY RESET */
7805 /* will be issued, until max "retry" reaches */
7808 /* pDevice - device's context */
7809 /* retry - number of retries */
7810 /* reset - TRUE=will cause a PHY reset initially */
7811 /* FALSE = will not issue a PHY reset */
7812 /* unless TAP lockup detected */
7815 /* TRUE - PHY Reset is done sucessfully */
7816 /* FALSE - PHY Reset had failed, after "retry" */
7820 /* void LM_wait_macro_done() */
7821 /* LM_UINT32 pattern[] */
7824 /* a. Before calling this routine, caller must */
7825 /* determine if the chip is a 5702/03/04 or */
7826 /* CIOB-E, and only call this routine if the */
7827 /* is one of these. */
7828 /* or its derivatives. */
7829 /* b. Instead of using MII register write to reset */
7830 /* the PHY, call this routine instead */
7831 /* c. Upon return from this routine, check return */
7832 /* value (TRUE/FALSE) to determine if PHY reset */
7833 /* is successful of not and "optionally" take */
7834 /* appropriate action (such as: event log) */
7835 /* d. Regardless of the return TRUE or FALSE, */
7836 /* proceed with PHY setup as you normally would */
7837 /* after a PHY_RESET. */
7838 /* e. It is recommended that the caller will give */
7839 /* 10 "retry", however, caller can change to a */
7840 /* different number, depending on you code. */
7842 /********************************************************/
7843 LM_STATUS LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset);
7846 LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset)
7848 LM_UINT32 val32, save9;
7849 LM_UINT32 dataLo, dataHi;
7851 int reset_success = LM_STATUS_FAILURE;
7854 /* to actually do a PHY_RESET or not is dictated by the caller */
7855 force_reset = reset;
7857 while (retry-- && (reset_success != LM_STATUS_SUCCESS))
7861 /* issue a phy reset, and wait for reset to complete */
7862 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
7863 for(i = 0; i < 100; i++)
7867 LM_ReadPhy(pDevice, PHY_CTRL_REG, &val32);
7868 if(val32 && !(val32 & PHY_CTRL_PHY_RESET))
7875 /* no more phy reset unless lockup detected */
7876 force_reset = FALSE;
7879 /* assuming reset is successful first */
7880 reset_success = LM_STATUS_SUCCESS;
7882 /* now go check the DFE TAPs to see if locked up, but
7883 first, we need to set up PHY so we can read DFE TAPs */
7885 /* Disable Transmitter and Interrupt, while we play with
7886 the PHY registers, so the link partner won't see any
7887 strange data and the Driver won't see any interrupts. */
7888 LM_ReadPhy(pDevice, 0x10, &val32);
7889 LM_WritePhy(pDevice, 0x10, val32 | 0x3000);
7891 /* Setup Full-Duplex, 1000 mbps */
7892 LM_WritePhy(pDevice, 0x0, 0x0140);
7894 /* Set to Master mode */
7895 LM_ReadPhy(pDevice, 0x9, &save9);
7896 LM_WritePhy(pDevice, 0x9, 0x1800);
7898 /* Enable SM_DSP_CLOCK & 6dB */
7899 LM_WritePhy(pDevice, 0x18, 0x0c00);
7901 /* blocks the PHY control access */
7902 LM_WritePhy(pDevice, 0x17, 0x8005);
7903 LM_WritePhy(pDevice, 0x15, 0x0800);
7905 /* check TAPs for all 4 channels, as soon
7906 as we see a lockup we'll stop checking */
7907 for (channel=0; (channel<4) && (reset_success == LM_STATUS_SUCCESS);
7910 /* select channel and set TAP index to 0 */
7911 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
7912 /* freeze filter again just to be safe */
7913 LM_WritePhy(pDevice, 0x16, 0x0002);
7915 /* write fixed pattern to the RAM, 3 TAPs for
7916 each channel, each TAP have 2 WORDs (LO/HI) */
7918 LM_WritePhy(pDevice, 0x15, pattern[channel][i]);
7920 /* Activate PHY's Macro operation to write DFE TAP from RAM,
7921 and wait for Macro to complete */
7922 LM_WritePhy(pDevice, 0x16, 0x0202);
7923 if (!LM_wait_macro_done(pDevice))
7925 reset_success = LM_STATUS_FAILURE;
7930 /* --- done with write phase, now begin read phase --- */
7932 /* select channel and set TAP index to 0 */
7933 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
7935 /* Active PHY's Macro operation to load DFE TAP to RAM,
7936 and wait for Macro to complete */
7937 LM_WritePhy(pDevice, 0x16, 0x0082);
7938 if (!LM_wait_macro_done(pDevice))
7940 reset_success = LM_STATUS_FAILURE;
7945 /* enable "pre-fetch" */
7946 LM_WritePhy(pDevice, 0x16, 0x0802);
7947 if (!LM_wait_macro_done(pDevice))
7949 reset_success = LM_STATUS_FAILURE;
7954 /* read back the TAP values.
7955 3 TAPs for each channel, each TAP have 2 WORDs (LO/HI) */
7956 for (i=0; i<6; i+=2)
7958 /* read Lo/Hi then wait for 'done' is faster */
7959 LM_ReadPhy(pDevice, 0x15, &dataLo);
7960 LM_ReadPhy(pDevice, 0x15, &dataHi);
7961 if (!LM_wait_macro_done(pDevice))
7963 reset_success = LM_STATUS_FAILURE;
7968 /* For 5703/04, each DFE TAP has 21-bits (low word 15,
7969 * hi word 6) For 5705, each DFE TAP pas 19-bits (low word 15,
7970 * hi word 4) For simplicity, we check only 19-bits, so we
7971 * don't have to distinguish which chip it is. */
7975 /* check if what we wrote is what we read back */
7976 if ( (dataLo != pattern[channel][i]) || (dataHi != pattern[channel][i+1]) )
7978 /* if failed, then the PHY is locked up,
7979 we need to do PHY reset again */
7980 reset_success = LM_STATUS_FAILURE;
7982 /* 04/25/2003. sb. do these writes before issueing a reset. */
7983 /* these steps will reduce the chance of back-to-back
7984 * phy lockup after reset */
7985 LM_WritePhy(pDevice, 0x17, 0x000B);
7986 LM_WritePhy(pDevice, 0x15, 0x4001);
7987 LM_WritePhy(pDevice, 0x15, 0x4005);
7994 /* restore dfe coeff back to zeros */
7995 for (channel=0; channel<4 ; channel++)
7997 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
7998 LM_WritePhy(pDevice, 0x16, 0x0002);
8000 LM_WritePhy(pDevice, 0x15, 0x0000);
8001 LM_WritePhy(pDevice, 0x16, 0x0202);
8002 if (!LM_wait_macro_done(pDevice))
8004 reset_success = LM_STATUS_FAILURE;
8009 /* remove block phy control */
8010 LM_WritePhy(pDevice, 0x17, 0x8005);
8011 LM_WritePhy(pDevice, 0x15, 0x0000);
8013 /* unfreeze DFE TAP filter for all channels */
8014 LM_WritePhy(pDevice, 0x17, 0x8200);
8015 LM_WritePhy(pDevice, 0x16, 0x0000);
8017 /* Restore PHY back to operating state */
8018 LM_WritePhy(pDevice, 0x18, 0x0400);
8020 /* Restore register 9 */
8021 LM_WritePhy(pDevice, 0x9, save9);
8023 /* enable transmitter and interrupt */
8024 LM_ReadPhy(pDevice, 0x10, &val32);
8025 LM_WritePhy(pDevice, 0x10, (val32 & ~0x3000));
8027 return reset_success;
8031 LM_ResetPhy(LM_DEVICE_BLOCK *pDevice)
8036 if (pDevice->PhyFlags & PHY_CHECK_TAPS_AFTER_RESET)
8038 LM_ResetPhy_5703_4_5(pDevice, 5, 1);
8043 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8045 if( pDevice->PhyFlags & PHY_IS_FIBER )
8048 for(j = 0; j < wait_val; j++)
8052 LM_ReadPhy(pDevice, PHY_CTRL_REG, &miireg);
8053 if(miireg && !(miireg & PHY_CTRL_PHY_RESET))
8060 LM_PhyTapPowerMgmt(pDevice);
8062 if ( (pDevice->PhyFlags & PHY_ADC_FIX) &&
8063 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8065 LM_WritePhy(pDevice, 0x18, 0x0c00);
8066 LM_WritePhy(pDevice, 0x17, 0x201f);
8067 LM_WritePhy(pDevice, 0x15, 0x2aaa);
8068 LM_WritePhy(pDevice, 0x17, 0x000a);
8069 LM_WritePhy(pDevice, 0x15, 0x0323);
8070 LM_WritePhy(pDevice, 0x18, 0x0400);
8072 if ( (pDevice->PhyFlags & PHY_5705_5750_FIX) &&
8073 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8075 LM_WritePhy(pDevice, 0x18, 0x0c00);
8076 LM_WritePhy(pDevice, 0x17, 0x000a);
8077 LM_WritePhy(pDevice, 0x15, 0x310b);
8078 LM_WritePhy(pDevice, 0x17, 0x201f);
8079 LM_WritePhy(pDevice, 0x15, 0x9506);
8080 LM_WritePhy(pDevice, 0x17, 0x401f);
8081 LM_WritePhy(pDevice, 0x15, 0x14e2);
8082 LM_WritePhy(pDevice, 0x18, 0x0400);
8084 if ( (pDevice->PhyFlags & PHY_5704_A0_FIX) &&
8085 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8087 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8088 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8090 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
8092 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8093 miireg |= 1; /* set tx elastic fifo */
8094 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8096 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
8098 else if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
8100 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
8101 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &miireg);
8102 miireg |= 0x4000; /* set rx extended packet length */
8103 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, miireg);
8105 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8106 miireg |= 1; /* set tx elastic fifo */
8107 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8111 LM_SetEthWireSpeed(pDevice);
8112 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
8116 LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice)
8120 if( pDevice->PhyFlags & PHY_IS_FIBER)
8123 /* Enable Ethernet@WireSpeed. */
8124 if (pDevice->PhyFlags & PHY_ETHERNET_WIRESPEED)
8126 LM_WritePhy(pDevice, 0x18, 0x7007);
8127 LM_ReadPhy(pDevice, 0x18, &Value32);
8128 LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
8133 LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice)
8137 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &miireg);
8138 pDevice->advertising = miireg;
8139 if ((miireg & PHY_AN_AD_ALL_SPEEDS) != PHY_AN_AD_ALL_SPEEDS)
8141 return LM_STATUS_FAILURE;
8144 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &miireg);
8145 pDevice->advertising1000 = miireg;
8147 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
8149 if ((miireg & BCM540X_AN_AD_ALL_1G_SPEEDS) !=
8150 BCM540X_AN_AD_ALL_1G_SPEEDS)
8152 return LM_STATUS_FAILURE;
8158 return LM_STATUS_FAILURE;
8161 return LM_STATUS_SUCCESS;
8164 /******************************************************************************/
8168 /******************************************************************************/
8171 PLM_DEVICE_BLOCK pDevice,
8173 PLM_UINT32 pData32) {
8177 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8179 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8180 ~MI_MODE_AUTO_POLLING_ENABLE);
8181 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8185 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8186 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8187 MI_COM_CMD_READ | MI_COM_START;
8189 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8191 for(j = 0; j < 200; j++)
8195 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8197 if(!(Value32 & MI_COM_BUSY))
8200 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8201 Value32 &= MI_COM_PHY_DATA_MASK;
8206 if(Value32 & MI_COM_BUSY)
8213 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8215 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8216 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8223 /******************************************************************************/
8227 /******************************************************************************/
8230 PLM_DEVICE_BLOCK pDevice,
8236 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8238 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8239 ~MI_MODE_AUTO_POLLING_ENABLE);
8240 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8244 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8245 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8246 (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
8248 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8250 for(j = 0; j < 200; j++)
8254 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8256 if(!(Value32 & MI_COM_BUSY))
8263 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8265 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8266 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8271 /* MII read/write functions to export to the robo support code */
8273 robo_miird(void *h, int phyadd, int regoff)
8275 PLM_DEVICE_BLOCK pdev = h;
8276 LM_UINT32 savephyaddr, val32;
8278 savephyaddr = pdev->PhyAddr;
8279 pdev->PhyAddr = phyadd;
8281 LM_ReadPhy(pdev, regoff, &val32);
8283 pdev->PhyAddr = savephyaddr;
8285 return ((LM_UINT16)(val32 & 0xffff));
8289 robo_miiwr(void *h, int phyadd, int regoff, LM_UINT16 value)
8291 PLM_DEVICE_BLOCK pdev = h;
8292 LM_UINT32 val32, savephyaddr;
8294 savephyaddr = pdev->PhyAddr;
8295 pdev->PhyAddr = phyadd;
8297 val32 = (LM_UINT32)value;
8298 LM_WritePhy(pdev, regoff, val32);
8300 pdev->PhyAddr = savephyaddr;
8304 LM_GetPhyId(LM_DEVICE_BLOCK *pDevice)
8308 LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
8309 pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
8311 LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
8312 pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
8313 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
8318 LM_EnableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8320 pDevice->LoopBackMode = LM_MAC_LOOP_BACK_MODE;
8321 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
8322 pDevice->MacMode |= (MAC_MODE_PORT_INTERNAL_LOOPBACK |
8323 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII);
8324 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8326 LM_SetupPhy(pDevice);
8327 return LM_STATUS_SUCCESS;
8331 LM_DisableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8333 pDevice->LoopBackMode = 0;
8335 pDevice->MacMode &= ~(MAC_MODE_PORT_INTERNAL_LOOPBACK |
8336 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_MASK);
8337 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8339 if(pDevice->PhyFlags & PHY_IS_FIBER)
8340 LM_ResetPhy(pDevice);
8342 LM_SetupPhy(pDevice);
8343 return LM_STATUS_SUCCESS;
8347 LM_EnablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8349 pDevice->LoopBackMode = LM_PHY_LOOP_BACK_MODE;
8350 LM_SetupPhy(pDevice);
8351 return LM_STATUS_SUCCESS;
8355 LM_DisablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8357 pDevice->LoopBackMode = 0;
8358 LM_SetupPhy(pDevice);
8359 return LM_STATUS_SUCCESS;
8363 LM_EnableExtLoopBack(PLM_DEVICE_BLOCK pDevice, LM_LINE_SPEED LineSpeed)
8365 pDevice->LoopBackMode = LM_EXT_LOOP_BACK_MODE;
8367 pDevice->SavedDisableAutoNeg = pDevice->DisableAutoNeg;
8368 pDevice->SavedRequestedLineSpeed = pDevice->RequestedLineSpeed;
8369 pDevice->SavedRequestedDuplexMode = pDevice->RequestedDuplexMode;
8371 pDevice->DisableAutoNeg = TRUE;
8372 pDevice->RequestedLineSpeed = LineSpeed;
8373 pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_FULL;
8374 LM_SetupPhy(pDevice);
8375 return LM_STATUS_SUCCESS;
8379 LM_DisableExtLoopBack(PLM_DEVICE_BLOCK pDevice)
8381 pDevice->LoopBackMode = 0;
8383 pDevice->DisableAutoNeg = pDevice->SavedDisableAutoNeg;
8384 pDevice->RequestedLineSpeed = pDevice->SavedRequestedLineSpeed;
8385 pDevice->RequestedDuplexMode = pDevice->SavedRequestedDuplexMode;
8387 LM_SetupPhy(pDevice);
8388 return LM_STATUS_SUCCESS;
8391 /******************************************************************************/
8395 /******************************************************************************/
8398 PLM_DEVICE_BLOCK pDevice,
8399 LM_POWER_STATE PowerLevel)
8402 LM_UINT32 PmeSupport;
8403 PLM_DEVICE_BLOCK pDevice2 = 0;
8409 /* make sureindirect accesses are enabled*/
8410 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
8412 /* Clear the PME_ASSERT bit and the power state bits. Also enable */
8414 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
8416 PmCtrl |= T3_PM_PME_ASSERTED;
8417 PmCtrl &= ~T3_PM_POWER_STATE_MASK;
8419 /* Set the appropriate power state. */
8420 if(PowerLevel == LM_POWER_STATE_D0)
8422 /* Bring the card out of low power mode. */
8423 PmCtrl |= T3_PM_POWER_STATE_D0;
8424 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8426 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
8428 if(T3_ASIC_5752(pDevice->ChipRevId)){
8429 Value32 |= (GRC_MISC_LOCAL_CTRL_GPIO_OE3 |
8430 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 |
8431 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8432 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8433 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8434 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8435 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8436 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8440 Value32 &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8441 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8442 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8443 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8444 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8445 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8448 RAW_REG_WR(pDevice, Grc.LocalCtrl, Value32);
8450 MM_Wait(40); /* Required delay is about 20us. */
8452 pDevice->PowerLevel = PowerLevel;
8453 return LM_STATUS_SUCCESS;
8456 else if(PowerLevel == LM_POWER_STATE_D1)
8458 PmCtrl |= T3_PM_POWER_STATE_D1;
8460 else if(PowerLevel == LM_POWER_STATE_D2)
8462 PmCtrl |= T3_PM_POWER_STATE_D2;
8464 else if(PowerLevel == LM_POWER_STATE_D3)
8466 PmCtrl |= T3_PM_POWER_STATE_D3;
8470 return LM_STATUS_FAILURE;
8472 PmCtrl |= T3_PM_PME_ENABLE;
8474 /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
8475 /* setting new line speed. */
8476 Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
8477 REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
8479 if(!pDevice->RestoreOnWakeUp)
8481 pDevice->RestoreOnWakeUp = TRUE;
8482 pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
8483 pDevice->WakeUpRequestedLineSpeed = pDevice->RequestedLineSpeed;
8484 pDevice->WakeUpRequestedDuplexMode = pDevice->RequestedDuplexMode;
8487 /* Force auto-negotiation to 10 line speed. */
8488 pDevice->DisableAutoNeg = FALSE;
8490 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8492 pDevice->RequestedLineSpeed = LM_LINE_SPEED_10MBPS;
8493 LM_SetupPhy(pDevice);
8496 /* Put the driver in the initial state, and go through the power down */
8500 if (!(pDevice->AsfFlags & ASF_ENABLED))
8502 for(j = 0; j < 20000; j++)
8506 Value32 = MEM_RD_OFFSET(pDevice, T3_ASF_FW_STATUS_MAILBOX);
8507 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE)
8514 MEM_WR_OFFSET(pDevice, DRV_WOL_MAILBOX, DRV_WOL_SIGNATURE |
8515 DRV_DOWN_STATE_SHUTDOWN | 0x2 | DRV_WOL_SET_MAGIC_PKT);
8517 MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
8519 if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
8523 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8525 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
8529 if (! T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
8531 /* Let boot code deal with LED mode on shasta */
8532 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
8535 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8537 Value32 = MAC_MODE_PORT_MODE_TBI;
8541 Value32 = MAC_MODE_PORT_MODE_MII;
8542 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
8544 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_2 ||
8545 pDevice->WolSpeed == WOL_SPEED_10MB)
8547 Value32 |= MAC_MODE_LINK_POLARITY;
8552 Value32 |= MAC_MODE_LINK_POLARITY;
8555 REG_WR(pDevice, MacCtrl.Mode, Value32);
8556 REG_RD_BACK(pDevice, MacCtrl.Mode);
8557 MM_Wait(40); MM_Wait(40); MM_Wait(40);
8559 /* Always enable magic packet wake-up if we have vaux. */
8560 if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
8561 (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
8563 Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
8567 if (pDevice->AsfFlags & ASF_ENABLED)
8569 Value32 &= ~MAC_MODE_ACPI_POWER_ON_ENABLE;
8572 REG_WR(pDevice, MacCtrl.Mode, Value32);
8574 /* Enable the receiver. */
8575 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
8577 else if (!(pDevice->AsfFlags & ASF_ENABLED))
8579 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8581 REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
8582 LED_CTRL_OVERRIDE_TRAFFIC_LED);
8586 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
8587 BCM540X_EXT_CTRL_FORCE_LED_OFF);
8588 LM_WritePhy(pDevice, 0x18, 0x01b2);
8589 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8590 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
8591 !T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8593 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOWER_POWER_MODE);
8598 /* Disable tx/rx clocks, and select an alternate clock. */
8599 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
8602 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
8603 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
8604 (pDevice->WolSpeed == WOL_SPEED_10MB)))
8606 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8607 T3_PCI_SELECT_ALTERNATE_CLOCK |
8608 T3_PCI_POWER_DOWN_PCI_PLL133;
8610 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8612 /* ASF on 5750 will not run properly on slow core clock */
8613 else if( !(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) &&
8614 (pDevice->AsfFlags & ASF_ENABLED) ))
8616 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8618 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8619 T3_PCI_SELECT_ALTERNATE_CLOCK;
8621 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8623 Value32 = T3_PCI_625_CORE_CLOCK;
8627 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
8629 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8633 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8634 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8636 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8637 T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8639 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8641 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_625_CORE_CLOCK;
8643 else if(!T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8645 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8648 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8650 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8654 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8655 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8657 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8658 T3_PCI_44MHZ_CORE_CLOCK;
8662 Value32 = T3_PCI_44MHZ_CORE_CLOCK;
8665 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8671 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
8673 pDevice2 = MM_FindPeerDev(pDevice);
8675 if (!(pDevice->Flags & EEPROM_WP_FLAG))
8677 LM_SwitchVaux(pDevice, pDevice2);
8680 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8682 if((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_AX) ||
8683 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_BX)) {
8685 Value32= REG_RD_OFFSET(pDevice, 0x7d00);
8686 REG_WR_OFFSET(pDevice, 0x7d00,Value32 & ~(BIT_16 | BIT_4 | BIT_2 | BIT_1 | BIT_0));
8688 if(!(pDevice->AsfFlags & ASF_ENABLED))
8689 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
8693 /* Put the the hardware in low power mode. */
8694 if (!(pDevice->Flags & DISABLE_D3HOT_FLAG))
8696 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8697 MM_Wait(200); /* Wait 200us for state transition */
8700 pDevice->PowerLevel = PowerLevel;
8703 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8704 #endif /* BCM_WOL */
8706 return LM_STATUS_SUCCESS;
8707 } /* LM_SetPowerState */
8711 LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2)
8713 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8716 pDevice->GrcLocalCtrl &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8717 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8718 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8719 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8720 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8721 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8723 /* Switch adapter to auxilliary power if WOL enabled */
8724 if ((pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
8725 (pDevice->AsfFlags & ASF_ENABLED) ||
8726 (pDevice2 && ((pDevice2->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
8727 (pDevice2->AsfFlags & ASF_ENABLED))))
8729 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8730 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8732 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
8733 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8734 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8735 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8736 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8737 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8738 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8743 if (pDevice2 && pDevice2->InitDone)
8748 /* On NICs GPIOs are used for vaux.
8749 The transition of GPIO0 from 0-1 causes vaux
8750 to power up. Transition of GPIO1 from 1-0 turns vaux off.
8751 GPIO2 transition from 1-0 enables a non-glitch vaux
8752 transition from one state to another.
8753 On certain designs we should not output GPIO2.
8755 if(pDevice->Flags & GPIO2_DONOT_OUTPUT)
8757 /* GPIO0 = 0, GPIO1 = 1. */
8758 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8759 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8760 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8761 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8765 /* GPIO0 = 1, GPIO1 = 1. */
8766 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8767 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8768 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8769 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8770 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8777 /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
8778 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8779 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8780 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8781 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8782 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8783 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8787 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
8788 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8789 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8790 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8791 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8792 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8793 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8794 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8797 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
8798 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8799 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8800 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8801 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8802 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8803 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8806 } /* Not 5700||5701 */
8807 } /* WOL disabled */
8810 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8811 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
8813 if (pDevice2 && pDevice2->InitDone)
8819 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8820 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8821 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8825 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8826 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
8830 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8831 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8832 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8839 /******************************************************************************/
8843 /******************************************************************************/
8845 GetPhyAdFlowCntrlSettings(
8846 PLM_DEVICE_BLOCK pDevice)
8852 /* Auto negotiation flow control only when autonegotiation is enabled. */
8853 if(pDevice->DisableAutoNeg == FALSE ||
8854 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
8856 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
8857 (pDevice->PhyFlags & PHY_IS_FIBER)) {
8859 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
8860 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
8861 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
8862 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
8864 Value32 |=PHY_AN_AD_1000XPAUSE;
8866 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
8868 Value32 |= PHY_AN_AD_1000XPSE_ASYM;
8870 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
8872 Value32 |= (PHY_AN_AD_1000XPSE_ASYM | PHY_AN_AD_1000XPAUSE);
8877 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
8878 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
8879 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
8880 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
8882 Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
8884 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
8886 Value32 |= PHY_AN_AD_ASYM_PAUSE;
8888 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
8890 Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
8900 /******************************************************************************/
8904 /* LM_STATUS_FAILURE */
8905 /* LM_STATUS_SUCCESS */
8907 /******************************************************************************/
8909 LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice)
8911 LM_LINE_SPEED LineSpeed;
8912 LM_DUPLEX_MODE DuplexMode;
8913 LM_UINT32 NewPhyCtrl;
8914 LM_UINT32 Value32, PhyReg18;
8917 /* Get the interface type, line speed, and duplex mode. */
8918 LineSpeed = pDevice->RequestedLineSpeed;
8919 DuplexMode = pDevice->RequestedDuplexMode;
8921 /* Exit ext. loop back, in case it was in ext. loopback mode */
8922 /* Set Extended packet length bit on chips that support jumbo frames */
8923 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
8925 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
8927 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
8928 Value32 |= 1; /* set tx elastic fifo */
8929 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
8934 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
8935 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
8936 PhyReg18 &= ~0x8000; /* clear external loop back */
8938 if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
8940 PhyReg18 |= 0x4000; /* set extended packet length */
8941 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
8942 Value32 |= 1; /* set tx elastic fifo */
8943 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
8945 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
8949 if (pDevice->RestoreOnWakeUp)
8951 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
8952 pDevice->advertising1000 = 0;
8953 Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
8954 if (pDevice->WolSpeed == WOL_SPEED_100MB)
8956 Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
8958 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
8959 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
8960 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
8961 pDevice->advertising = Value32;
8963 /* Setup the auto-negotiation advertisement register. */
8964 else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
8966 /* Setup the auto-negotiation advertisement register. */
8967 if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
8970 /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
8971 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | PHY_AN_AD_ALL_SPEEDS;
8972 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
8974 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
8975 pDevice->advertising = Value32;
8977 /* Advertise 1000Mbps */
8978 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
8980 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS;
8982 #ifdef INCLUDE_5701_AX_FIX
8983 /* slave mode. This will force the PHY to operate in */
8985 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
8986 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
8988 Value32 |= BCM540X_CONFIG_AS_MASTER |
8989 BCM540X_ENABLE_CONFIG_AS_MASTER;
8993 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
8994 pDevice->advertising1000 = Value32;
8998 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
8999 pDevice->advertising1000 = 0;
9004 if ((pDevice->PhyFlags & PHY_NO_GIGABIT) &&
9005 (LineSpeed == LM_LINE_SPEED_1000MBPS))
9007 LineSpeed = LM_LINE_SPEED_100MBPS;
9009 if(LineSpeed == LM_LINE_SPEED_1000MBPS)
9011 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9012 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9014 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9015 pDevice->advertising = Value32;
9017 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9019 Value32 = BCM540X_AN_AD_1000BASET_HALF;
9023 Value32 = BCM540X_AN_AD_1000BASET_FULL;
9026 #ifdef INCLUDE_5701_AX_FIX
9027 if ((pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE) ||
9028 (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9029 pDevice->ChipRevId == T3_CHIP_ID_5701_B0))
9031 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9034 Value32 |= BCM540X_CONFIG_AS_MASTER |
9035 BCM540X_ENABLE_CONFIG_AS_MASTER;
9037 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9038 pDevice->advertising1000 = Value32;
9039 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9041 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9043 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x8c20);
9047 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9048 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9049 PhyReg18 |= 0x8000; /* set loop back */
9050 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9054 else if(LineSpeed == LM_LINE_SPEED_100MBPS)
9056 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9057 pDevice->advertising1000 = 0;
9059 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9061 Value32 = PHY_AN_AD_100BASETX_HALF;
9065 Value32 = PHY_AN_AD_100BASETX_FULL;
9068 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9069 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9071 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9072 pDevice->advertising = Value32;
9074 else if(LineSpeed == LM_LINE_SPEED_10MBPS)
9076 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9077 pDevice->advertising1000 = 0;
9079 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9081 Value32 = PHY_AN_AD_10BASET_HALF;
9085 Value32 = PHY_AN_AD_10BASET_FULL;
9088 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9089 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9091 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9092 pDevice->advertising = Value32;
9096 /* Force line speed if auto-negotiation is disabled. */
9097 if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
9099 /* This code path is executed only when there is link. */
9100 pDevice->LineSpeed = LineSpeed;
9101 pDevice->DuplexMode = DuplexMode;
9103 /* Force line seepd. */
9107 case LM_LINE_SPEED_10MBPS:
9108 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
9110 case LM_LINE_SPEED_100MBPS:
9111 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
9113 case LM_LINE_SPEED_1000MBPS:
9114 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9117 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9121 if(DuplexMode == LM_DUPLEX_MODE_FULL)
9123 NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
9126 /* Don't do anything if the PHY_CTRL is already what we wanted. */
9127 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
9128 if(Value32 != NewPhyCtrl)
9130 /* Temporary bring the link down before forcing line speed. */
9131 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
9133 /* Wait for link to go down. */
9134 for(Cnt = 0; Cnt < 1500; Cnt++)
9138 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9139 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9141 if(!(Value32 & PHY_STATUS_LINK_PASS))
9148 LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
9154 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
9155 PHY_CTRL_RESTART_AUTO_NEG);
9158 return LM_STATUS_SUCCESS;
9159 } /* LM_ForceAutoNegBcm540xPhy */
9161 /******************************************************************************/
9165 /******************************************************************************/
9166 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
9167 PT3_FWIMG_INFO pFwImg,
9173 LM_VOID (*Wr_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register,LM_UINT32 Value32);
9174 LM_UINT32 (*Rd_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register);
9176 LM_UINT32 base_addr;
9178 /* BCM4785: Avoid all use of firmware. */
9179 if (pDevice->Flags & SB_CORE_FLAG)
9180 return LM_STATUS_FAILURE;
9182 #ifdef INCLUDE_TCP_SEG_SUPPORT
9183 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
9185 Wr_fn = LM_MemWrInd;
9186 Rd_fn = LM_MemRdInd;
9187 len = LM_GetStkOffLdFirmwareSize(pDevice);
9188 base_addr = T3_NIC_BCM5705_MBUF_POOL_ADDR;
9193 Wr_fn = LM_RegWrInd;
9194 Rd_fn = LM_RegRdInd;
9195 len = T3_RX_CPU_SPAD_SIZE;
9196 base_addr = T3_RX_CPU_SPAD_ADDR;
9199 if (LoadCpu & T3_RX_CPU_ID)
9201 if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
9203 return LM_STATUS_FAILURE;
9206 /* First of all clear scrach pad memory */
9207 for (i = 0; i < len; i+=4)
9209 Wr_fn(pDevice,base_addr+i,0);
9212 /* Copy code first */
9213 address = base_addr + (pFwImg->Text.Offset & 0xffff);
9214 for (i = 0; i <= pFwImg->Text.Length; i+=4)
9216 Wr_fn(pDevice,address+i,
9217 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9220 address = base_addr + (pFwImg->ROnlyData.Offset & 0xffff);
9221 for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
9223 Wr_fn(pDevice,address+i,
9224 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9227 address = base_addr + (pFwImg->Data.Offset & 0xffff);
9228 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9230 Wr_fn(pDevice,address+i,
9231 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9235 if ((LoadCpu & T3_TX_CPU_ID) &&
9236 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9238 if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
9240 return LM_STATUS_FAILURE;
9243 /* First of all clear scrach pad memory */
9244 for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
9246 Wr_fn(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
9249 /* Copy code first */
9250 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
9251 for (i= 0; i <= pFwImg->Text.Length; i+=4)
9253 Wr_fn(pDevice,address+i,
9254 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9257 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
9258 for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
9260 Wr_fn(pDevice,address+i,
9261 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9264 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
9265 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9267 Wr_fn(pDevice,address+i,
9268 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9272 if (StartCpu & T3_RX_CPU_ID)
9275 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9276 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9277 for (i = 0 ; i < 5; i++)
9279 if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
9282 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9283 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9284 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9285 REG_RD_BACK(pDevice,rxCpu.reg.PC);
9289 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9290 REG_WR(pDevice,rxCpu.reg.mode, 0);
9293 if ((StartCpu & T3_TX_CPU_ID) &&
9294 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9297 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9298 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9299 for (i = 0 ; i < 5; i++)
9301 if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
9304 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9305 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9306 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9307 REG_RD_BACK(pDevice,txCpu.reg.PC);
9311 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9312 REG_WR(pDevice,txCpu.reg.mode, 0);
9315 return LM_STATUS_SUCCESS;
9318 LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
9323 status = LM_STATUS_SUCCESS;
9325 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) &&
9326 !(cpu_number & T3_RX_CPU_ID))
9331 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9332 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9334 status = LM_NVRAM_AcquireLock(pDevice);
9337 if (cpu_number & T3_RX_CPU_ID)
9339 for (i = 0 ; i < 10000; i++)
9341 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9342 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9344 if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
9348 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9349 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9350 REG_RD_BACK(pDevice,rxCpu.reg.mode);
9354 status = LM_STATUS_FAILURE;
9358 * BCM4785: There is only an Rx CPU for the 5750 derivative in
9359 * the 4785. Don't go any further in this code in order to
9360 * avoid access to the NVRAM arbitration register.
9362 if (pDevice->Flags & SB_CORE_FLAG)
9365 if ((pDevice->Flags & T3_HAS_TWO_CPUS) &&
9366 (cpu_number & T3_TX_CPU_ID))
9368 for (i = 0 ; i < 10000; i++)
9370 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9371 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9373 if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
9378 status = LM_STATUS_FAILURE;
9381 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9382 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9384 if (status != LM_STATUS_SUCCESS)
9387 * Some part of this operation failed.
9388 * Just undo our own actions.
9390 LM_NVRAM_ReleaseLock(pDevice);
9392 else if (!(pDevice->Flags & T3_HAS_TWO_CPUS) ||
9393 cpu_number == (T3_TX_CPU_ID | T3_RX_CPU_ID))
9396 * Release our NVRAM arbitration grant along
9397 * with the firmware's arbitration request bit.
9399 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9400 REG_RD_BACK(pDevice, Nvram.SwArb);
9404 LM_NVRAM_ReleaseLock(pDevice);
9406 if (LM_NVRAM_AcquireLock(pDevice) == LM_STATUS_SUCCESS)
9408 /* All is well. Release the arbitration and continue. */
9409 LM_NVRAM_ReleaseLock(pDevice);
9414 * We've timed out while attempting to get the
9415 * NVRAM arbitration. Assume the cause is that
9416 * the NVRAM has requested arbitration after we
9417 * acquired arbitration the first time, but before
9418 * the CPU was actually halted.
9422 * Release our NVRAM arbitration grant along
9423 * with the firmware's arbitration request bit.
9425 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9426 REG_RD_BACK(pDevice, Nvram.SwArb);
9436 LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
9439 int ret = LM_STATUS_SUCCESS;
9441 if(BlinkDurationSec == 0)
9443 BlinkDurationSec = 1;
9445 if(BlinkDurationSec > 120)
9447 BlinkDurationSec = 120;
9450 for(j = 0; j < BlinkDurationSec * 2; j++)
9454 // Turn on the LEDs.
9455 REG_WR(pDevice, MacCtrl.LedCtrl,
9456 LED_CTRL_OVERRIDE_LINK_LED |
9457 LED_CTRL_1000MBPS_LED_ON |
9458 LED_CTRL_100MBPS_LED_ON |
9459 LED_CTRL_10MBPS_LED_ON |
9460 LED_CTRL_OVERRIDE_TRAFFIC_LED |
9461 LED_CTRL_BLINK_TRAFFIC_LED |
9462 LED_CTRL_TRAFFIC_LED);
9466 // Turn off the LEDs.
9467 REG_WR(pDevice, MacCtrl.LedCtrl,
9468 LED_CTRL_OVERRIDE_LINK_LED |
9469 LED_CTRL_OVERRIDE_TRAFFIC_LED);
9471 if (MM_Sleep(pDevice, 500) != LM_STATUS_SUCCESS)/* 0.5 second */
9473 ret = LM_STATUS_FAILURE;
9477 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
9482 LM_SwitchClocks(PLM_DEVICE_BLOCK pDevice)
9484 LM_UINT32 ClockCtrl;
9486 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9487 return LM_STATUS_SUCCESS;
9489 ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl);
9490 pDevice->ClockCtrl = ClockCtrl & (T3_PCI_FORCE_CLKRUN |
9491 T3_PCI_CLKRUN_OUTPUT_EN | 0x1f);
9492 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9494 if (ClockCtrl & T3_PCI_625_CORE_CLOCK)
9496 /* clear ALT clock first */
9497 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9498 T3_PCI_625_CORE_CLOCK);
9499 MM_Wait(40); /* required delay is 27usec */
9504 if (ClockCtrl & T3_PCI_44MHZ_CORE_CLOCK)
9506 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9507 T3_PCI_44MHZ_CORE_CLOCK | T3_PCI_SELECT_ALTERNATE_CLOCK);
9508 MM_Wait(40); /* required delay is 27usec */
9509 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9510 T3_PCI_SELECT_ALTERNATE_CLOCK);
9511 MM_Wait(40); /* required delay is 27usec */
9515 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
9516 MM_Wait(40); /* required delay is 27usec */
9517 return LM_STATUS_SUCCESS;
9520 int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
9521 LM_PHYSICAL_ADDRESS host_addr_phy, int length,
9524 T3_DMA_DESC dma_desc;
9526 LM_UINT32 dma_desc_addr;
9529 REG_WR(pDevice, BufMgr.Mode, 0);
9530 REG_WR(pDevice, Ftq.Reset, 0);
9532 dma_desc.host_addr.High = host_addr_phy.High;
9533 dma_desc.host_addr.Low = host_addr_phy.Low;
9534 dma_desc.nic_mbuf = 0x2100;
9535 dma_desc.len = length;
9536 dma_desc.flags = 0x00000005; /* Generate Rx-CPU event */
9540 dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
9541 T3_QID_DMA_HIGH_PRI_READ;
9542 REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
9546 dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
9547 T3_QID_DMA_HIGH_PRI_WRITE;
9548 REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
9551 dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
9553 /* Writing this DMA descriptor to DMA memory */
9554 for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
9556 value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
9557 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
9558 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG,
9559 MM_SWAP_LE32(value32));
9561 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
9564 REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
9566 REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
9568 for (i = 0; i < 40; i++)
9571 value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
9573 value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
9575 if ((value32 & 0xffff) == dma_desc_addr)
9581 return LM_STATUS_SUCCESS;
9585 LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
9586 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
9590 int dma_success = 0;
9591 LM_STATUS ret = LM_STATUS_FAILURE;
9593 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
9594 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
9596 return LM_STATUS_SUCCESS;
9598 while (!dma_success)
9600 /* Fill data with incremental patterns */
9601 ptr = (LM_UINT32 *)pBufferVirt;
9602 for (j = 0; j < BufferSize/4; j++)
9605 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
9607 goto LM_DmaTestDone;
9611 ptr = (LM_UINT32 *)pBufferVirt;
9612 /* Fill data with zero */
9613 for (j = 0; j < BufferSize/4; j++)
9616 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
9618 goto LM_DmaTestDone;
9622 /* Check for data */
9623 ptr = (LM_UINT32 *)pBufferVirt;
9624 for (j = 0; j < BufferSize/4; j++)
9628 if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
9629 != DMA_CTRL_WRITE_BOUNDARY_16)
9631 pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
9632 ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
9633 DMA_CTRL_WRITE_BOUNDARY_16;
9634 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
9635 pDevice->DmaReadWriteCtrl);
9640 goto LM_DmaTestDone;
9644 if (j == (BufferSize/4))
9647 ret = LM_STATUS_SUCCESS;
9649 memset(pBufferVirt, 0, BufferSize);
9654 LM_Add32To64Counter(LM_UINT32 Counter32, T3_64BIT_REGISTER *Counter64)
9656 Counter64->Low += Counter32;
9657 if (Counter64->Low < Counter32)
9664 LM_GetStats(PLM_DEVICE_BLOCK pDevice)
9666 PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt;
9668 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9670 return LM_STATUS_FAILURE;
9675 return LM_STATUS_FAILURE;
9677 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutOctets),
9678 &pStats->ifHCOutOctets);
9679 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsCollisions),
9680 &pStats->etherStatsCollisions);
9681 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXonSent),
9682 &pStats->outXonSent);
9683 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXoffSent),
9684 &pStats->outXoffSent);
9685 LM_Add32To64Counter(REG_RD(pDevice,
9686 MacCtrl.dot3StatsInternalMacTransmitErrors),
9687 &pStats->dot3StatsInternalMacTransmitErrors);
9688 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsSingleCollisionFrames),
9689 &pStats->dot3StatsSingleCollisionFrames);
9690 LM_Add32To64Counter(REG_RD(pDevice,
9691 MacCtrl.dot3StatsMultipleCollisionFrames),
9692 &pStats->dot3StatsMultipleCollisionFrames);
9693 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsDeferredTransmissions),
9694 &pStats->dot3StatsDeferredTransmissions);
9695 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsExcessiveCollisions),
9696 &pStats->dot3StatsExcessiveCollisions);
9697 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsLateCollisions),
9698 &pStats->dot3StatsLateCollisions);
9699 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutUcastPkts),
9700 &pStats->ifHCOutUcastPkts);
9701 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutMulticastPkts),
9702 &pStats->ifHCOutMulticastPkts);
9703 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutBroadcastPkts),
9704 &pStats->ifHCOutBroadcastPkts);
9705 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInOctets),
9706 &pStats->ifHCInOctets);
9707 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsFragments),
9708 &pStats->etherStatsFragments);
9709 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInUcastPkts),
9710 &pStats->ifHCInUcastPkts);
9711 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInMulticastPkts),
9712 &pStats->ifHCInMulticastPkts);
9713 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInBroadcastPkts),
9714 &pStats->ifHCInBroadcastPkts);
9715 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFCSErrors),
9716 &pStats->dot3StatsFCSErrors);
9717 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsAlignmentErrors),
9718 &pStats->dot3StatsAlignmentErrors);
9719 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xonPauseFramesReceived),
9720 &pStats->xonPauseFramesReceived);
9721 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffPauseFramesReceived),
9722 &pStats->xoffPauseFramesReceived);
9723 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.macControlFramesReceived),
9724 &pStats->macControlFramesReceived);
9725 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffStateEntered),
9726 &pStats->xoffStateEntered);
9727 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFramesTooLong),
9728 &pStats->dot3StatsFramesTooLong);
9729 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsJabbers),
9730 &pStats->etherStatsJabbers);
9731 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsUndersizePkts),
9732 &pStats->etherStatsUndersizePkts);
9734 return LM_STATUS_SUCCESS;