2 * Broadcom BCM5325E/536x switch configuration module
4 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * Broadcom 53xx RoboSwitch device driver.
19 * Copyright 2007, Broadcom Corporation
20 * All Rights Reserved.
22 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
24 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
25 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
29 #include <linux/autoconf.h>
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <asm/uaccess.h>
38 #include <bcmendian.h>
39 #include "bcmparams.h"
43 #include "proto/ethernet.h"
44 #include <switch-core.h>
46 #define DRIVER_NAME "bcm57xx"
47 #define DRIVER_VERSION "0.1"
49 #ifndef GPIO_PIN_NOTDEFINED
50 #define GPIO_PIN_NOTDEFINED 0x20
54 #define ET_ERROR(args) printk args
56 #define ET_ERROR(args)
61 * Switch can be programmed through SPI interface, which
62 * has a rreg and a wreg functions to read from and write to
66 /* MII access registers */
67 #define PSEUDO_PHYAD 0x1E /* MII Pseudo PHY address */
68 #define REG_MII_PAGE 0x10 /* MII Page register */
69 #define REG_MII_ADDR 0x11 /* MII Address register */
70 #define REG_MII_DATA0 0x18 /* MII Data register 0 */
71 #define REG_MII_DATA1 0x19 /* MII Data register 1 */
72 #define REG_MII_DATA2 0x1a /* MII Data register 2 */
73 #define REG_MII_DATA3 0x1b /* MII Data register 3 */
76 #define PAGE_CTRL 0x00 /* Control page */
77 #define PAGE_MMR 0x02 /* 5397 Management/Mirroring page */
78 #define PAGE_VTBL 0x05 /* ARL/VLAN Table access page */
79 #define PAGE_VLAN 0x34 /* VLAN page */
81 /* Control page registers */
82 #define REG_CTRL_PORT0 0x00 /* Port 0 traffic control register */
83 #define REG_CTRL_PORT1 0x01 /* Port 1 traffic control register */
84 #define REG_CTRL_PORT2 0x02 /* Port 2 traffic control register */
85 #define REG_CTRL_PORT3 0x03 /* Port 3 traffic control register */
86 #define REG_CTRL_PORT4 0x04 /* Port 4 traffic control register */
87 #define REG_CTRL_PORT5 0x05 /* Port 5 traffic control register */
88 #define REG_CTRL_PORT6 0x06 /* Port 6 traffic control register */
89 #define REG_CTRL_PORT7 0x07 /* Port 7 traffic control register */
90 #define REG_CTRL_MODE 0x0B /* Switch Mode register */
91 #define REG_CTRL_MIIPO 0x0E /* 5325: MII Port Override register */
92 #define REG_CTRL_SRST 0x79 /* Software reset control register */
94 #define REG_DEVICE_ID 0x30 /* 539x Device id: */
95 #define DEVID5325 0x25 /* 5325 (Not really be we fake it) */
96 #define DEVID5395 0x95 /* 5395 */
97 #define DEVID5397 0x97 /* 5397 */
98 #define DEVID5398 0x98 /* 5398 */
100 /* VLAN page registers */
101 #define REG_VLAN_CTRL0 0x00 /* VLAN Control 0 register */
102 #define REG_VLAN_CTRL1 0x01 /* VLAN Control 1 register */
103 #define REG_VLAN_CTRL4 0x04 /* VLAN Control 4 register */
104 #define REG_VLAN_CTRL5 0x05 /* VLAN Control 5 register */
105 #define REG_VLAN_ACCESS 0x06 /* VLAN Table Access register */
106 #define REG_VLAN_WRITE 0x08 /* VLAN Write register */
107 #define REG_VLAN_READ 0x0C /* VLAN Read register */
108 #define REG_VLAN_PTAG0 0x10 /* VLAN Default Port Tag register - port 0 */
109 #define REG_VLAN_PTAG1 0x12 /* VLAN Default Port Tag register - port 1 */
110 #define REG_VLAN_PTAG2 0x14 /* VLAN Default Port Tag register - port 2 */
111 #define REG_VLAN_PTAG3 0x16 /* VLAN Default Port Tag register - port 3 */
112 #define REG_VLAN_PTAG4 0x18 /* VLAN Default Port Tag register - port 4 */
113 #define REG_VLAN_PTAG5 0x1a /* VLAN Default Port Tag register - port 5 */
114 #define REG_VLAN_PTAG6 0x1c /* VLAN Default Port Tag register - port 6 */
115 #define REG_VLAN_PTAG7 0x1e /* VLAN Default Port Tag register - port 7 */
116 #define REG_VLAN_PTAG8 0x20 /* 539x: VLAN Default Port Tag register - IMP port */
117 #define REG_VLAN_PMAP 0x20 /* 5325: VLAN Priority Re-map register */
119 #define VLAN_NUMVLANS 16 /* # of VLANs */
122 /* ARL/VLAN Table Access page registers */
123 #define REG_VTBL_CTRL 0x00 /* ARL Read/Write Control */
124 #define REG_VTBL_MINDX 0x02 /* MAC Address Index */
125 #define REG_VTBL_VINDX 0x08 /* VID Table Index */
126 #define REG_VTBL_ARL_E0 0x10 /* ARL Entry 0 */
127 #define REG_VTBL_ARL_E1 0x18 /* ARL Entry 1 */
128 #define REG_VTBL_DAT_E0 0x18 /* ARL Table Data Entry 0 */
129 #define REG_VTBL_SCTRL 0x20 /* ARL Search Control */
130 #define REG_VTBL_SADDR 0x22 /* ARL Search Address */
131 #define REG_VTBL_SRES 0x24 /* ARL Search Result */
132 #define REG_VTBL_SREXT 0x2c /* ARL Search Result */
133 #define REG_VTBL_VID_E0 0x30 /* VID Entry 0 */
134 #define REG_VTBL_VID_E1 0x32 /* VID Entry 1 */
135 #define REG_VTBL_PREG 0xFF /* Page Register */
136 #define REG_VTBL_ACCESS 0x60 /* VLAN table access register */
137 #define REG_VTBL_INDX 0x61 /* VLAN table address index register */
138 #define REG_VTBL_ENTRY 0x63 /* VLAN table entry register */
139 #define REG_VTBL_ACCESS_5395 0x80 /* VLAN table access register */
140 #define REG_VTBL_INDX_5395 0x81 /* VLAN table address index register */
141 #define REG_VTBL_ENTRY_5395 0x83 /* VLAN table entry register */
144 #define REG_SPI_PAGE 0xff /* SPI Page register */
146 /* Access switch registers through GPIO/SPI */
148 /* Minimum timing constants */
149 #define SCK_EDGE_TIME 2 /* clock edge duration - 2us */
150 #define MOSI_SETUP_TIME 1 /* input setup duration - 1us */
151 #define SS_SETUP_TIME 1 /* select setup duration - 1us */
153 /* misc. constants */
154 #define SPI_MAX_RETRY 100
156 static int config_attach(robo_info_t *robo);
157 static void config_detach(robo_info_t *robo);
159 /* Enable GPIO access to the chip */
161 gpio_enable(robo_info_t *robo)
163 /* Enable GPIO outputs with SCK and MOSI low, SS high */
164 sb_gpioout(robo->sbh, robo->ss | robo->sck | robo->mosi, robo->ss, GPIO_DRV_PRIORITY);
165 sb_gpioouten(robo->sbh, robo->ss | robo->sck | robo->mosi,
166 robo->ss | robo->sck | robo->mosi, GPIO_DRV_PRIORITY);
169 /* Disable GPIO access to the chip */
171 gpio_disable(robo_info_t *robo)
173 /* Disable GPIO outputs with all their current values */
174 sb_gpioouten(robo->sbh, robo->ss | robo->sck | robo->mosi, 0, GPIO_DRV_PRIORITY);
177 /* Write a byte stream to the chip thru SPI */
179 spi_write(robo_info_t *robo, uint8 *buf, uint len)
184 /* Byte bang from LSB to MSB */
185 for (i = 0; i < len; i++) {
186 /* Bit bang from MSB to LSB */
187 for (mask = 0x80; mask; mask >>= 1) {
189 sb_gpioout(robo->sbh, robo->sck, 0, GPIO_DRV_PRIORITY);
190 OSL_DELAY(SCK_EDGE_TIME);
192 /* Sample on rising edge */
194 sb_gpioout(robo->sbh, robo->mosi, robo->mosi, GPIO_DRV_PRIORITY);
196 sb_gpioout(robo->sbh, robo->mosi, 0, GPIO_DRV_PRIORITY);
197 OSL_DELAY(MOSI_SETUP_TIME);
200 sb_gpioout(robo->sbh, robo->sck, robo->sck, GPIO_DRV_PRIORITY);
201 OSL_DELAY(SCK_EDGE_TIME);
208 /* Read a byte stream from the chip thru SPI */
210 spi_read(robo_info_t *robo, uint8 *buf, uint len)
213 uint8 rack, mask, byte;
215 /* Timeout after 100 tries without RACK */
216 for (i = 0, rack = 0, timeout = SPI_MAX_RETRY; i < len && timeout;) {
217 /* Bit bang from MSB to LSB */
218 for (mask = 0x80, byte = 0; mask; mask >>= 1) {
220 sb_gpioout(robo->sbh, robo->sck, 0, GPIO_DRV_PRIORITY);
221 OSL_DELAY(SCK_EDGE_TIME);
223 /* Sample on falling edge */
224 if (sb_gpioin(robo->sbh) & robo->miso)
228 sb_gpioout(robo->sbh, robo->sck, robo->sck, GPIO_DRV_PRIORITY);
229 OSL_DELAY(SCK_EDGE_TIME);
231 /* RACK when bit 0 is high */
237 /* Byte bang from LSB to MSB */
243 ET_ERROR(("spi_read: timeout"));
250 /* Enable/disable SPI access */
252 spi_select(robo_info_t *robo, uint8 spi)
255 /* Enable SPI access */
256 sb_gpioout(robo->sbh, robo->ss, 0, GPIO_DRV_PRIORITY);
258 /* Disable SPI access */
259 sb_gpioout(robo->sbh, robo->ss, robo->ss, GPIO_DRV_PRIORITY);
261 OSL_DELAY(SS_SETUP_TIME);
265 /* Select chip and page */
267 spi_goto(robo_info_t *robo, uint8 page)
269 uint8 reg8 = REG_SPI_PAGE; /* page select register */
272 /* Issue the command only when we are on a different page */
273 if (robo->page == page)
278 /* Enable SPI access */
281 /* Select new page with CID 0 */
282 cmd8 = ((6 << 4) | /* normal SPI */
284 spi_write(robo, &cmd8, 1);
285 spi_write(robo, ®8, 1);
286 spi_write(robo, &page, 1);
288 /* Disable SPI access */
292 /* Write register thru SPI */
294 spi_wreg(robo_info_t *robo, uint8 page, uint8 addr, void *val, int len)
304 /* validate value length and buffer address */
305 ASSERT(len == 1 || (len == 2 && !((int)val & 1)) ||
306 (len == 4 && !((int)val & 3)));
308 /* Select chip and page */
309 spi_goto(robo, page);
311 /* Enable SPI access */
314 /* Write with CID 0 */
315 cmd8 = ((6 << 4) | /* normal SPI */
317 spi_write(robo, &cmd8, 1);
318 spi_write(robo, &addr, 1);
321 bytes.val8 = *(uint8 *)val;
324 bytes.val16 = htol16(*(uint16 *)val);
327 bytes.val32 = htol32(*(uint32 *)val);
330 spi_write(robo, (uint8 *)val, len);
332 ET_MSG(("%s: [0x%x-0x%x] := 0x%x (len %d)\n", __FUNCTION__, page, addr,
333 *(uint16 *)val, len));
334 /* Disable SPI access */
339 /* Read register thru SPI in fast SPI mode */
341 spi_rreg(robo_info_t *robo, uint8 page, uint8 addr, void *val, int len)
351 /* validate value length and buffer address */
352 ASSERT(len == 1 || (len == 2 && !((int)val & 1)) ||
353 (len == 4 && !((int)val & 3)));
355 /* Select chip and page */
356 spi_goto(robo, page);
358 /* Enable SPI access */
361 /* Fast SPI read with CID 0 and byte offset 0 */
362 cmd8 = (1 << 4); /* fast SPI */
363 spi_write(robo, &cmd8, 1);
364 spi_write(robo, &addr, 1);
365 status = spi_read(robo, (uint8 *)&bytes, len);
368 *(uint8 *)val = bytes.val8;
371 *(uint16 *)val = ltoh16(bytes.val16);
374 *(uint32 *)val = ltoh32(bytes.val32);
378 ET_MSG(("%s: [0x%x-0x%x] => 0x%x (len %d)\n", __FUNCTION__, page, addr,
379 *(uint16 *)val, len));
381 /* Disable SPI access */
386 /* SPI/gpio interface functions */
387 static dev_ops_t spigpio = {
396 /* Access switch registers through MII (MDC/MDIO) */
398 #define MII_MAX_RETRY 100
400 /* Write register thru MDC/MDIO */
402 mii_wreg(robo_info_t *robo, uint8 page, uint8 reg, void *val, int len)
404 uint16 cmd16, val16,val48[3];
410 uint8 *ptr = (uint8 *)val;
412 /* validate value length and buffer address */
413 ASSERT(len == 1 || len == 6 || len == 8 ||
414 ((len == 2) && !((int)val & 1)) || ((len == 4) && !((int)val & 3)));
416 ET_MSG(("%s: [0x%x-0x%x] := 0x%x (len %d)\n", __FUNCTION__, page, reg,
417 *(uint16 *)val, len));
419 /* set page number - MII register 0x10 */
420 if (robo->page != page) {
421 cmd16 = ((page << 8) | /* page number */
422 1); /* mdc/mdio access enable */
423 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_PAGE, cmd16);
430 val16 = ((val16 << 8) | ptr[6]);
431 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA3, val16);
436 val16 = ((val16 << 8) | ptr[4]);
437 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA2, val16);
439 val16 = ((val16 << 8) | ptr[2]);
440 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA1, val16);
442 val16 = ((val16 << 8) | ptr[0]);
443 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
447 val16 = (uint16)((*(uint32 *)val) >> 16);
448 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA1, val16);
449 val16 = (uint16)(*(uint32 *)val);
450 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
454 val16 = *(uint16 *)val;
455 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
459 val16 = *(uint8 *)val;
460 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
464 /* set register address - MII register 0x11 */
465 cmd16 = ((reg << 8) | /* register address */
466 1); /* opcode write */
467 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_ADDR, cmd16);
469 /* is operation finished? */
470 for (i = MII_MAX_RETRY; i > 0; i --) {
471 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_ADDR);
472 if ((val16 & 3) == 0)
478 ET_ERROR(("mii_wreg: timeout"));
484 /* Read register thru MDC/MDIO */
486 mii_rreg(robo_info_t *robo, uint8 page, uint8 reg, void *val, int len)
491 uint8 *ptr = (uint8 *)val;
493 /* validate value length and buffer address */
494 ASSERT(len == 1 || len == 6 || len == 8 ||
495 ((len == 2) && !((int)val & 1)) || ((len == 4) && !((int)val & 3)));
497 /* set page number - MII register 0x10 */
498 if (robo->page != page) {
499 cmd16 = ((page << 8) | /* page number */
500 1); /* mdc/mdio access enable */
501 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_PAGE, cmd16);
505 /* set register address - MII register 0x11 */
506 cmd16 = ((reg << 8) | /* register address */
507 2); /* opcode read */
508 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_ADDR, cmd16);
510 /* is operation finished? */
511 for (i = MII_MAX_RETRY; i > 0; i --) {
512 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_ADDR);
513 if ((val16 & 3) == 0)
518 ET_ERROR(("mii_rreg: timeout"));
522 ET_MSG(("%s: [0x%x-0x%x] => 0x%x (len %d)\n", __FUNCTION__, page, reg, val16, len));
526 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA3);
527 ptr[7] = (val16 >> 8);
528 ptr[6] = (val16 & 0xff);
532 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA2);
533 ptr[5] = (val16 >> 8);
534 ptr[4] = (val16 & 0xff);
535 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA1);
536 ptr[3] = (val16 >> 8);
537 ptr[2] = (val16 & 0xff);
538 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
539 ptr[1] = (val16 >> 8);
540 ptr[0] = (val16 & 0xff);
544 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA1);
545 *(uint32 *)val = (((uint32)val16) << 16);
546 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
547 *(uint32 *)val |= val16;
551 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
552 *(uint16 *)val = val16;
555 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
556 *(uint8 *)val = (uint8)(val16 & 0xff);
563 /* MII interface functions */
564 static dev_ops_t mdcmdio = {
572 /* High level switch configuration functions. */
575 findmatch(char *string, char *name)
582 while ((c = strchr(string, ',')) != NULL) {
583 if (len == (uint)(c - string) && !strncmp(string, name, len))
588 return (!strcmp(string, name));
592 getgpiopin(char *vars, char *pin_name, uint def_pin)
594 char name[] = "gpioXXXX";
598 /* Go thru all possibilities till a match in pin name */
599 for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
600 snprintf(name, sizeof(name), "gpio%d", pin);
601 val = getvar(vars, name);
602 if (val && findmatch(val, pin_name))
606 if (def_pin != GPIO_PIN_NOTDEFINED) {
607 /* make sure the default pin is not used by someone else */
608 snprintf(name, sizeof(name), "gpio%d", def_pin);
609 if (getvar(vars, name)) {
610 def_pin = GPIO_PIN_NOTDEFINED;
619 #define FLAG_TAGGED 't' /* output tagged (external ports only) */
620 #define FLAG_UNTAG 'u' /* input & output untagged (CPU port only, for OS (linux, ...) */
621 #define FLAG_LAN '*' /* input & output untagged (CPU port only, for CFE */
623 /* port descriptor */
625 uint32 untag; /* untag enable bit (Page 0x05 Address 0x63-0x66 Bit[17:9]) */
626 uint32 member; /* vlan member bit (Page 0x05 Address 0x63-0x66 Bit[7:0]) */
627 uint8 ptagr; /* port tag register address (Page 0x34 Address 0x10-0x1F) */
628 uint8 cpu; /* is this cpu port? */
631 pdesc_t pdesc97[] = {
632 /* 5395/5397/5398 is 0 ~ 7. port 8 is IMP port. */
633 /* port 0 */ {1 << 9, 1 << 0, REG_VLAN_PTAG0, 0},
634 /* port 1 */ {1 << 10, 1 << 1, REG_VLAN_PTAG1, 0},
635 /* port 2 */ {1 << 11, 1 << 2, REG_VLAN_PTAG2, 0},
636 /* port 3 */ {1 << 12, 1 << 3, REG_VLAN_PTAG3, 0},
637 /* port 4 */ {1 << 13, 1 << 4, REG_VLAN_PTAG4, 0},
638 /* port 5 */ {1 << 14, 1 << 5, REG_VLAN_PTAG5, 0},
639 /* port 6 */ {1 << 15, 1 << 6, REG_VLAN_PTAG6, 0},
640 /* port 7 */ {1 << 16, 1 << 7, REG_VLAN_PTAG7, 0},
641 /* mii port */ {1 << 17, 1 << 8, REG_VLAN_PTAG8, 1},
644 pdesc_t pdesc25[] = {
645 /* port 0 */ {1 << 6, 1 << 0, REG_VLAN_PTAG0, 0},
646 /* port 1 */ {1 << 7, 1 << 1, REG_VLAN_PTAG1, 0},
647 /* port 2 */ {1 << 8, 1 << 2, REG_VLAN_PTAG2, 0},
648 /* port 3 */ {1 << 9, 1 << 3, REG_VLAN_PTAG3, 0},
649 /* port 4 */ {1 << 10, 1 << 4, REG_VLAN_PTAG4, 0},
650 /* mii port */ {1 << 11, 1 << 5, REG_VLAN_PTAG5, 1},
654 #define to_robo(driver) ((robo_info_t *) ((switch_driver *) driver)->priv)
655 #define ROBO_START(driver) \
657 robo_info_t *robo = to_robo(driver); \
658 if (robo->ops->enable_mgmtif) \
659 robo->ops->enable_mgmtif(robo)
661 #define ROBO_END(driver) \
662 if (robo->ops->disable_mgmtif) \
663 robo->ops->disable_mgmtif(robo); \
667 bcm_robo_reset(robo_info_t *robo)
676 /* printk(KERN_WARNING "bcmrobo.c: bcm_robo_reset\n"); */
678 if (robo->ops->enable_mgmtif)
679 robo->ops->enable_mgmtif(robo);
681 /* setup global vlan configuration, FIXME: necessary? */
682 /* VLAN Control 0 Register (Page 0x34, Address 0) */
683 val8 = ((1 << 7) | /* enable 802.1Q VLAN */
684 (3 << 5)); /* individual VLAN learning mode */
685 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL0, &val8, sizeof(val8));
687 /* VLAN Control 1 Register (Page 0x34, Address 1) */
688 robo->ops->read_reg(robo, PAGE_VLAN, REG_VLAN_CTRL0, &val8, sizeof(val8));
689 val8 |= ((1 << 2) | /* enable RSV multicast V Fwdmap */
690 (1 << 3)); /* enable RSV multicast V Untagmap */
691 if (robo->devid == DEVID5325)
692 val8 |= (1 << 1); /* enable RSV multicast V Tagging */
693 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL1, &val8, sizeof(val8));
695 bcm_robo_set_macaddr(robo, NULL);
697 if (robo->devid == DEVID5325) {
698 /* VLAN Control 4 Register (Page 0x34, Address 4) */
699 val8 = (1 << 6); /* drop frame with VID violation */
700 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL4, &val8, sizeof(val8));
702 /* VLAN Control 5 Register (Page 0x34, Address 5) */
703 val8 = (1 << 3); /* drop frame when miss V table */
704 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL5, &val8, sizeof(val8));
707 pdescsz = sizeof(pdesc25) / sizeof(pdesc_t);
710 pdescsz = sizeof(pdesc97) / sizeof(pdesc_t);
713 if (robo->devid == DEVID5325) {
714 /* setup priority mapping - applies to tagged ingress frames */
715 /* Priority Re-map Register (Page 0x34, Address 0x20-0x23) */
716 /* FIXME: un-hardcode */
717 val32 = ((0 << 0) | /* 0 -> 0 */
718 (1 << 3) | /* 1 -> 1 */
719 (2 << 6) | /* 2 -> 2 */
720 (3 << 9) | /* 3 -> 3 */
721 (4 << 12) | /* 4 -> 4 */
722 (5 << 15) | /* 5 -> 5 */
723 (6 << 18) | /* 6 -> 6 */
724 (7 << 21)); /* 7 -> 7 */
725 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_PMAP, &val32, sizeof(val32));
728 /* Set unmanaged mode */
729 robo->ops->read_reg(robo, PAGE_CTRL, REG_CTRL_MODE, &val8, sizeof(val8));
731 robo->ops->write_reg(robo, PAGE_CTRL, REG_CTRL_MODE, &val8, sizeof(val8));
733 /* No spanning tree for unmanaged mode */
735 max_port_ind = ((robo->devid == DEVID5398) ? REG_CTRL_PORT7 : REG_CTRL_PORT4);
736 for (i = REG_CTRL_PORT0; i <= max_port_ind; i++) {
737 robo->ops->write_reg(robo, PAGE_CTRL, i, &val8, sizeof(val8));
742 robo->ops->write_reg(robo, PAGE_CTRL, 0x16, &val16, 2);
744 if (robo->ops->enable_mgmtif)
745 robo->ops->disable_mgmtif(robo);
750 /* Get access to the RoboSwitch */
752 bcm_robo_attach(sb_t *sbh, void *h, char *name, char *vars, miird_f miird, miiwr_f miiwr)
759 /* Allocate and init private state */
760 if (!(robo = MALLOC(sb_osh(sbh), sizeof(robo_info_t)))) {
761 ET_ERROR(("robo_attach: out of memory, malloced %d bytes", MALLOCED(sb_osh(sbh))));
764 bzero(robo, sizeof(robo_info_t));
774 /* Trigger external reset by nvram variable existance */
775 if ((reset = getgpiopin(robo->vars, "robo_reset", GPIO_PIN_NOTDEFINED)) !=
776 GPIO_PIN_NOTDEFINED) {
778 * Reset sequence: RESET low(50ms)->high(20ms)
780 * We have to perform a full sequence for we don't know how long
781 * it has been from power on till now.
783 ET_MSG(("%s: Using external reset in gpio pin %d\n", __FUNCTION__, reset));
786 /* Keep RESET low for 50 ms */
787 sb_gpioout(robo->sbh, reset, 0, GPIO_DRV_PRIORITY);
788 sb_gpioouten(robo->sbh, reset, reset, GPIO_DRV_PRIORITY);
791 if (robo->devid == DEVID5395)
792 nvram_set("switch_type", "BCM5395");
793 else if(robo->devid == DEVID5397)
794 nvram_set("switch_type", "BCM5397");
796 nvram_set("switch_type", "unknown");
798 /* Keep RESET high for at least 20 ms */
799 sb_gpioout(robo->sbh, reset, reset, GPIO_DRV_PRIORITY);
802 /* In case we need it */
803 idx = sb_coreidx(robo->sbh);
805 if (sb_setcore(robo->sbh, SB_ROBO, 0)) {
806 /* If we have an internal robo core, reset it using sb_core_reset */
807 ET_MSG(("%s: Resetting internal robo core\n", __FUNCTION__));
808 sb_core_reset(robo->sbh, 0, 0);
811 sb_setcoreidx(robo->sbh, idx);
814 if (miird && miiwr) {
816 int rc, retry_count = 0;
818 /* Read the PHY ID */
819 tmp = miird(h, PSEUDO_PHYAD, 2);
822 rc = mii_rreg(robo, PAGE_MMR, REG_DEVICE_ID, \
823 &robo->devid, sizeof(uint16));
827 } while ((robo->devid == 0) && (retry_count < 10));
829 ET_MSG(("%s: devid read %ssuccesfully via mii: 0x%x\n", __FUNCTION__, \
830 rc ? "un" : "", robo->devid));
831 ET_MSG(("%s: mii access to switch works\n", __FUNCTION__));
832 robo->ops = &mdcmdio;
833 if ((rc != 0) || (robo->devid == 0)) {
834 ET_MSG(("%s: error reading devid, assuming 5325e\n", __FUNCTION__));
835 robo->devid = DEVID5325;
837 ET_MSG(("%s: devid: 0x%x\n", __FUNCTION__, robo->devid));
841 if ((robo->devid == DEVID5395) ||
842 (robo->devid == DEVID5397) ||
843 (robo->devid == DEVID5398)) {
846 /* If it is a 539x switch, use the soft reset register */
847 ET_MSG(("%s: Resetting 539x robo switch\n", __FUNCTION__));
849 /* Reset the 539x switch core and register file */
851 mii_wreg(robo, PAGE_CTRL, REG_CTRL_SRST, &srst_ctrl, sizeof(uint8));
856 mii_wreg(robo, PAGE_CTRL, REG_CTRL_SRST, &srst_ctrl, sizeof(uint8));
860 int mosi, miso, ss, sck;
862 robo->ops = &spigpio;
863 robo->devid = DEVID5325;
865 /* Init GPIO mapping. Default 2, 3, 4, 5 */
866 ss = getgpiopin(vars, "robo_ss", 2);
867 if (ss == GPIO_PIN_NOTDEFINED) {
868 ET_ERROR(("robo_attach: robo_ss gpio fail: GPIO 2 in use"));
872 sck = getgpiopin(vars, "robo_sck", 3);
873 if (sck == GPIO_PIN_NOTDEFINED) {
874 ET_ERROR(("robo_attach: robo_sck gpio fail: GPIO 3 in use"));
877 robo->sck = 1 << sck;
878 mosi = getgpiopin(vars, "robo_mosi", 4);
879 if (mosi == GPIO_PIN_NOTDEFINED) {
880 ET_ERROR(("robo_attach: robo_mosi gpio fail: GPIO 4 in use"));
883 robo->mosi = 1 << mosi;
884 miso = getgpiopin(vars, "robo_miso", 5);
885 if (miso == GPIO_PIN_NOTDEFINED) {
886 ET_ERROR(("robo_attach: robo_miso gpio fail: GPIO 5 in use"));
889 robo->miso = 1 << miso;
890 ET_MSG(("%s: ss %d sck %d mosi %d miso %d\n", __FUNCTION__,
891 ss, sck, mosi, miso));
896 ASSERT(robo->ops->write_reg);
897 ASSERT(robo->ops->read_reg);
898 ASSERT((robo->devid == DEVID5325) ||
899 (robo->devid == DEVID5395) ||
900 (robo->devid == DEVID5397) ||
901 (robo->devid == DEVID5398));
903 bcm_robo_reset(robo);
909 MFREE(sb_osh(robo->sbh), robo, sizeof(robo_info_t));
913 /* Release access to the RoboSwitch */
915 bcm_robo_detach(robo_info_t *robo)
918 MFREE(sb_osh(robo->sbh), robo, sizeof(robo_info_t));
921 /* Enable the device and set it to a known good state */
923 bcm_robo_enable_device(robo_info_t *robo)
925 uint8 reg_offset, reg_val;
928 /* Enable management interface access */
929 if (robo->ops->enable_mgmtif)
930 robo->ops->enable_mgmtif(robo);
932 if (robo->devid == DEVID5398) {
933 /* Disable unused ports: port 6 and 7 */
934 for (reg_offset = REG_CTRL_PORT6; reg_offset <= REG_CTRL_PORT7; reg_offset ++) {
935 /* Set bits [1:0] to disable RX and TX */
937 robo->ops->write_reg(robo, PAGE_CTRL, reg_offset, ®_val,
942 if (robo->devid == DEVID5325) {
943 /* Must put the switch into Reverse MII mode! */
945 /* MII port state override (page 0 register 14) */
946 robo->ops->read_reg(robo, PAGE_CTRL, REG_CTRL_MIIPO, ®_val, sizeof(reg_val));
948 /* Bit 4 enables reverse MII mode */
949 if (!(reg_val & (1 << 4))) {
952 robo->ops->write_reg(robo, PAGE_CTRL, REG_CTRL_MIIPO, ®_val,
956 robo->ops->read_reg(robo, PAGE_CTRL, REG_CTRL_MIIPO, ®_val,
958 if (!(reg_val & (1 << 4))) {
959 ET_ERROR(("robo_enable_device: enabling RvMII mode failed\n"));
965 /* Disable management interface access */
966 if (robo->ops->disable_mgmtif)
967 robo->ops->disable_mgmtif(robo);
973 void bcm_robo_set_macaddr(robo_info_t *robo, char *mac_addr)
975 uint8 arl_entry[8] = { 0 }, arl_entry1[8] = { 0 };
977 if (mac_addr != NULL)
978 memcpy(robo->macaddr, mac_addr, 6);
980 mac_addr = robo->macaddr;
982 /* setup mac address */
983 arl_entry[0] = mac_addr[5];
984 arl_entry[1] = mac_addr[4];
985 arl_entry[2] = mac_addr[3];
986 arl_entry[3] = mac_addr[2];
987 arl_entry[4] = mac_addr[1];
988 arl_entry[5] = mac_addr[0];
990 if (robo->devid == DEVID5325) {
991 /* Init the entry 1 of the bin */
992 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_ARL_E1, \
993 arl_entry1, sizeof(arl_entry1));
994 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_VID_E1, \
997 /* Init the entry 0 of the bin */
998 arl_entry[6] = 0x8; /* Port Id: MII */
999 arl_entry[7] = 0xc0; /* Static Entry, Valid */
1001 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_ARL_E0, \
1002 arl_entry, sizeof(arl_entry));
1003 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_MINDX, \
1004 arl_entry, ETHER_ADDR_LEN);
1007 /* Initialize the MAC Addr Index Register */
1008 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_MINDX, \
1009 arl_entry, ETHER_ADDR_LEN);
1013 static int handle_reset(void *driver, char *buf, int nr)
1016 bcm_robo_reset(robo);
1023 static int handle_enable_read(void *driver, char *buf, int nr)
1029 robo->ops->read_reg(robo, PAGE_CTRL, REG_CTRL_MODE, &val8, sizeof(val8));
1030 ret = sprintf(buf, "%d\n", !!(val8 & (1 << 1)));
1036 static int handle_enable_write(void *driver, char *buf, int nr)
1040 /* printk(KERN_WARNING "bcmrobo.c: handle_enable_write\n"); */
1043 robo->ops->read_reg(robo, PAGE_CTRL, REG_CTRL_MODE, &val8, sizeof(val8));
1045 val8 |= ((buf[0] == '1') << 1);
1046 robo->ops->write_reg(robo, PAGE_CTRL, REG_CTRL_MODE, &val8, sizeof(val8));
1052 static int handle_enable_vlan_read(void *driver, char *buf, int nr)
1057 robo->ops->read_reg(robo, PAGE_VLAN, REG_VLAN_CTRL0, &val8, sizeof(val8));
1060 return sprintf(buf, "%d\n", (((val8 & (1 << 7)) == (1 << 7)) ? 1 : 0));
1062 static int handle_enable_vlan_write(void *driver, char *buf, int nr)
1064 int disable = ((buf[0] != '1') ? 1 : 0);
1071 uint8 arl_entry[8] = { 0 }, arl_entry1[8] = { 0 };
1073 /* printk(KERN_WARNING "bcmrobo.c: handle_enable_vlan_write\n"); */
1077 /* setup global vlan configuration */
1078 /* VLAN Control 0 Register (Page 0x34, Address 0) */
1079 val8 = disable ? 0 :
1080 ((1 << 7) | /* enable/disable 802.1Q VLAN */
1081 (3 << 5)); /* individual VLAN learning mode */
1082 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL0, &val8, sizeof(val8));
1084 /* VLAN Control 1 Register (Page 0x34, Address 1) */
1085 val8 = disable ? 0 :
1086 ((1 << 2) | /* enable/disable RSV multicast V Fwdmap */
1087 (1 << 3)); /* enable/disable RSV multicast V Untagmap */
1088 if (robo->devid == DEVID5325)
1089 val8 |= disable ? 0 : (1 << 1); /* enable/disable RSV multicast V Tagging */
1090 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL1, &val8, sizeof(val8));
1092 if ( disable == 0 ) { /* FIXME: ok to stop here when disabling? */
1093 arl_entry[0] = robo->macaddr[5];
1094 arl_entry[1] = robo->macaddr[4];
1095 arl_entry[2] = robo->macaddr[3];
1096 arl_entry[3] = robo->macaddr[2];
1097 arl_entry[4] = robo->macaddr[1];
1098 arl_entry[5] = robo->macaddr[0];
1100 if (robo->devid == DEVID5325) {
1101 /* Init the entry 1 of the bin */
1102 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_ARL_E1, \
1103 arl_entry1, sizeof(arl_entry1));
1104 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_VID_E1, \
1107 /* Init the entry 0 of the bin */
1108 arl_entry[6] = 0x8; /* Port Id: MII */
1109 arl_entry[7] = 0xc0; /* Static Entry, Valid */
1111 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_ARL_E0, \
1112 arl_entry, sizeof(arl_entry));
1113 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_MINDX, \
1114 arl_entry, ETHER_ADDR_LEN);
1116 /* VLAN Control 4 Register (Page 0x34, Address 4) */
1117 val8 = (1 << 6); /* drop frame with VID violation */
1118 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL4, &val8, sizeof(val8));
1120 /* VLAN Control 5 Register (Page 0x34, Address 5) */
1121 val8 = (1 << 3); /* drop frame when miss V table */
1122 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_CTRL5, &val8, sizeof(val8));
1125 pdescsz = sizeof(pdesc25) / sizeof(pdesc_t);
1127 /* Initialize the MAC Addr Index Register */
1128 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_MINDX, \
1129 arl_entry, ETHER_ADDR_LEN);
1132 pdescsz = sizeof(pdesc97) / sizeof(pdesc_t);
1135 /* setup each vlan. max. 16 vlans. */
1136 /* force vlan id to be equal to vlan number */
1137 for (vid = 0; vid < VLAN_NUMVLANS; vid ++) {
1139 /* Add static ARL entries */
1140 if (robo->devid == DEVID5325) {
1142 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_VID_E0, \
1143 &val8, sizeof(val8));
1144 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_VINDX, \
1145 &val8, sizeof(val8));
1147 /* Write the entry */
1149 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_CTRL, \
1150 &val8, sizeof(val8));
1151 /* Wait for write to complete */
1152 SPINWAIT((robo->ops->read_reg(robo, PAGE_VTBL, REG_VTBL_CTRL, \
1153 &val8, sizeof(val8)), ((val8 & 0x80) != 0)),
1156 /* Set the VLAN Id in VLAN ID Index Register */
1158 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_VINDX, \
1159 &val8, sizeof(val8));
1161 /* Set the MAC addr and VLAN Id in ARL Table MAC/VID Entry 0
1166 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_ARL_E0, \
1167 arl_entry, sizeof(arl_entry));
1169 /* Set the Static bit , Valid bit and Port ID fields in
1170 * ARL Table Data Entry 0 Register
1173 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_DAT_E0, \
1174 &val16, sizeof(val16));
1176 /* Clear the ARL_R/W bit and set the START/DONE bit in
1177 * the ARL Read/Write Control Register.
1180 robo->ops->write_reg(robo, PAGE_VTBL, REG_VTBL_CTRL, \
1181 &val8, sizeof(val8));
1182 /* Wait for write to complete */
1183 SPINWAIT((robo->ops->read_reg(robo, PAGE_VTBL, REG_VTBL_CTRL, \
1184 &val8, sizeof(val8)), ((val8 & 0x80) != 0)),
1194 static int handle_vlan_port_read(void *driver, char *buf, int nr)
1196 /* FIXME: yeah, some work is missing here */
1197 return sprintf(buf, "bcmrobo.c: handle_vlan_port_read unimplimented\n");
1200 static int handle_vlan_port_write(void *driver, char *buf, int nr)
1203 switch_driver *d = (switch_driver *) driver;
1204 switch_vlan_config *c = switch_parse_vlan(d, buf);
1213 /* printk(KERN_WARNING "bcmrobo.c: handle_vlan_port_write, nr %d\n", nr); */
1220 if (robo->devid == DEVID5325) {
1222 pdescsz = sizeof(pdesc25) / sizeof(pdesc_t);
1225 pdescsz = sizeof(pdesc97) / sizeof(pdesc_t);
1229 for (j = 0; j < d->ports; j++) {
1230 if ((c->untag | c->pvid) & (1 << j))
1231 if ((j != d->cpuport) || (c->untag & (1 << j))) {
1233 /* change default vlan tag */
1235 /* printk(KERN_WARNING "bcmrobo.c: set default vlan tag, port %d -> vlan %d\n", j, nr); */
1237 val16 = ((0 << 13) | /* priority - always 0 */
1239 robo->ops->write_reg(robo, PAGE_VLAN, pdesc[j].ptagr, &val16, sizeof(val16));
1244 if (robo->devid == DEVID5325) {
1245 val32 = ((c->untag << 6) | /* untag enable */
1246 c->port); /* vlan members */
1247 val32 |= ((1 << 20) | /* valid write */
1248 ((nr >> 4) << 12)); /* vlan id bit[11:4] */
1249 /* VLAN Write Register (Page 0x34, Address 0x08-0x0B) */
1250 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_WRITE, &val32,
1252 /* VLAN Table Access Register (Page 0x34, Address 0x06-0x07) */
1253 val16 = ((1 << 13) | /* start command */
1254 (1 << 12) | /* write state */
1256 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_ACCESS, &val16,
1259 uint8 vtble, vtbli, vtbla;
1260 val32 = ((c->untag << 9) | /* untag enable */
1261 c->port); /* vlan members */
1263 if (robo->devid == DEVID5395) {
1264 vtble = REG_VTBL_ENTRY_5395;
1265 vtbli = REG_VTBL_INDX_5395;
1266 vtbla = REG_VTBL_ACCESS_5395;
1268 vtble = REG_VTBL_ENTRY;
1269 vtbli = REG_VTBL_INDX;
1270 vtbla = REG_VTBL_ACCESS;
1273 /* VLAN Table Entry Register (Page 0x05, Address 0x63-0x66/0x83-0x86) */
1274 robo->ops->write_reg(robo, PAGE_VTBL, vtble, &val32,
1276 /* VLAN Table Address Index Reg (Page 0x05, Address 0x61-0x62/0x81-0x82) */
1277 val16 = nr; /* vlan id */
1278 robo->ops->write_reg(robo, PAGE_VTBL, vtbli, &val16,
1281 /* VLAN Table Access Register (Page 0x34, Address 0x60/0x80) */
1282 val8 = ((1 << 7) | /* start command */
1284 robo->ops->write_reg(robo, PAGE_VTBL, vtbla, &val8,
1292 static int __init config_attach(robo_info_t *robo)
1294 switch_config cfg[] = {
1295 {"enable", handle_enable_read, handle_enable_write},
1296 {"reset", NULL, handle_reset},
1297 {"enable_vlan", handle_enable_vlan_read, handle_enable_vlan_write},
1300 switch_config vlan[] = {
1301 {"ports", handle_vlan_port_read, handle_vlan_port_write},
1304 switch_driver driver = {
1306 version: DRIVER_VERSION,
1307 interface: robo->name,
1311 driver_handlers: cfg,
1312 port_handlers: NULL,
1313 vlan_handlers: vlan,
1315 if (robo->devid == DEVID5325) {
1319 driver.priv = (void *) robo;
1321 return switch_register_driver(&driver);
1324 static void __exit config_detach(robo_info_t *robo)
1326 switch_unregister_driver(DRIVER_NAME);