package/b43/src/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "sysfs.h"
  50 #include "xmit.h"
  51 #include "lo.h"
  52 #include "pcmcia.h"
  53
  54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  55 MODULE_AUTHOR("Martin Langer");
  56 MODULE_AUTHOR("Stefano Brivio");
  57 MODULE_AUTHOR("Michael Buesch");
  58 MODULE_LICENSE("GPL");
  59
  60
  61 static int modparam_bad_frames_preempt;
  62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  63 MODULE_PARM_DESC(bad_frames_preempt,
  64                  "enable(1) / disable(0) Bad Frames Preemption");
  65
  66 static char modparam_fwpostfix[16];
  67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  69
  70 static int modparam_hwpctl;
  71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  73
  74 static int modparam_nohwcrypt;
  75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77
  78 static const struct ssb_device_id b43_ssb_tbl[] = {
  79         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  80         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  81         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  86         SSB_DEVTABLE_END
  87 };
  88
  89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  90
  91 /* Channel and ratetables are shared for all devices.
  92  * They can't be const, because ieee80211 puts some precalculated
  93  * data in there. This data is the same for all devices, so we don't
  94  * get concurrency issues */
  95 #define RATETAB_ENT(_rateid, _flags) \
  96         {                                                               \
  97                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
  98                 .hw_value       = (_rateid),                            \
  99                 .flags          = (_flags),                             \
 100         }
 101
 102 /*
 103  * NOTE: When changing this, sync with xmit.c's
 104  *       b43_plcp_get_bitrate_idx_* functions!
 105  */
 106 static struct ieee80211_rate __b43_ratetable[] = {
 107         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
 108         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 109         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 110         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 111         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
 112         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
 113         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
 114         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
 115         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
 116         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
 117         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
 118         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
 119 };
 120
 121 #define b43_a_ratetable         (__b43_ratetable + 4)
 122 #define b43_a_ratetable_size    8
 123 #define b43_b_ratetable         (__b43_ratetable + 0)
 124 #define b43_b_ratetable_size    4
 125 #define b43_g_ratetable         (__b43_ratetable + 0)
 126 #define b43_g_ratetable_size    12
 127
 128 #define CHANTAB_ENT(_chanid, _freq) \
 129         {                                                       \
 130                 .center_freq    = (_freq),                      \
 131                 .hw_value       = (_chanid),                    \
 132         }
 133 static struct ieee80211_channel b43_2ghz_chantable[] = {
 134         CHANTAB_ENT(1, 2412),
 135         CHANTAB_ENT(2, 2417),
 136         CHANTAB_ENT(3, 2422),
 137         CHANTAB_ENT(4, 2427),
 138         CHANTAB_ENT(5, 2432),
 139         CHANTAB_ENT(6, 2437),
 140         CHANTAB_ENT(7, 2442),
 141         CHANTAB_ENT(8, 2447),
 142         CHANTAB_ENT(9, 2452),
 143         CHANTAB_ENT(10, 2457),
 144         CHANTAB_ENT(11, 2462),
 145         CHANTAB_ENT(12, 2467),
 146         CHANTAB_ENT(13, 2472),
 147         CHANTAB_ENT(14, 2484),
 148 };
 149
 150 #ifdef NOTYET
 151 static struct ieee80211_channel b43_5ghz_chantable[] = {
 152         CHANTAB_ENT(36, 5180),
 153         CHANTAB_ENT(40, 5200),
 154         CHANTAB_ENT(44, 5220),
 155         CHANTAB_ENT(48, 5240),
 156         CHANTAB_ENT(52, 5260),
 157         CHANTAB_ENT(56, 5280),
 158         CHANTAB_ENT(60, 5300),
 159         CHANTAB_ENT(64, 5320),
 160         CHANTAB_ENT(149, 5745),
 161         CHANTAB_ENT(153, 5765),
 162         CHANTAB_ENT(157, 5785),
 163         CHANTAB_ENT(161, 5805),
 164         CHANTAB_ENT(165, 5825),
 165 };
 166
 167 static struct ieee80211_supported_band b43_band_5GHz = {
 168         .channels = b43_5ghz_chantable,
 169         .n_channels = ARRAY_SIZE(b43_5ghz_chantable),
 170         .bitrates = b43_a_ratetable,
 171         .n_bitrates = b43_a_ratetable_size,
 172 };
 173 #endif
 174
 175 static struct ieee80211_supported_band b43_band_2GHz = {
 176         .channels = b43_2ghz_chantable,
 177         .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
 178         .bitrates = b43_g_ratetable,
 179         .n_bitrates = b43_g_ratetable_size,
 180 };
 181
 182 static void b43_wireless_core_exit(struct b43_wldev *dev);
 183 static int b43_wireless_core_init(struct b43_wldev *dev);
 184 static void b43_wireless_core_stop(struct b43_wldev *dev);
 185 static int b43_wireless_core_start(struct b43_wldev *dev);
 186
 187 static int b43_ratelimit(struct b43_wl *wl)
 188 {
 189         if (!wl || !wl->current_dev)
 190                 return 1;
 191         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 192                 return 1;
 193         /* We are up and running.
 194          * Ratelimit the messages to avoid DoS over the net. */
 195         return net_ratelimit();
 196 }
 197
 198 void b43info(struct b43_wl *wl, const char *fmt, ...)
 199 {
 200         va_list args;
 201
 202         if (!b43_ratelimit(wl))
 203                 return;
 204         va_start(args, fmt);
 205         printk(KERN_INFO "b43-%s: ",
 206                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 207         vprintk(fmt, args);
 208         va_end(args);
 209 }
 210
 211 void b43err(struct b43_wl *wl, const char *fmt, ...)
 212 {
 213         va_list args;
 214
 215         if (!b43_ratelimit(wl))
 216                 return;
 217         va_start(args, fmt);
 218         printk(KERN_ERR "b43-%s ERROR: ",
 219                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 220         vprintk(fmt, args);
 221         va_end(args);
 222 }
 223
 224 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 225 {
 226         va_list args;
 227
 228         if (!b43_ratelimit(wl))
 229                 return;
 230         va_start(args, fmt);
 231         printk(KERN_WARNING "b43-%s warning: ",
 232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 233         vprintk(fmt, args);
 234         va_end(args);
 235 }
 236
 237 #if B43_DEBUG
 238 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 239 {
 240         va_list args;
 241
 242         va_start(args, fmt);
 243         printk(KERN_DEBUG "b43-%s debug: ",
 244                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 245         vprintk(fmt, args);
 246         va_end(args);
 247 }
 248 #endif /* DEBUG */
 249
 250 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 251 {
 252         u32 macctl;
 253
 254         B43_WARN_ON(offset % 4 != 0);
 255
 256         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 257         if (macctl & B43_MACCTL_BE)
 258                 val = swab32(val);
 259
 260         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 261         mmiowb();
 262         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 263 }
 264
 265 static inline void b43_shm_control_word(struct b43_wldev *dev,
 266                                         u16 routing, u16 offset)
 267 {
 268         u32 control;
 269
 270         /* "offset" is the WORD offset. */
 271         control = routing;
 272         control <<= 16;
 273         control |= offset;
 274         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 275 }
 276
 277 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 278 {
 279         struct b43_wl *wl = dev->wl;
 280         unsigned long flags;
 281         u32 ret;
 282
 283         spin_lock_irqsave(&wl->shm_lock, flags);
 284         if (routing == B43_SHM_SHARED) {
 285                 B43_WARN_ON(offset & 0x0001);
 286                 if (offset & 0x0003) {
 287                         /* Unaligned access */
 288                         b43_shm_control_word(dev, routing, offset >> 2);
 289                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 290                         ret <<= 16;
 291                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 292                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 293
 294                         goto out;
 295                 }
 296                 offset >>= 2;
 297         }
 298         b43_shm_control_word(dev, routing, offset);
 299         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 300 out:
 301         spin_unlock_irqrestore(&wl->shm_lock, flags);
 302
 303         return ret;
 304 }
 305
 306 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 307 {
 308         struct b43_wl *wl = dev->wl;
 309         unsigned long flags;
 310         u16 ret;
 311
 312         spin_lock_irqsave(&wl->shm_lock, flags);
 313         if (routing == B43_SHM_SHARED) {
 314                 B43_WARN_ON(offset & 0x0001);
 315                 if (offset & 0x0003) {
 316                         /* Unaligned access */
 317                         b43_shm_control_word(dev, routing, offset >> 2);
 318                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 319
 320                         goto out;
 321                 }
 322                 offset >>= 2;
 323         }
 324         b43_shm_control_word(dev, routing, offset);
 325         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 326 out:
 327         spin_unlock_irqrestore(&wl->shm_lock, flags);
 328
 329         return ret;
 330 }
 331
 332 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 333 {
 334         struct b43_wl *wl = dev->wl;
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&wl->shm_lock, flags);
 338         if (routing == B43_SHM_SHARED) {
 339                 B43_WARN_ON(offset & 0x0001);
 340                 if (offset & 0x0003) {
 341                         /* Unaligned access */
 342                         b43_shm_control_word(dev, routing, offset >> 2);
 343                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 344                                     (value >> 16) & 0xffff);
 345                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 346                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 347                         goto out;
 348                 }
 349                 offset >>= 2;
 350         }
 351         b43_shm_control_word(dev, routing, offset);
 352         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 353 out:
 354         spin_unlock_irqrestore(&wl->shm_lock, flags);
 355 }
 356
 357 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 358 {
 359         struct b43_wl *wl = dev->wl;
 360         unsigned long flags;
 361
 362         spin_lock_irqsave(&wl->shm_lock, flags);
 363         if (routing == B43_SHM_SHARED) {
 364                 B43_WARN_ON(offset & 0x0001);
 365                 if (offset & 0x0003) {
 366                         /* Unaligned access */
 367                         b43_shm_control_word(dev, routing, offset >> 2);
 368                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 369                         goto out;
 370                 }
 371                 offset >>= 2;
 372         }
 373         b43_shm_control_word(dev, routing, offset);
 374         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 375 out:
 376         spin_unlock_irqrestore(&wl->shm_lock, flags);
 377 }
 378
 379 /* Read HostFlags */
 380 u32 b43_hf_read(struct b43_wldev * dev)
 381 {
 382         u32 ret;
 383
 384         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 385         ret <<= 16;
 386         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 387
 388         return ret;
 389 }
 390
 391 /* Write HostFlags */
 392 void b43_hf_write(struct b43_wldev *dev, u32 value)
 393 {
 394         b43_shm_write16(dev, B43_SHM_SHARED,
 395                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 396         b43_shm_write16(dev, B43_SHM_SHARED,
 397                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 398 }
 399
 400 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 401 {
 402         /* We need to be careful. As we read the TSF from multiple
 403          * registers, we should take care of register overflows.
 404          * In theory, the whole tsf read process should be atomic.
 405          * We try to be atomic here, by restaring the read process,
 406          * if any of the high registers changed (overflew).
 407          */
 408         if (dev->dev->id.revision >= 3) {
 409                 u32 low, high, high2;
 410
 411                 do {
 412                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 413                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 414                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 415                 } while (unlikely(high != high2));
 416
 417                 *tsf = high;
 418                 *tsf <<= 32;
 419                 *tsf |= low;
 420         } else {
 421                 u64 tmp;
 422                 u16 v0, v1, v2, v3;
 423                 u16 test1, test2, test3;
 424
 425                 do {
 426                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 427                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 428                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 429                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 430
 431                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 432                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 433                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 434                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 435
 436                 *tsf = v3;
 437                 *tsf <<= 48;
 438                 tmp = v2;
 439                 tmp <<= 32;
 440                 *tsf |= tmp;
 441                 tmp = v1;
 442                 tmp <<= 16;
 443                 *tsf |= tmp;
 444                 *tsf |= v0;
 445         }
 446 }
 447
 448 static void b43_time_lock(struct b43_wldev *dev)
 449 {
 450         u32 macctl;
 451
 452         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 453         macctl |= B43_MACCTL_TBTTHOLD;
 454         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 455         /* Commit the write */
 456         b43_read32(dev, B43_MMIO_MACCTL);
 457 }
 458
 459 static void b43_time_unlock(struct b43_wldev *dev)
 460 {
 461         u32 macctl;
 462
 463         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 464         macctl &= ~B43_MACCTL_TBTTHOLD;
 465         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 466         /* Commit the write */
 467         b43_read32(dev, B43_MMIO_MACCTL);
 468 }
 469
 470 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 471 {
 472         /* Be careful with the in-progress timer.
 473          * First zero out the low register, so we have a full
 474          * register-overflow duration to complete the operation.
 475          */
 476         if (dev->dev->id.revision >= 3) {
 477                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 478                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 479
 480                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 481                 mmiowb();
 482                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 483                 mmiowb();
 484                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 485         } else {
 486                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 487                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 488                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 489                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 490
 491                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 492                 mmiowb();
 493                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 494                 mmiowb();
 495                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 496                 mmiowb();
 497                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 498                 mmiowb();
 499                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 500         }
 501 }
 502
 503 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 504 {
 505         b43_time_lock(dev);
 506         b43_tsf_write_locked(dev, tsf);
 507         b43_time_unlock(dev);
 508 }
 509
 510 static
 511 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 512 {
 513         static const u8 zero_addr[ETH_ALEN] = { 0 };
 514         u16 data;
 515
 516         if (!mac)
 517                 mac = zero_addr;
 518
 519         offset |= 0x0020;
 520         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 521
 522         data = mac[0];
 523         data |= mac[1] << 8;
 524         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 525         data = mac[2];
 526         data |= mac[3] << 8;
 527         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 528         data = mac[4];
 529         data |= mac[5] << 8;
 530         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 531 }
 532
 533 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 534 {
 535         const u8 *mac;
 536         const u8 *bssid;
 537         u8 mac_bssid[ETH_ALEN * 2];
 538         int i;
 539         u32 tmp;
 540
 541         bssid = dev->wl->bssid;
 542         mac = dev->wl->mac_addr;
 543
 544         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 545
 546         memcpy(mac_bssid, mac, ETH_ALEN);
 547         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 548
 549         /* Write our MAC address and BSSID to template ram */
 550         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 551                 tmp = (u32) (mac_bssid[i + 0]);
 552                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 553                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 554                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 555                 b43_ram_write(dev, 0x20 + i, tmp);
 556         }
 557 }
 558
 559 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 560 {
 561         b43_write_mac_bssid_templates(dev);
 562         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 563 }
 564
 565 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 566 {
 567         /* slot_time is in usec. */
 568         if (dev->phy.type != B43_PHYTYPE_G)
 569                 return;
 570         b43_write16(dev, 0x684, 510 + slot_time);
 571         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 572 }
 573
 574 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 575 {
 576         b43_set_slot_time(dev, 9);
 577         dev->short_slot = 1;
 578 }
 579
 580 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 581 {
 582         b43_set_slot_time(dev, 20);
 583         dev->short_slot = 0;
 584 }
 585
 586 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 587  * Returns the _previously_ enabled IRQ mask.
 588  */
 589 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 590 {
 591         u32 old_mask;
 592
 593         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 594         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 595
 596         return old_mask;
 597 }
 598
 599 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 600  * Returns the _previously_ enabled IRQ mask.
 601  */
 602 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 603 {
 604         u32 old_mask;
 605
 606         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 607         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 608
 609         return old_mask;
 610 }
 611
 612 /* Synchronize IRQ top- and bottom-half.
 613  * IRQs must be masked before calling this.
 614  * This must not be called with the irq_lock held.
 615  */
 616 static void b43_synchronize_irq(struct b43_wldev *dev)
 617 {
 618         synchronize_irq(dev->dev->irq);
 619         tasklet_kill(&dev->isr_tasklet);
 620 }
 621
 622 /* DummyTransmission function, as documented on
 623  * http://bcm-specs.sipsolutions.net/DummyTransmission
 624  */
 625 void b43_dummy_transmission(struct b43_wldev *dev)
 626 {
 627         struct b43_phy *phy = &dev->phy;
 628         unsigned int i, max_loop;
 629         u16 value;
 630         u32 buffer[5] = {
 631                 0x00000000,
 632                 0x00D40000,
 633                 0x00000000,
 634                 0x01000000,
 635                 0x00000000,
 636         };
 637
 638         switch (phy->type) {
 639         case B43_PHYTYPE_A:
 640                 max_loop = 0x1E;
 641                 buffer[0] = 0x000201CC;
 642                 break;
 643         case B43_PHYTYPE_B:
 644         case B43_PHYTYPE_G:
 645                 max_loop = 0xFA;
 646                 buffer[0] = 0x000B846E;
 647                 break;
 648         default:
 649                 B43_WARN_ON(1);
 650                 return;
 651         }
 652
 653         for (i = 0; i < 5; i++)
 654                 b43_ram_write(dev, i * 4, buffer[i]);
 655
 656         /* Commit writes */
 657         b43_read32(dev, B43_MMIO_MACCTL);
 658
 659         b43_write16(dev, 0x0568, 0x0000);
 660         b43_write16(dev, 0x07C0, 0x0000);
 661         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 662         b43_write16(dev, 0x050C, value);
 663         b43_write16(dev, 0x0508, 0x0000);
 664         b43_write16(dev, 0x050A, 0x0000);
 665         b43_write16(dev, 0x054C, 0x0000);
 666         b43_write16(dev, 0x056A, 0x0014);
 667         b43_write16(dev, 0x0568, 0x0826);
 668         b43_write16(dev, 0x0500, 0x0000);
 669         b43_write16(dev, 0x0502, 0x0030);
 670
 671         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 672                 b43_radio_write16(dev, 0x0051, 0x0017);
 673         for (i = 0x00; i < max_loop; i++) {
 674                 value = b43_read16(dev, 0x050E);
 675                 if (value & 0x0080)
 676                         break;
 677                 udelay(10);
 678         }
 679         for (i = 0x00; i < 0x0A; i++) {
 680                 value = b43_read16(dev, 0x050E);
 681                 if (value & 0x0400)
 682                         break;
 683                 udelay(10);
 684         }
 685         for (i = 0x00; i < 0x0A; i++) {
 686                 value = b43_read16(dev, 0x0690);
 687                 if (!(value & 0x0100))
 688                         break;
 689                 udelay(10);
 690         }
 691         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 692                 b43_radio_write16(dev, 0x0051, 0x0037);
 693 }
 694
 695 static void key_write(struct b43_wldev *dev,
 696                       u8 index, u8 algorithm, const u8 * key)
 697 {
 698         unsigned int i;
 699         u32 offset;
 700         u16 value;
 701         u16 kidx;
 702
 703         /* Key index/algo block */
 704         kidx = b43_kidx_to_fw(dev, index);
 705         value = ((kidx << 4) | algorithm);
 706         b43_shm_write16(dev, B43_SHM_SHARED,
 707                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 708
 709         /* Write the key to the Key Table Pointer offset */
 710         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 711         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 712                 value = key[i];
 713                 value |= (u16) (key[i + 1]) << 8;
 714                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 715         }
 716 }
 717
 718 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 719 {
 720         u32 addrtmp[2] = { 0, 0, };
 721         u8 per_sta_keys_start = 8;
 722
 723         if (b43_new_kidx_api(dev))
 724                 per_sta_keys_start = 4;
 725
 726         B43_WARN_ON(index < per_sta_keys_start);
 727         /* We have two default TX keys and possibly two default RX keys.
 728          * Physical mac 0 is mapped to physical key 4 or 8, depending
 729          * on the firmware version.
 730          * So we must adjust the index here.
 731          */
 732         index -= per_sta_keys_start;
 733
 734         if (addr) {
 735                 addrtmp[0] = addr[0];
 736                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 737                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 738                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 739                 addrtmp[1] = addr[4];
 740                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 741         }
 742
 743         if (dev->dev->id.revision >= 5) {
 744                 /* Receive match transmitter address mechanism */
 745                 b43_shm_write32(dev, B43_SHM_RCMTA,
 746                                 (index * 2) + 0, addrtmp[0]);
 747                 b43_shm_write16(dev, B43_SHM_RCMTA,
 748                                 (index * 2) + 1, addrtmp[1]);
 749         } else {
 750                 /* RXE (Receive Engine) and
 751                  * PSM (Programmable State Machine) mechanism
 752                  */
 753                 if (index < 8) {
 754                         /* TODO write to RCM 16, 19, 22 and 25 */
 755                 } else {
 756                         b43_shm_write32(dev, B43_SHM_SHARED,
 757                                         B43_SHM_SH_PSM + (index * 6) + 0,
 758                                         addrtmp[0]);
 759                         b43_shm_write16(dev, B43_SHM_SHARED,
 760                                         B43_SHM_SH_PSM + (index * 6) + 4,
 761                                         addrtmp[1]);
 762                 }
 763         }
 764 }
 765
 766 static void do_key_write(struct b43_wldev *dev,
 767                          u8 index, u8 algorithm,
 768                          const u8 * key, size_t key_len, const u8 * mac_addr)
 769 {
 770         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 771         u8 per_sta_keys_start = 8;
 772
 773         if (b43_new_kidx_api(dev))
 774                 per_sta_keys_start = 4;
 775
 776         B43_WARN_ON(index >= dev->max_nr_keys);
 777         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 778
 779         if (index >= per_sta_keys_start)
 780                 keymac_write(dev, index, NULL); /* First zero out mac. */
 781         if (key)
 782                 memcpy(buf, key, key_len);
 783         key_write(dev, index, algorithm, buf);
 784         if (index >= per_sta_keys_start)
 785                 keymac_write(dev, index, mac_addr);
 786
 787         dev->key[index].algorithm = algorithm;
 788 }
 789
 790 static int b43_key_write(struct b43_wldev *dev,
 791                          int index, u8 algorithm,
 792                          const u8 * key, size_t key_len,
 793                          const u8 * mac_addr,
 794                          struct ieee80211_key_conf *keyconf)
 795 {
 796         int i;
 797         int sta_keys_start;
 798
 799         if (key_len > B43_SEC_KEYSIZE)
 800                 return -EINVAL;
 801         for (i = 0; i < dev->max_nr_keys; i++) {
 802                 /* Check that we don't already have this key. */
 803                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 804         }
 805         if (index < 0) {
 806                 /* Either pairwise key or address is 00:00:00:00:00:00
 807                  * for transmit-only keys. Search the index. */
 808                 if (b43_new_kidx_api(dev))
 809                         sta_keys_start = 4;
 810                 else
 811                         sta_keys_start = 8;
 812                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 813                         if (!dev->key[i].keyconf) {
 814                                 /* found empty */
 815                                 index = i;
 816                                 break;
 817                         }
 818                 }
 819                 if (index < 0) {
 820                         b43err(dev->wl, "Out of hardware key memory\n");
 821                         return -ENOSPC;
 822                 }
 823         } else
 824                 B43_WARN_ON(index > 3);
 825
 826         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 827         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 828                 /* Default RX key */
 829                 B43_WARN_ON(mac_addr);
 830                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 831         }
 832         keyconf->hw_key_idx = index;
 833         dev->key[index].keyconf = keyconf;
 834
 835         return 0;
 836 }
 837
 838 static int b43_key_clear(struct b43_wldev *dev, int index)
 839 {
 840         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 841                 return -EINVAL;
 842         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 843                      NULL, B43_SEC_KEYSIZE, NULL);
 844         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 845                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 846                              NULL, B43_SEC_KEYSIZE, NULL);
 847         }
 848         dev->key[index].keyconf = NULL;
 849
 850         return 0;
 851 }
 852
 853 static void b43_clear_keys(struct b43_wldev *dev)
 854 {
 855         int i;
 856
 857         for (i = 0; i < dev->max_nr_keys; i++)
 858                 b43_key_clear(dev, i);
 859 }
 860
 861 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 862 {
 863         u32 macctl;
 864         u16 ucstat;
 865         bool hwps;
 866         bool awake;
 867         int i;
 868
 869         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 870                     (ps_flags & B43_PS_DISABLED));
 871         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 872
 873         if (ps_flags & B43_PS_ENABLED) {
 874                 hwps = 1;
 875         } else if (ps_flags & B43_PS_DISABLED) {
 876                 hwps = 0;
 877         } else {
 878                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 879                 //      and thus is not an AP and we are associated, set bit 25
 880         }
 881         if (ps_flags & B43_PS_AWAKE) {
 882                 awake = 1;
 883         } else if (ps_flags & B43_PS_ASLEEP) {
 884                 awake = 0;
 885         } else {
 886                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 887                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 888                 //      successful, set bit26
 889         }
 890
 891 /* FIXME: For now we force awake-on and hwps-off */
 892         hwps = 0;
 893         awake = 1;
 894
 895         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 896         if (hwps)
 897                 macctl |= B43_MACCTL_HWPS;
 898         else
 899                 macctl &= ~B43_MACCTL_HWPS;
 900         if (awake)
 901                 macctl |= B43_MACCTL_AWAKE;
 902         else
 903                 macctl &= ~B43_MACCTL_AWAKE;
 904         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 905         /* Commit write */
 906         b43_read32(dev, B43_MMIO_MACCTL);
 907         if (awake && dev->dev->id.revision >= 5) {
 908                 /* Wait for the microcode to wake up. */
 909                 for (i = 0; i < 100; i++) {
 910                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 911                                                 B43_SHM_SH_UCODESTAT);
 912                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 913                                 break;
 914                         udelay(10);
 915                 }
 916         }
 917 }
 918
 919 /* Turn the Analog ON/OFF */
 920 static void b43_switch_analog(struct b43_wldev *dev, int on)
 921 {
 922         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 923 }
 924
 925 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 926 {
 927         u32 tmslow;
 928         u32 macctl;
 929
 930         flags |= B43_TMSLOW_PHYCLKEN;
 931         flags |= B43_TMSLOW_PHYRESET;
 932         ssb_device_enable(dev->dev, flags);
 933         msleep(2);              /* Wait for the PLL to turn on. */
 934
 935         /* Now take the PHY out of Reset again */
 936         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 937         tmslow |= SSB_TMSLOW_FGC;
 938         tmslow &= ~B43_TMSLOW_PHYRESET;
 939         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 940         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 941         msleep(1);
 942         tmslow &= ~SSB_TMSLOW_FGC;
 943         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 944         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 945         msleep(1);
 946
 947         /* Turn Analog ON */
 948         b43_switch_analog(dev, 1);
 949
 950         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 951         macctl &= ~B43_MACCTL_GMODE;
 952         if (flags & B43_TMSLOW_GMODE)
 953                 macctl |= B43_MACCTL_GMODE;
 954         macctl |= B43_MACCTL_IHR_ENABLED;
 955         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 956 }
 957
 958 static void handle_irq_transmit_status(struct b43_wldev *dev)
 959 {
 960         u32 v0, v1;
 961         u16 tmp;
 962         struct b43_txstatus stat;
 963
 964         while (1) {
 965                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 966                 if (!(v0 & 0x00000001))
 967                         break;
 968                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 969
 970                 stat.cookie = (v0 >> 16);
 971                 stat.seq = (v1 & 0x0000FFFF);
 972                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 973                 tmp = (v0 & 0x0000FFFF);
 974                 stat.frame_count = ((tmp & 0xF000) >> 12);
 975                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 976                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 977                 stat.pm_indicated = !!(tmp & 0x0080);
 978                 stat.intermediate = !!(tmp & 0x0040);
 979                 stat.for_ampdu = !!(tmp & 0x0020);
 980                 stat.acked = !!(tmp & 0x0002);
 981
 982                 b43_handle_txstatus(dev, &stat);
 983         }
 984 }
 985
 986 static void drain_txstatus_queue(struct b43_wldev *dev)
 987 {
 988         u32 dummy;
 989
 990         if (dev->dev->id.revision < 5)
 991                 return;
 992         /* Read all entries from the microcode TXstatus FIFO
 993          * and throw them away.
 994          */
 995         while (1) {
 996                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 997                 if (!(dummy & 0x00000001))
 998                         break;
 999                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1000         }
1001 }
1002
1003 static u32 b43_jssi_read(struct b43_wldev *dev)
1004 {
1005         u32 val = 0;
1006
1007         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1008         val <<= 16;
1009         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1010
1011         return val;
1012 }
1013
1014 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1015 {
1016         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1017         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1018 }
1019
1020 static void b43_generate_noise_sample(struct b43_wldev *dev)
1021 {
1022         b43_jssi_write(dev, 0x7F7F7F7F);
1023         b43_write32(dev, B43_MMIO_MACCMD,
1024                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1025         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1026 }
1027
1028 static void b43_calculate_link_quality(struct b43_wldev *dev)
1029 {
1030         /* Top half of Link Quality calculation. */
1031
1032         if (dev->noisecalc.calculation_running)
1033                 return;
1034         dev->noisecalc.channel_at_start = dev->phy.channel;
1035         dev->noisecalc.calculation_running = 1;
1036         dev->noisecalc.nr_samples = 0;
1037
1038         b43_generate_noise_sample(dev);
1039 }
1040
1041 static void handle_irq_noise(struct b43_wldev *dev)
1042 {
1043         struct b43_phy *phy = &dev->phy;
1044         u16 tmp;
1045         u8 noise[4];
1046         u8 i, j;
1047         s32 average;
1048
1049         /* Bottom half of Link Quality calculation. */
1050
1051         B43_WARN_ON(!dev->noisecalc.calculation_running);
1052         if (dev->noisecalc.channel_at_start != phy->channel)
1053                 goto drop_calculation;
1054         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1055         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1056             noise[2] == 0x7F || noise[3] == 0x7F)
1057                 goto generate_new;
1058
1059         /* Get the noise samples. */
1060         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1061         i = dev->noisecalc.nr_samples;
1062         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1063         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1064         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1065         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1066         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1067         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1068         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1069         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1070         dev->noisecalc.nr_samples++;
1071         if (dev->noisecalc.nr_samples == 8) {
1072                 /* Calculate the Link Quality by the noise samples. */
1073                 average = 0;
1074                 for (i = 0; i < 8; i++) {
1075                         for (j = 0; j < 4; j++)
1076                                 average += dev->noisecalc.samples[i][j];
1077                 }
1078                 average /= (8 * 4);
1079                 average *= 125;
1080                 average += 64;
1081                 average /= 128;
1082                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1083                 tmp = (tmp / 128) & 0x1F;
1084                 if (tmp >= 8)
1085                         average += 2;
1086                 else
1087                         average -= 25;
1088                 if (tmp == 8)
1089                         average -= 72;
1090                 else
1091                         average -= 48;
1092
1093                 dev->stats.link_noise = average;
1094               drop_calculation:
1095                 dev->noisecalc.calculation_running = 0;
1096                 return;
1097         }
1098       generate_new:
1099         b43_generate_noise_sample(dev);
1100 }
1101
1102 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1103 {
1104         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1105                 ///TODO: PS TBTT
1106         } else {
1107                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1108                         b43_power_saving_ctl_bits(dev, 0);
1109         }
1110         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1111                 dev->dfq_valid = 1;
1112 }
1113
1114 static void handle_irq_atim_end(struct b43_wldev *dev)
1115 {
1116         if (dev->dfq_valid) {
1117                 b43_write32(dev, B43_MMIO_MACCMD,
1118                             b43_read32(dev, B43_MMIO_MACCMD)
1119                             | B43_MACCMD_DFQ_VALID);
1120                 dev->dfq_valid = 0;
1121         }
1122 }
1123
1124 static void handle_irq_pmq(struct b43_wldev *dev)
1125 {
1126         u32 tmp;
1127
1128         //TODO: AP mode.
1129
1130         while (1) {
1131                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1132                 if (!(tmp & 0x00000008))
1133                         break;
1134         }
1135         /* 16bit write is odd, but correct. */
1136         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1137 }
1138
1139 static void b43_write_template_common(struct b43_wldev *dev,
1140                                       const u8 * data, u16 size,
1141                                       u16 ram_offset,
1142                                       u16 shm_size_offset, u8 rate)
1143 {
1144         u32 i, tmp;
1145         struct b43_plcp_hdr4 plcp;
1146
1147         plcp.data = 0;
1148         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1149         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1150         ram_offset += sizeof(u32);
1151         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1152          * So leave the first two bytes of the next write blank.
1153          */
1154         tmp = (u32) (data[0]) << 16;
1155         tmp |= (u32) (data[1]) << 24;
1156         b43_ram_write(dev, ram_offset, tmp);
1157         ram_offset += sizeof(u32);
1158         for (i = 2; i < size; i += sizeof(u32)) {
1159                 tmp = (u32) (data[i + 0]);
1160                 if (i + 1 < size)
1161                         tmp |= (u32) (data[i + 1]) << 8;
1162                 if (i + 2 < size)
1163                         tmp |= (u32) (data[i + 2]) << 16;
1164                 if (i + 3 < size)
1165                         tmp |= (u32) (data[i + 3]) << 24;
1166                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1167         }
1168         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1169                         size + sizeof(struct b43_plcp_hdr6));
1170 }
1171
1172 static void b43_write_beacon_template(struct b43_wldev *dev,
1173                                       u16 ram_offset,
1174                                       u16 shm_size_offset, u8 rate)
1175 {
1176         unsigned int i, len, variable_len;
1177         const struct ieee80211_mgmt *bcn;
1178         const u8 *ie;
1179         bool tim_found = 0;
1180
1181         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1182         len = min((size_t) dev->wl->current_beacon->len,
1183                   0x200 - sizeof(struct b43_plcp_hdr6));
1184
1185         b43_write_template_common(dev, (const u8 *)bcn,
1186                                   len, ram_offset, shm_size_offset, rate);
1187
1188         /* Find the position of the TIM and the DTIM_period value
1189          * and write them to SHM. */
1190         ie = bcn->u.beacon.variable;
1191         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1192         for (i = 0; i < variable_len - 2; ) {
1193                 uint8_t ie_id, ie_len;
1194
1195                 ie_id = ie[i];
1196                 ie_len = ie[i + 1];
1197                 if (ie_id == 5) {
1198                         u16 tim_position;
1199                         u16 dtim_period;
1200                         /* This is the TIM Information Element */
1201
1202                         /* Check whether the ie_len is in the beacon data range. */
1203                         if (variable_len < ie_len + 2 + i)
1204                                 break;
1205                         /* A valid TIM is at least 4 bytes long. */
1206                         if (ie_len < 4)
1207                                 break;
1208                         tim_found = 1;
1209
1210                         tim_position = sizeof(struct b43_plcp_hdr6);
1211                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1212                         tim_position += i;
1213
1214                         dtim_period = ie[i + 3];
1215
1216                         b43_shm_write16(dev, B43_SHM_SHARED,
1217                                         B43_SHM_SH_TIMBPOS, tim_position);
1218                         b43_shm_write16(dev, B43_SHM_SHARED,
1219                                         B43_SHM_SH_DTIMPER, dtim_period);
1220                         break;
1221                 }
1222                 i += ie_len + 2;
1223         }
1224         if (!tim_found) {
1225                 b43warn(dev->wl, "Did not find a valid TIM IE in "
1226                         "the beacon template packet. AP or IBSS operation "
1227                         "may be broken.\n");
1228         }
1229 }
1230
1231 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1232                                       u16 shm_offset, u16 size,
1233                                       struct ieee80211_rate *rate)
1234 {
1235         struct b43_plcp_hdr4 plcp;
1236         u32 tmp;
1237         __le16 dur;
1238
1239         plcp.data = 0;
1240         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1241         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1242                                                dev->wl->vif, size,
1243                                                rate);
1244         /* Write PLCP in two parts and timing for packet transfer */
1245         tmp = le32_to_cpu(plcp.data);
1246         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1247         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1248         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1249 }
1250
1251 /* Instead of using custom probe response template, this function
1252  * just patches custom beacon template by:
1253  * 1) Changing packet type
1254  * 2) Patching duration field
1255  * 3) Stripping TIM
1256  */
1257 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1258                                           u16 *dest_size,
1259                                           struct ieee80211_rate *rate)
1260 {
1261         const u8 *src_data;
1262         u8 *dest_data;
1263         u16 src_size, elem_size, src_pos, dest_pos;
1264         __le16 dur;
1265         struct ieee80211_hdr *hdr;
1266         size_t ie_start;
1267
1268         src_size = dev->wl->current_beacon->len;
1269         src_data = (const u8 *)dev->wl->current_beacon->data;
1270
1271         /* Get the start offset of the variable IEs in the packet. */
1272         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1273         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1274
1275         if (B43_WARN_ON(src_size < ie_start))
1276                 return NULL;
1277
1278         dest_data = kmalloc(src_size, GFP_ATOMIC);
1279         if (unlikely(!dest_data))
1280                 return NULL;
1281
1282         /* Copy the static data and all Information Elements, except the TIM. */
1283         memcpy(dest_data, src_data, ie_start);
1284         src_pos = ie_start;
1285         dest_pos = ie_start;
1286         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1287                 elem_size = src_data[src_pos + 1] + 2;
1288                 if (src_data[src_pos] == 5) {
1289                         /* This is the TIM. */
1290                         continue;
1291                 }
1292                 memcpy(dest_data + dest_pos, src_data + src_pos,
1293                        elem_size);
1294                 dest_pos += elem_size;
1295         }
1296         *dest_size = dest_pos;
1297         hdr = (struct ieee80211_hdr *)dest_data;
1298
1299         /* Set the frame control. */
1300         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1301                                          IEEE80211_STYPE_PROBE_RESP);
1302         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1303                                                dev->wl->vif, *dest_size,
1304                                                rate);
1305         hdr->duration_id = dur;
1306
1307         return dest_data;
1308 }
1309
1310 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1311                                           u16 ram_offset,
1312                                           u16 shm_size_offset,
1313                                           struct ieee80211_rate *rate)
1314 {
1315         const u8 *probe_resp_data;
1316         u16 size;
1317
1318         size = dev->wl->current_beacon->len;
1319         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1320         if (unlikely(!probe_resp_data))
1321                 return;
1322
1323         /* Looks like PLCP headers plus packet timings are stored for
1324          * all possible basic rates
1325          */
1326         b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1327         b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1328         b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1329         b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1330
1331         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1332         b43_write_template_common(dev, probe_resp_data,
1333                                   size, ram_offset, shm_size_offset,
1334                                   rate->hw_value);
1335         kfree(probe_resp_data);
1336 }
1337
1338 /* Asynchronously update the packet templates in template RAM.
1339  * Locking: Requires wl->irq_lock to be locked. */
1340 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1341 {
1342         /* This is the top half of the ansynchronous beacon update.
1343          * The bottom half is the beacon IRQ.
1344          * Beacon update must be asynchronous to avoid sending an
1345          * invalid beacon. This can happen for example, if the firmware
1346          * transmits a beacon while we are updating it. */
1347
1348         if (wl->current_beacon)
1349                 dev_kfree_skb_any(wl->current_beacon);
1350         wl->current_beacon = beacon;
1351         wl->beacon0_uploaded = 0;
1352         wl->beacon1_uploaded = 0;
1353 }
1354
1355 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1356 {
1357         u32 tmp;
1358         u16 i, len;
1359
1360         len = min((u16) ssid_len, (u16) 0x100);
1361         for (i = 0; i < len; i += sizeof(u32)) {
1362                 tmp = (u32) (ssid[i + 0]);
1363                 if (i + 1 < len)
1364                         tmp |= (u32) (ssid[i + 1]) << 8;
1365                 if (i + 2 < len)
1366                         tmp |= (u32) (ssid[i + 2]) << 16;
1367                 if (i + 3 < len)
1368                         tmp |= (u32) (ssid[i + 3]) << 24;
1369                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1370         }
1371         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1372 }
1373
1374 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1375 {
1376         b43_time_lock(dev);
1377         if (dev->dev->id.revision >= 3) {
1378                 b43_write32(dev, 0x188, (beacon_int << 16));
1379         } else {
1380                 b43_write16(dev, 0x606, (beacon_int >> 6));
1381                 b43_write16(dev, 0x610, beacon_int);
1382         }
1383         b43_time_unlock(dev);
1384 }
1385
1386 static void handle_irq_beacon(struct b43_wldev *dev)
1387 {
1388         struct b43_wl *wl = dev->wl;
1389         u32 cmd;
1390
1391         if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1392                 return;
1393
1394         /* This is the bottom half of the asynchronous beacon update. */
1395
1396         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1397         if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1398                 if (!wl->beacon0_uploaded) {
1399                         b43_write_beacon_template(dev, 0x68, 0x18,
1400                                                   B43_CCK_RATE_1MB);
1401                         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1402                                                       &__b43_ratetable[3]);
1403                         wl->beacon0_uploaded = 1;
1404                 }
1405                 cmd |= B43_MACCMD_BEACON0_VALID;
1406         }
1407         if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1408                 if (!wl->beacon1_uploaded) {
1409                         b43_write_beacon_template(dev, 0x468, 0x1A,
1410                                                   B43_CCK_RATE_1MB);
1411                         wl->beacon1_uploaded = 1;
1412                 }
1413                 cmd |= B43_MACCMD_BEACON1_VALID;
1414         }
1415         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1416 }
1417
1418 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1419 {
1420         //TODO
1421 }
1422
1423 /* Interrupt handler bottom-half */
1424 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1425 {
1426         u32 reason;
1427         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1428         u32 merged_dma_reason = 0;
1429         int i;
1430         unsigned long flags;
1431
1432         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1433
1434         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1435
1436         reason = dev->irq_reason;
1437         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1438                 dma_reason[i] = dev->dma_reason[i];
1439                 merged_dma_reason |= dma_reason[i];
1440         }
1441
1442         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1443                 b43err(dev->wl, "MAC transmission error\n");
1444
1445         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1446                 b43err(dev->wl, "PHY transmission error\n");
1447                 rmb();
1448                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1449                         atomic_set(&dev->phy.txerr_cnt,
1450                                    B43_PHY_TX_BADNESS_LIMIT);
1451                         b43err(dev->wl, "Too many PHY TX errors, "
1452                                         "restarting the controller\n");
1453                         b43_controller_restart(dev, "PHY TX errors");
1454                 }
1455         }
1456
1457         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1458                                           B43_DMAIRQ_NONFATALMASK))) {
1459                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1460                         b43err(dev->wl, "Fatal DMA error: "
1461                                "0x%08X, 0x%08X, 0x%08X, "
1462                                "0x%08X, 0x%08X, 0x%08X\n",
1463                                dma_reason[0], dma_reason[1],
1464                                dma_reason[2], dma_reason[3],
1465                                dma_reason[4], dma_reason[5]);
1466                         b43_controller_restart(dev, "DMA error");
1467                         mmiowb();
1468                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1469                         return;
1470                 }
1471                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1472                         b43err(dev->wl, "DMA error: "
1473                                "0x%08X, 0x%08X, 0x%08X, "
1474                                "0x%08X, 0x%08X, 0x%08X\n",
1475                                dma_reason[0], dma_reason[1],
1476                                dma_reason[2], dma_reason[3],
1477                                dma_reason[4], dma_reason[5]);
1478                 }
1479         }
1480
1481         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1482                 handle_irq_ucode_debug(dev);
1483         if (reason & B43_IRQ_TBTT_INDI)
1484                 handle_irq_tbtt_indication(dev);
1485         if (reason & B43_IRQ_ATIM_END)
1486                 handle_irq_atim_end(dev);
1487         if (reason & B43_IRQ_BEACON)
1488                 handle_irq_beacon(dev);
1489         if (reason & B43_IRQ_PMQ)
1490                 handle_irq_pmq(dev);
1491         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1492                 ;/* TODO */
1493         if (reason & B43_IRQ_NOISESAMPLE_OK)
1494                 handle_irq_noise(dev);
1495
1496         /* Check the DMA reason registers for received data. */
1497         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1498                 b43_dma_rx(dev->dma.rx_ring0);
1499         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1500                 b43_dma_rx(dev->dma.rx_ring3);
1501         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1502         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1503         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1504         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1505
1506         if (reason & B43_IRQ_TX_OK)
1507                 handle_irq_transmit_status(dev);
1508
1509         b43_interrupt_enable(dev, dev->irq_savedstate);
1510         mmiowb();
1511         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1512 }
1513
1514 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1515 {
1516         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1517
1518         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1519         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1520         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1521         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1522         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1523         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1524 }
1525
1526 /* Interrupt handler top-half */
1527 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1528 {
1529         irqreturn_t ret = IRQ_NONE;
1530         struct b43_wldev *dev = dev_id;
1531         u32 reason;
1532
1533         if (!dev)
1534                 return IRQ_NONE;
1535
1536         spin_lock(&dev->wl->irq_lock);
1537
1538         if (b43_status(dev) < B43_STAT_STARTED)
1539                 goto out;
1540         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1541         if (reason == 0xffffffff)       /* shared IRQ */
1542                 goto out;
1543         ret = IRQ_HANDLED;
1544         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1545         if (!reason)
1546                 goto out;
1547
1548         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1549             & 0x0001DC00;
1550         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1551             & 0x0000DC00;
1552         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1553             & 0x0000DC00;
1554         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1555             & 0x0001DC00;
1556         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1557             & 0x0000DC00;
1558         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1559             & 0x0000DC00;
1560
1561         b43_interrupt_ack(dev, reason);
1562         /* disable all IRQs. They are enabled again in the bottom half. */
1563         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1564         /* save the reason code and call our bottom half. */
1565         dev->irq_reason = reason;
1566         tasklet_schedule(&dev->isr_tasklet);
1567       out:
1568         mmiowb();
1569         spin_unlock(&dev->wl->irq_lock);
1570
1571         return ret;
1572 }
1573
1574 static void do_release_fw(struct b43_firmware_file *fw)
1575 {
1576         release_firmware(fw->data);
1577         fw->data = NULL;
1578         fw->filename = NULL;
1579 }
1580
1581 static void b43_release_firmware(struct b43_wldev *dev)
1582 {
1583         do_release_fw(&dev->fw.ucode);
1584         do_release_fw(&dev->fw.pcm);
1585         do_release_fw(&dev->fw.initvals);
1586         do_release_fw(&dev->fw.initvals_band);
1587 }
1588
1589 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1590 {
1591         const char *text;
1592
1593         text = "You must go to "
1594                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1595                "and download the latest firmware (version 4).\n";
1596         if (error)
1597                 b43err(wl, text);
1598         else
1599                 b43warn(wl, text);
1600 }
1601
1602 static int do_request_fw(struct b43_wldev *dev,
1603                          const char *name,
1604                          struct b43_firmware_file *fw)
1605 {
1606         char path[sizeof(modparam_fwpostfix) + 32];
1607         const struct firmware *blob;
1608         struct b43_fw_header *hdr;
1609         u32 size;
1610         int err;
1611
1612         if (!name) {
1613                 /* Don't fetch anything. Free possibly cached firmware. */
1614                 do_release_fw(fw);
1615                 return 0;
1616         }
1617         if (fw->filename) {
1618                 if (strcmp(fw->filename, name) == 0)
1619                         return 0; /* Already have this fw. */
1620                 /* Free the cached firmware first. */
1621                 do_release_fw(fw);
1622         }
1623
1624         snprintf(path, ARRAY_SIZE(path),
1625                  "b43%s/%s.fw",
1626                  modparam_fwpostfix, name);
1627         err = request_firmware(&blob, path, dev->dev->dev);
1628         if (err) {
1629                 b43err(dev->wl, "Firmware file \"%s\" not found "
1630                        "or load failed.\n", path);
1631                 return err;
1632         }
1633         if (blob->size < sizeof(struct b43_fw_header))
1634                 goto err_format;
1635         hdr = (struct b43_fw_header *)(blob->data);
1636         switch (hdr->type) {
1637         case B43_FW_TYPE_UCODE:
1638         case B43_FW_TYPE_PCM:
1639                 size = be32_to_cpu(hdr->size);
1640                 if (size != blob->size - sizeof(struct b43_fw_header))
1641                         goto err_format;
1642                 /* fallthrough */
1643         case B43_FW_TYPE_IV:
1644                 if (hdr->ver != 1)
1645                         goto err_format;
1646                 break;
1647         default:
1648                 goto err_format;
1649         }
1650
1651         fw->data = blob;
1652         fw->filename = name;
1653
1654         return 0;
1655
1656 err_format:
1657         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1658         release_firmware(blob);
1659
1660         return -EPROTO;
1661 }
1662
1663 static int b43_request_firmware(struct b43_wldev *dev)
1664 {
1665         struct b43_firmware *fw = &dev->fw;
1666         const u8 rev = dev->dev->id.revision;
1667         const char *filename;
1668         u32 tmshigh;
1669         int err;
1670
1671         /* Get microcode */
1672         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1673         if ((rev >= 5) && (rev <= 10))
1674                 filename = "ucode5";
1675         else if ((rev >= 11) && (rev <= 12))
1676                 filename = "ucode11";
1677         else if (rev >= 13)
1678                 filename = "ucode13";
1679         else
1680                 goto err_no_ucode;
1681         err = do_request_fw(dev, filename, &fw->ucode);
1682         if (err)
1683                 goto err_load;
1684
1685         /* Get PCM code */
1686         if ((rev >= 5) && (rev <= 10))
1687                 filename = "pcm5";
1688         else if (rev >= 11)
1689                 filename = NULL;
1690         else
1691                 goto err_no_pcm;
1692         err = do_request_fw(dev, filename, &fw->pcm);
1693         if (err)
1694                 goto err_load;
1695
1696         /* Get initvals */
1697         switch (dev->phy.type) {
1698         case B43_PHYTYPE_A:
1699                 if ((rev >= 5) && (rev <= 10)) {
1700                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1701                                 filename = "a0g1initvals5";
1702                         else
1703                                 filename = "a0g0initvals5";
1704                 } else
1705                         goto err_no_initvals;
1706                 break;
1707         case B43_PHYTYPE_G:
1708                 if ((rev >= 5) && (rev <= 10))
1709                         filename = "b0g0initvals5";
1710                 else if (rev >= 13)
1711                         filename = "lp0initvals13";
1712                 else
1713                         goto err_no_initvals;
1714                 break;
1715         case B43_PHYTYPE_N:
1716                 if ((rev >= 11) && (rev <= 12))
1717                         filename = "n0initvals11";
1718                 else
1719                         goto err_no_initvals;
1720                 break;
1721         default:
1722                 goto err_no_initvals;
1723         }
1724         err = do_request_fw(dev, filename, &fw->initvals);
1725         if (err)
1726                 goto err_load;
1727
1728         /* Get bandswitch initvals */
1729         switch (dev->phy.type) {
1730         case B43_PHYTYPE_A:
1731                 if ((rev >= 5) && (rev <= 10)) {
1732                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1733                                 filename = "a0g1bsinitvals5";
1734                         else
1735                                 filename = "a0g0bsinitvals5";
1736                 } else if (rev >= 11)
1737                         filename = NULL;
1738                 else
1739                         goto err_no_initvals;
1740                 break;
1741         case B43_PHYTYPE_G:
1742                 if ((rev >= 5) && (rev <= 10))
1743                         filename = "b0g0bsinitvals5";
1744                 else if (rev >= 11)
1745                         filename = NULL;
1746                 else
1747                         goto err_no_initvals;
1748                 break;
1749         case B43_PHYTYPE_N:
1750                 if ((rev >= 11) && (rev <= 12))
1751                         filename = "n0bsinitvals11";
1752                 else
1753                         goto err_no_initvals;
1754                 break;
1755         default:
1756                 goto err_no_initvals;
1757         }
1758         err = do_request_fw(dev, filename, &fw->initvals_band);
1759         if (err)
1760                 goto err_load;
1761
1762         return 0;
1763
1764 err_load:
1765         b43_print_fw_helptext(dev->wl, 1);
1766         goto error;
1767
1768 err_no_ucode:
1769         err = -ENODEV;
1770         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1771         goto error;
1772
1773 err_no_pcm:
1774         err = -ENODEV;
1775         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1776         goto error;
1777
1778 err_no_initvals:
1779         err = -ENODEV;
1780         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1781                "core rev %u\n", dev->phy.type, rev);
1782         goto error;
1783
1784 error:
1785         b43_release_firmware(dev);
1786         return err;
1787 }
1788
1789 static int b43_upload_microcode(struct b43_wldev *dev)
1790 {
1791         const size_t hdr_len = sizeof(struct b43_fw_header);
1792         const __be32 *data;
1793         unsigned int i, len;
1794         u16 fwrev, fwpatch, fwdate, fwtime;
1795         u32 tmp, macctl;
1796         int err = 0;
1797
1798         /* Jump the microcode PSM to offset 0 */
1799         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1800         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1801         macctl |= B43_MACCTL_PSM_JMP0;
1802         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1803         /* Zero out all microcode PSM registers and shared memory. */
1804         for (i = 0; i < 64; i++)
1805                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1806         for (i = 0; i < 4096; i += 2)
1807                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1808
1809         /* Upload Microcode. */
1810         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1811         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1812         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1813         for (i = 0; i < len; i++) {
1814                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1815                 udelay(10);
1816         }
1817
1818         if (dev->fw.pcm.data) {
1819                 /* Upload PCM data. */
1820                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1821                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1822                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1823                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1824                 /* No need for autoinc bit in SHM_HW */
1825                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1826                 for (i = 0; i < len; i++) {
1827                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1828                         udelay(10);
1829                 }
1830         }
1831
1832         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1833
1834         /* Start the microcode PSM */
1835         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1836         macctl &= ~B43_MACCTL_PSM_JMP0;
1837         macctl |= B43_MACCTL_PSM_RUN;
1838         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1839
1840         /* Wait for the microcode to load and respond */
1841         i = 0;
1842         while (1) {
1843                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1844                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1845                         break;
1846                 i++;
1847                 if (i >= 20) {
1848                         b43err(dev->wl, "Microcode not responding\n");
1849                         b43_print_fw_helptext(dev->wl, 1);
1850                         err = -ENODEV;
1851                         goto error;
1852                 }
1853                 msleep_interruptible(50);
1854                 if (signal_pending(current)) {
1855                         err = -EINTR;
1856                         goto error;
1857                 }
1858         }
1859         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1860
1861         /* Get and check the revisions. */
1862         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1863         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1864         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1865         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1866
1867         if (fwrev <= 0x128) {
1868                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1869                        "binary drivers older than version 4.x is unsupported. "
1870                        "You must upgrade your firmware files.\n");
1871                 b43_print_fw_helptext(dev->wl, 1);
1872                 err = -EOPNOTSUPP;
1873                 goto error;
1874         }
1875         b43dbg(dev->wl, "Loading firmware version %u.%u "
1876                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1877                fwrev, fwpatch,
1878                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1879                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1880
1881         dev->fw.rev = fwrev;
1882         dev->fw.patch = fwpatch;
1883
1884         if (b43_is_old_txhdr_format(dev)) {
1885                 b43warn(dev->wl, "You are using an old firmware image. "
1886                         "Support for old firmware will be removed in July 2008.\n");
1887                 b43_print_fw_helptext(dev->wl, 0);
1888         }
1889
1890         return 0;
1891
1892 error:
1893         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1894         macctl &= ~B43_MACCTL_PSM_RUN;
1895         macctl |= B43_MACCTL_PSM_JMP0;
1896         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1897
1898         return err;
1899 }
1900
1901 static int b43_write_initvals(struct b43_wldev *dev,
1902                               const struct b43_iv *ivals,
1903                               size_t count,
1904                               size_t array_size)
1905 {
1906         const struct b43_iv *iv;
1907         u16 offset;
1908         size_t i;
1909         bool bit32;
1910
1911         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1912         iv = ivals;
1913         for (i = 0; i < count; i++) {
1914                 if (array_size < sizeof(iv->offset_size))
1915                         goto err_format;
1916                 array_size -= sizeof(iv->offset_size);
1917                 offset = be16_to_cpu(iv->offset_size);
1918                 bit32 = !!(offset & B43_IV_32BIT);
1919                 offset &= B43_IV_OFFSET_MASK;
1920                 if (offset >= 0x1000)
1921                         goto err_format;
1922                 if (bit32) {
1923                         u32 value;
1924
1925                         if (array_size < sizeof(iv->data.d32))
1926                                 goto err_format;
1927                         array_size -= sizeof(iv->data.d32);
1928
1929                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1930                         b43_write32(dev, offset, value);
1931
1932                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1933                                                         sizeof(__be16) +
1934                                                         sizeof(__be32));
1935                 } else {
1936                         u16 value;
1937
1938                         if (array_size < sizeof(iv->data.d16))
1939                                 goto err_format;
1940                         array_size -= sizeof(iv->data.d16);
1941
1942                         value = be16_to_cpu(iv->data.d16);
1943                         b43_write16(dev, offset, value);
1944
1945                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1946                                                         sizeof(__be16) +
1947                                                         sizeof(__be16));
1948                 }
1949         }
1950         if (array_size)
1951                 goto err_format;
1952
1953         return 0;
1954
1955 err_format:
1956         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1957         b43_print_fw_helptext(dev->wl, 1);
1958
1959         return -EPROTO;
1960 }
1961
1962 static int b43_upload_initvals(struct b43_wldev *dev)
1963 {
1964         const size_t hdr_len = sizeof(struct b43_fw_header);
1965         const struct b43_fw_header *hdr;
1966         struct b43_firmware *fw = &dev->fw;
1967         const struct b43_iv *ivals;
1968         size_t count;
1969         int err;
1970
1971         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1972         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1973         count = be32_to_cpu(hdr->size);
1974         err = b43_write_initvals(dev, ivals, count,
1975                                  fw->initvals.data->size - hdr_len);
1976         if (err)
1977                 goto out;
1978         if (fw->initvals_band.data) {
1979                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1980                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1981                 count = be32_to_cpu(hdr->size);
1982                 err = b43_write_initvals(dev, ivals, count,
1983                                          fw->initvals_band.data->size - hdr_len);
1984                 if (err)
1985                         goto out;
1986         }
1987 out:
1988
1989         return err;
1990 }
1991
1992 /* Initialize the GPIOs
1993  * http://bcm-specs.sipsolutions.net/GPIO
1994  */
1995 static int b43_gpio_init(struct b43_wldev *dev)
1996 {
1997         struct ssb_bus *bus = dev->dev->bus;
1998         struct ssb_device *gpiodev, *pcidev = NULL;
1999         u32 mask, set;
2000
2001         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2002                     & ~B43_MACCTL_GPOUTSMSK);
2003
2004         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2005                     | 0x000F);
2006
2007         mask = 0x0000001F;
2008         set = 0x0000000F;
2009         if (dev->dev->bus->chip_id == 0x4301) {
2010                 mask |= 0x0060;
2011                 set |= 0x0060;
2012         }
2013         if (0 /* FIXME: conditional unknown */ ) {
2014                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2015                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2016                             | 0x0100);
2017                 mask |= 0x0180;
2018                 set |= 0x0180;
2019         }
2020         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2021                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2022                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2023                             | 0x0200);
2024                 mask |= 0x0200;
2025                 set |= 0x0200;
2026         }
2027         if (dev->dev->id.revision >= 2)
2028                 mask |= 0x0010; /* FIXME: This is redundant. */
2029
2030 #ifdef CONFIG_SSB_DRIVER_PCICORE
2031         pcidev = bus->pcicore.dev;
2032 #endif
2033         gpiodev = bus->chipco.dev ? : pcidev;
2034         if (!gpiodev)
2035                 return 0;
2036         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2037                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2038                      & mask) | set);
2039
2040         return 0;
2041 }
2042
2043 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2044 static void b43_gpio_cleanup(struct b43_wldev *dev)
2045 {
2046         struct ssb_bus *bus = dev->dev->bus;
2047         struct ssb_device *gpiodev, *pcidev = NULL;
2048
2049 #ifdef CONFIG_SSB_DRIVER_PCICORE
2050         pcidev = bus->pcicore.dev;
2051 #endif
2052         gpiodev = bus->chipco.dev ? : pcidev;
2053         if (!gpiodev)
2054                 return;
2055         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2056 }
2057
2058 /* http://bcm-specs.sipsolutions.net/EnableMac */
2059 void b43_mac_enable(struct b43_wldev *dev)
2060 {
2061         dev->mac_suspended--;
2062         B43_WARN_ON(dev->mac_suspended < 0);
2063         B43_WARN_ON(irqs_disabled());
2064         if (dev->mac_suspended == 0) {
2065                 b43_write32(dev, B43_MMIO_MACCTL,
2066                             b43_read32(dev, B43_MMIO_MACCTL)
2067                             | B43_MACCTL_ENABLED);
2068                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2069                             B43_IRQ_MAC_SUSPENDED);
2070                 /* Commit writes */
2071                 b43_read32(dev, B43_MMIO_MACCTL);
2072                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2073                 b43_power_saving_ctl_bits(dev, 0);
2074
2075                 /* Re-enable IRQs. */
2076                 spin_lock_irq(&dev->wl->irq_lock);
2077                 b43_interrupt_enable(dev, dev->irq_savedstate);
2078                 spin_unlock_irq(&dev->wl->irq_lock);
2079         }
2080 }
2081
2082 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2083 void b43_mac_suspend(struct b43_wldev *dev)
2084 {
2085         int i;
2086         u32 tmp;
2087
2088         might_sleep();
2089         B43_WARN_ON(irqs_disabled());
2090         B43_WARN_ON(dev->mac_suspended < 0);
2091
2092         if (dev->mac_suspended == 0) {
2093                 /* Mask IRQs before suspending MAC. Otherwise
2094                  * the MAC stays busy and won't suspend. */
2095                 spin_lock_irq(&dev->wl->irq_lock);
2096                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2097                 spin_unlock_irq(&dev->wl->irq_lock);
2098                 b43_synchronize_irq(dev);
2099                 dev->irq_savedstate = tmp;
2100
2101                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2102                 b43_write32(dev, B43_MMIO_MACCTL,
2103                             b43_read32(dev, B43_MMIO_MACCTL)
2104                             & ~B43_MACCTL_ENABLED);
2105                 /* force pci to flush the write */
2106                 b43_read32(dev, B43_MMIO_MACCTL);
2107                 for (i = 40; i; i--) {
2108                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2109                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2110                                 goto out;
2111                         msleep(1);
2112                 }
2113                 b43err(dev->wl, "MAC suspend failed\n");
2114         }
2115 out:
2116         dev->mac_suspended++;
2117 }
2118
2119 static void b43_adjust_opmode(struct b43_wldev *dev)
2120 {
2121         struct b43_wl *wl = dev->wl;
2122         u32 ctl;
2123         u16 cfp_pretbtt;
2124
2125         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2126         /* Reset status to STA infrastructure mode. */
2127         ctl &= ~B43_MACCTL_AP;
2128         ctl &= ~B43_MACCTL_KEEP_CTL;
2129         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2130         ctl &= ~B43_MACCTL_KEEP_BAD;
2131         ctl &= ~B43_MACCTL_PROMISC;
2132         ctl &= ~B43_MACCTL_BEACPROMISC;
2133         ctl |= B43_MACCTL_INFRA;
2134
2135         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2136                 ctl |= B43_MACCTL_AP;
2137         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2138                 ctl &= ~B43_MACCTL_INFRA;
2139
2140         if (wl->filter_flags & FIF_CONTROL)
2141                 ctl |= B43_MACCTL_KEEP_CTL;
2142         if (wl->filter_flags & FIF_FCSFAIL)
2143                 ctl |= B43_MACCTL_KEEP_BAD;
2144         if (wl->filter_flags & FIF_PLCPFAIL)
2145                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2146         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2147                 ctl |= B43_MACCTL_PROMISC;
2148         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2149                 ctl |= B43_MACCTL_BEACPROMISC;
2150
2151         /* Workaround: On old hardware the HW-MAC-address-filter
2152          * doesn't work properly, so always run promisc in filter
2153          * it in software. */
2154         if (dev->dev->id.revision <= 4)
2155                 ctl |= B43_MACCTL_PROMISC;
2156
2157         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2158
2159         cfp_pretbtt = 2;
2160         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2161                 if (dev->dev->bus->chip_id == 0x4306 &&
2162                     dev->dev->bus->chip_rev == 3)
2163                         cfp_pretbtt = 100;
2164                 else
2165                         cfp_pretbtt = 50;
2166         }
2167         b43_write16(dev, 0x612, cfp_pretbtt);
2168 }
2169
2170 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2171 {
2172         u16 offset;
2173
2174         if (is_ofdm) {
2175                 offset = 0x480;
2176                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2177         } else {
2178                 offset = 0x4C0;
2179                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2180         }
2181         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2182                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2183 }
2184
2185 static void b43_rate_memory_init(struct b43_wldev *dev)
2186 {
2187         switch (dev->phy.type) {
2188         case B43_PHYTYPE_A:
2189         case B43_PHYTYPE_G:
2190         case B43_PHYTYPE_N:
2191                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2192                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2193                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2194                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2195                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2196                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2197                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2198                 if (dev->phy.type == B43_PHYTYPE_A)
2199                         break;
2200                 /* fallthrough */
2201         case B43_PHYTYPE_B:
2202                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2203                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2204                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2205                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2206                 break;
2207         default:
2208                 B43_WARN_ON(1);
2209         }
2210 }
2211
2212 /* Set the TX-Antenna for management frames sent by firmware. */
2213 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2214 {
2215         u16 ant = 0;
2216         u16 tmp;
2217
2218         switch (antenna) {
2219         case B43_ANTENNA0:
2220                 ant |= B43_TXH_PHY_ANT0;
2221                 break;
2222         case B43_ANTENNA1:
2223                 ant |= B43_TXH_PHY_ANT1;
2224                 break;
2225         case B43_ANTENNA2:
2226                 ant |= B43_TXH_PHY_ANT2;
2227                 break;
2228         case B43_ANTENNA3:
2229                 ant |= B43_TXH_PHY_ANT3;
2230                 break;
2231         case B43_ANTENNA_AUTO:
2232                 ant |= B43_TXH_PHY_ANT01AUTO;
2233                 break;
2234         default:
2235                 B43_WARN_ON(1);
2236         }
2237
2238         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2239
2240         /* For Beacons */
2241         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2242         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2243         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2244         /* For ACK/CTS */
2245         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2246         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2247         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2248         /* For Probe Resposes */
2249         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2250         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2251         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2252 }
2253
2254 /* This is the opposite of b43_chip_init() */
2255 static void b43_chip_exit(struct b43_wldev *dev)
2256 {
2257         b43_radio_turn_off(dev, 1);
2258         b43_gpio_cleanup(dev);
2259         /* firmware is released later */
2260 }
2261
2262 /* Initialize the chip
2263  * http://bcm-specs.sipsolutions.net/ChipInit
2264  */
2265 static int b43_chip_init(struct b43_wldev *dev)
2266 {
2267         struct b43_phy *phy = &dev->phy;
2268         int err, tmp;
2269         u32 value32, macctl;
2270         u16 value16;
2271
2272         /* Initialize the MAC control */
2273         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2274         if (dev->phy.gmode)
2275                 macctl |= B43_MACCTL_GMODE;
2276         macctl |= B43_MACCTL_INFRA;
2277         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2278
2279         err = b43_request_firmware(dev);
2280         if (err)
2281                 goto out;
2282         err = b43_upload_microcode(dev);
2283         if (err)
2284                 goto out;       /* firmware is released later */
2285
2286         err = b43_gpio_init(dev);
2287         if (err)
2288                 goto out;       /* firmware is released later */
2289
2290         err = b43_upload_initvals(dev);
2291         if (err)
2292                 goto err_gpio_clean;
2293         b43_radio_turn_on(dev);
2294
2295         b43_write16(dev, 0x03E6, 0x0000);
2296         err = b43_phy_init(dev);
2297         if (err)
2298                 goto err_radio_off;
2299
2300         /* Select initial Interference Mitigation. */
2301         tmp = phy->interfmode;
2302         phy->interfmode = B43_INTERFMODE_NONE;
2303         b43_radio_set_interference_mitigation(dev, tmp);
2304
2305         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2306         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2307
2308         if (phy->type == B43_PHYTYPE_B) {
2309                 value16 = b43_read16(dev, 0x005E);
2310                 value16 |= 0x0004;
2311                 b43_write16(dev, 0x005E, value16);
2312         }
2313         b43_write32(dev, 0x0100, 0x01000000);
2314         if (dev->dev->id.revision < 5)
2315                 b43_write32(dev, 0x010C, 0x01000000);
2316
2317         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2318                     & ~B43_MACCTL_INFRA);
2319         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2320                     | B43_MACCTL_INFRA);
2321
2322         /* Probe Response Timeout value */
2323         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2324         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2325
2326         /* Initially set the wireless operation mode. */
2327         b43_adjust_opmode(dev);
2328
2329         if (dev->dev->id.revision < 3) {
2330                 b43_write16(dev, 0x060E, 0x0000);
2331                 b43_write16(dev, 0x0610, 0x8000);
2332                 b43_write16(dev, 0x0604, 0x0000);
2333                 b43_write16(dev, 0x0606, 0x0200);
2334         } else {
2335                 b43_write32(dev, 0x0188, 0x80000000);
2336                 b43_write32(dev, 0x018C, 0x02000000);
2337         }
2338         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2339         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2340         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2341         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2342         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2343         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2344         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2345
2346         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2347         value32 |= 0x00100000;
2348         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2349
2350         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2351                     dev->dev->bus->chipco.fast_pwrup_delay);
2352
2353         err = 0;
2354         b43dbg(dev->wl, "Chip initialized\n");
2355 out:
2356         return err;
2357
2358 err_radio_off:
2359         b43_radio_turn_off(dev, 1);
2360 err_gpio_clean:
2361         b43_gpio_cleanup(dev);
2362         return err;
2363 }
2364
2365 static void b43_periodic_every120sec(struct b43_wldev *dev)
2366 {
2367         struct b43_phy *phy = &dev->phy;
2368
2369         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2370                 return;
2371
2372         b43_mac_suspend(dev);
2373         b43_lo_g_measure(dev);
2374         b43_mac_enable(dev);
2375         if (b43_has_hardware_pctl(phy))
2376                 b43_lo_g_ctl_mark_all_unused(dev);
2377 }
2378
2379 static void b43_periodic_every60sec(struct b43_wldev *dev)
2380 {
2381         struct b43_phy *phy = &dev->phy;
2382
2383         if (phy->type != B43_PHYTYPE_G)
2384                 return;
2385         if (!b43_has_hardware_pctl(phy))
2386                 b43_lo_g_ctl_mark_all_unused(dev);
2387         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2388                 b43_mac_suspend(dev);
2389                 b43_calc_nrssi_slope(dev);
2390                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2391                         u8 old_chan = phy->channel;
2392
2393                         /* VCO Calibration */
2394                         if (old_chan >= 8)
2395                                 b43_radio_selectchannel(dev, 1, 0);
2396                         else
2397                                 b43_radio_selectchannel(dev, 13, 0);
2398                         b43_radio_selectchannel(dev, old_chan, 0);
2399                 }
2400                 b43_mac_enable(dev);
2401         }
2402 }
2403
2404 static void b43_periodic_every30sec(struct b43_wldev *dev)
2405 {
2406         /* Update device statistics. */
2407         b43_calculate_link_quality(dev);
2408 }
2409
2410 static void b43_periodic_every15sec(struct b43_wldev *dev)
2411 {
2412         struct b43_phy *phy = &dev->phy;
2413
2414         if (phy->type == B43_PHYTYPE_G) {
2415                 //TODO: update_aci_moving_average
2416                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2417                         b43_mac_suspend(dev);
2418                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2419                                 if (0 /*TODO: bunch of conditions */ ) {
2420                                         b43_radio_set_interference_mitigation
2421                                             (dev, B43_INTERFMODE_MANUALWLAN);
2422                                 }
2423                         } else if (1 /*TODO*/) {
2424                                 /*
2425                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2426                                    b43_radio_set_interference_mitigation(dev,
2427                                    B43_INTERFMODE_NONE);
2428                                    }
2429                                  */
2430                         }
2431                         b43_mac_enable(dev);
2432                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2433                            phy->rev == 1) {
2434                         //TODO: implement rev1 workaround
2435                 }
2436         }
2437         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2438         //TODO for APHY (temperature?)
2439
2440         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2441         wmb();
2442 }
2443
2444 static void do_periodic_work(struct b43_wldev *dev)
2445 {
2446         unsigned int state;
2447
2448         state = dev->periodic_state;
2449         if (state % 8 == 0)
2450                 b43_periodic_every120sec(dev);
2451         if (state % 4 == 0)
2452                 b43_periodic_every60sec(dev);
2453         if (state % 2 == 0)
2454                 b43_periodic_every30sec(dev);
2455         b43_periodic_every15sec(dev);
2456 }
2457
2458 /* Periodic work locking policy:
2459  *      The whole periodic work handler is protected by
2460  *      wl->mutex. If another lock is needed somewhere in the
2461  *      pwork callchain, it's aquired in-place, where it's needed.
2462  */
2463 static void b43_periodic_work_handler(struct work_struct *work)
2464 {
2465         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2466                                              periodic_work.work);
2467         struct b43_wl *wl = dev->wl;
2468         unsigned long delay;
2469
2470         mutex_lock(&wl->mutex);
2471
2472         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2473                 goto out;
2474         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2475                 goto out_requeue;
2476
2477         do_periodic_work(dev);
2478
2479         dev->periodic_state++;
2480 out_requeue:
2481         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2482                 delay = msecs_to_jiffies(50);
2483         else
2484                 delay = round_jiffies_relative(HZ * 15);
2485         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2486 out:
2487         mutex_unlock(&wl->mutex);
2488 }
2489
2490 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2491 {
2492         struct delayed_work *work = &dev->periodic_work;
2493
2494         dev->periodic_state = 0;
2495         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2496         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2497 }
2498
2499 /* Check if communication with the device works correctly. */
2500 static int b43_validate_chipaccess(struct b43_wldev *dev)
2501 {
2502         u32 v, backup;
2503
2504         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2505
2506         /* Check for read/write and endianness problems. */
2507         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2508         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2509                 goto error;
2510         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2511         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2512                 goto error;
2513
2514         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2515
2516         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2517                 /* The 32bit register shadows the two 16bit registers
2518                  * with update sideeffects. Validate this. */
2519                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2520                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2521                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2522                         goto error;
2523                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2524                         goto error;
2525         }
2526         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2527
2528         v = b43_read32(dev, B43_MMIO_MACCTL);
2529         v |= B43_MACCTL_GMODE;
2530         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2531                 goto error;
2532
2533         return 0;
2534 error:
2535         b43err(dev->wl, "Failed to validate the chipaccess\n");
2536         return -ENODEV;
2537 }
2538
2539 static void b43_security_init(struct b43_wldev *dev)
2540 {
2541         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2542         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2543         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2544         /* KTP is a word address, but we address SHM bytewise.
2545          * So multiply by two.
2546          */
2547         dev->ktp *= 2;
2548         if (dev->dev->id.revision >= 5) {
2549                 /* Number of RCMTA address slots */
2550                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2551         }
2552         b43_clear_keys(dev);
2553 }
2554
2555 static int b43_rng_read(struct hwrng *rng, u32 * data)
2556 {
2557         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2558         unsigned long flags;
2559
2560         /* Don't take wl->mutex here, as it could deadlock with
2561          * hwrng internal locking. It's not needed to take
2562          * wl->mutex here, anyway. */
2563
2564         spin_lock_irqsave(&wl->irq_lock, flags);
2565         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2566         spin_unlock_irqrestore(&wl->irq_lock, flags);
2567
2568         return (sizeof(u16));
2569 }
2570
2571 static void b43_rng_exit(struct b43_wl *wl)
2572 {
2573         if (wl->rng_initialized)
2574                 hwrng_unregister(&wl->rng);
2575 }
2576
2577 static int b43_rng_init(struct b43_wl *wl)
2578 {
2579         int err;
2580
2581         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2582                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2583         wl->rng.name = wl->rng_name;
2584         wl->rng.data_read = b43_rng_read;
2585         wl->rng.priv = (unsigned long)wl;
2586         wl->rng_initialized = 1;
2587         err = hwrng_register(&wl->rng);
2588         if (err) {
2589                 wl->rng_initialized = 0;
2590                 b43err(wl, "Failed to register the random "
2591                        "number generator (%d)\n", err);
2592         }
2593
2594         return err;
2595 }
2596
2597 static int b43_op_tx(struct ieee80211_hw *hw,
2598                      struct sk_buff *skb,
2599                      struct ieee80211_tx_control *ctl)
2600 {
2601         struct b43_wl *wl = hw_to_b43_wl(hw);
2602         struct b43_wldev *dev = wl->current_dev;
2603         int err = -ENODEV;
2604
2605         if (unlikely(!dev))
2606                 goto out;
2607         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2608                 goto out;
2609         /* DMA-TX is done without a global lock. */
2610         err = b43_dma_tx(dev, skb, ctl);
2611 out:
2612         if (unlikely(err))
2613                 return NETDEV_TX_BUSY;
2614         return NETDEV_TX_OK;
2615 }
2616
2617 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2618                           int queue,
2619                           const struct ieee80211_tx_queue_params *params)
2620 {
2621         return 0;
2622 }
2623
2624 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2625                                struct ieee80211_tx_queue_stats *stats)
2626 {
2627         struct b43_wl *wl = hw_to_b43_wl(hw);
2628         struct b43_wldev *dev = wl->current_dev;
2629         unsigned long flags;
2630         int err = -ENODEV;
2631
2632         if (!dev)
2633                 goto out;
2634         spin_lock_irqsave(&wl->irq_lock, flags);
2635         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2636                 b43_dma_get_tx_stats(dev, stats);
2637                 err = 0;
2638         }
2639         spin_unlock_irqrestore(&wl->irq_lock, flags);
2640 out:
2641         return err;
2642 }
2643
2644 static int b43_op_get_stats(struct ieee80211_hw *hw,
2645                             struct ieee80211_low_level_stats *stats)
2646 {
2647         struct b43_wl *wl = hw_to_b43_wl(hw);
2648         unsigned long flags;
2649
2650         spin_lock_irqsave(&wl->irq_lock, flags);
2651         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2652         spin_unlock_irqrestore(&wl->irq_lock, flags);
2653
2654         return 0;
2655 }
2656
2657 static const char *phymode_to_string(unsigned int phymode)
2658 {
2659         switch (phymode) {
2660         case B43_PHYMODE_A:
2661                 return "A";
2662         case B43_PHYMODE_B:
2663                 return "B";
2664         case B43_PHYMODE_G:
2665                 return "G";
2666         default:
2667                 B43_WARN_ON(1);
2668         }
2669         return "";
2670 }
2671
2672 static int find_wldev_for_phymode(struct b43_wl *wl,
2673                                   unsigned int phymode,
2674                                   struct b43_wldev **dev, bool * gmode)
2675 {
2676         struct b43_wldev *d;
2677
2678         list_for_each_entry(d, &wl->devlist, list) {
2679                 if (d->phy.possible_phymodes & phymode) {
2680                         /* Ok, this device supports the PHY-mode.
2681                          * Now figure out how the gmode bit has to be
2682                          * set to support it. */
2683                         if (phymode == B43_PHYMODE_A)
2684                                 *gmode = 0;
2685                         else
2686                                 *gmode = 1;
2687                         *dev = d;
2688
2689                         return 0;
2690                 }
2691         }
2692
2693         return -ESRCH;
2694 }
2695
2696 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2697 {
2698         struct ssb_device *sdev = dev->dev;
2699         u32 tmslow;
2700
2701         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2702         tmslow &= ~B43_TMSLOW_GMODE;
2703         tmslow |= B43_TMSLOW_PHYRESET;
2704         tmslow |= SSB_TMSLOW_FGC;
2705         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2706         msleep(1);
2707
2708         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2709         tmslow &= ~SSB_TMSLOW_FGC;
2710         tmslow |= B43_TMSLOW_PHYRESET;
2711         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2712         msleep(1);
2713 }
2714
2715 /* Expects wl->mutex locked */
2716 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2717 {
2718         struct b43_wldev *up_dev;
2719         struct b43_wldev *down_dev;
2720         int err;
2721         bool gmode = 0;
2722         int prev_status;
2723
2724         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2725         if (err) {
2726                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2727                        phymode_to_string(new_mode));
2728                 return err;
2729         }
2730         if ((up_dev == wl->current_dev) &&
2731             (!!wl->current_dev->phy.gmode == !!gmode)) {
2732                 /* This device is already running. */
2733                 return 0;
2734         }
2735         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2736                phymode_to_string(new_mode));
2737         down_dev = wl->current_dev;
2738
2739         prev_status = b43_status(down_dev);
2740         /* Shutdown the currently running core. */
2741         if (prev_status >= B43_STAT_STARTED)
2742                 b43_wireless_core_stop(down_dev);
2743         if (prev_status >= B43_STAT_INITIALIZED)
2744                 b43_wireless_core_exit(down_dev);
2745
2746         if (down_dev != up_dev) {
2747                 /* We switch to a different core, so we put PHY into
2748                  * RESET on the old core. */
2749                 b43_put_phy_into_reset(down_dev);
2750         }
2751
2752         /* Now start the new core. */
2753         up_dev->phy.gmode = gmode;
2754         if (prev_status >= B43_STAT_INITIALIZED) {
2755                 err = b43_wireless_core_init(up_dev);
2756                 if (err) {
2757                         b43err(wl, "Fatal: Could not initialize device for "
2758                                "newly selected %s-PHY mode\n",
2759                                phymode_to_string(new_mode));
2760                         goto init_failure;
2761                 }
2762         }
2763         if (prev_status >= B43_STAT_STARTED) {
2764                 err = b43_wireless_core_start(up_dev);
2765                 if (err) {
2766                         b43err(wl, "Fatal: Coult not start device for "
2767                                "newly selected %s-PHY mode\n",
2768                                phymode_to_string(new_mode));
2769                         b43_wireless_core_exit(up_dev);
2770                         goto init_failure;
2771                 }
2772         }
2773         B43_WARN_ON(b43_status(up_dev) != prev_status);
2774
2775         wl->current_dev = up_dev;
2776
2777         return 0;
2778       init_failure:
2779         /* Whoops, failed to init the new core. No core is operating now. */
2780         wl->current_dev = NULL;
2781         return err;
2782 }
2783
2784 /* Check if the use of the antenna that ieee80211 told us to
2785  * use is possible. This will fall back to DEFAULT.
2786  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2787 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2788                                   u8 antenna_nr)
2789 {
2790         u8 antenna_mask;
2791
2792         if (antenna_nr == 0) {
2793                 /* Zero means "use default antenna". That's always OK. */
2794                 return 0;
2795         }
2796
2797         /* Get the mask of available antennas. */
2798         if (dev->phy.gmode)
2799                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2800         else
2801                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2802
2803         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2804                 /* This antenna is not available. Fall back to default. */
2805                 return 0;
2806         }
2807
2808         return antenna_nr;
2809 }
2810
2811 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2812 {
2813         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2814         switch (antenna) {
2815         case 0:         /* default/diversity */
2816                 return B43_ANTENNA_DEFAULT;
2817         case 1:         /* Antenna 0 */
2818                 return B43_ANTENNA0;
2819         case 2:         /* Antenna 1 */
2820                 return B43_ANTENNA1;
2821         case 3:         /* Antenna 2 */
2822                 return B43_ANTENNA2;
2823         case 4:         /* Antenna 3 */
2824                 return B43_ANTENNA3;
2825         default:
2826                 return B43_ANTENNA_DEFAULT;
2827         }
2828 }
2829
2830 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2831 {
2832         struct b43_wl *wl = hw_to_b43_wl(hw);
2833         struct b43_wldev *dev;
2834         struct b43_phy *phy;
2835         unsigned long flags;
2836         unsigned int new_phymode = 0xFFFF;
2837         int antenna;
2838         int err = 0;
2839         u32 savedirqs;
2840
2841         mutex_lock(&wl->mutex);
2842
2843         /* Switch the PHY mode (if necessary). */
2844         switch (conf->channel->band) {
2845         case IEEE80211_BAND_5GHZ:
2846                 new_phymode = B43_PHYMODE_A;
2847                 break;
2848         case IEEE80211_BAND_2GHZ:
2849                 new_phymode = B43_PHYMODE_G;
2850                 break;
2851         default:
2852                 B43_WARN_ON(1);
2853         }
2854         err = b43_switch_phymode(wl, new_phymode);
2855         if (err)
2856                 goto out_unlock_mutex;
2857         dev = wl->current_dev;
2858         phy = &dev->phy;
2859
2860         /* Disable IRQs while reconfiguring the device.
2861          * This makes it possible to drop the spinlock throughout
2862          * the reconfiguration process. */
2863         spin_lock_irqsave(&wl->irq_lock, flags);
2864         if (b43_status(dev) < B43_STAT_STARTED) {
2865                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2866                 goto out_unlock_mutex;
2867         }
2868         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2869         spin_unlock_irqrestore(&wl->irq_lock, flags);
2870         b43_synchronize_irq(dev);
2871
2872         /* Switch to the requested channel.
2873          * The firmware takes care of races with the TX handler. */
2874         if (conf->channel->hw_value != phy->channel)
2875                 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
2876
2877         /* Enable/Disable ShortSlot timing. */
2878         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2879             dev->short_slot) {
2880                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2881                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2882                         b43_short_slot_timing_enable(dev);
2883                 else
2884                         b43_short_slot_timing_disable(dev);
2885         }
2886
2887         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2888
2889         /* Adjust the desired TX power level. */
2890         if (conf->power_level != 0) {
2891                 if (conf->power_level != phy->power_level) {
2892                         phy->power_level = conf->power_level;
2893                         b43_phy_xmitpower(dev);
2894                 }
2895         }
2896
2897         /* Antennas for RX and management frame TX. */
2898         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2899         b43_mgmtframe_txantenna(dev, antenna);
2900         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2901         b43_set_rx_antenna(dev, antenna);
2902
2903         /* Update templates for AP mode. */
2904         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2905                 b43_set_beacon_int(dev, conf->beacon_int);
2906
2907         if (!!conf->radio_enabled != phy->radio_on) {
2908                 if (conf->radio_enabled) {
2909                         b43_radio_turn_on(dev);
2910                         b43info(dev->wl, "Radio turned on by software\n");
2911                         if (!dev->radio_hw_enable) {
2912                                 b43info(dev->wl, "The hardware RF-kill button "
2913                                         "still turns the radio physically off. "
2914                                         "Press the button to turn it on.\n");
2915                         }
2916                 } else {
2917                         b43_radio_turn_off(dev, 0);
2918                         b43info(dev->wl, "Radio turned off by software\n");
2919                 }
2920         }
2921
2922         spin_lock_irqsave(&wl->irq_lock, flags);
2923         b43_interrupt_enable(dev, savedirqs);
2924         mmiowb();
2925         spin_unlock_irqrestore(&wl->irq_lock, flags);
2926       out_unlock_mutex:
2927         mutex_unlock(&wl->mutex);
2928
2929         return err;
2930 }
2931
2932 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2933                            const u8 *local_addr, const u8 *addr,
2934                            struct ieee80211_key_conf *key)
2935 {
2936         struct b43_wl *wl = hw_to_b43_wl(hw);
2937         struct b43_wldev *dev;
2938         unsigned long flags;
2939         u8 algorithm;
2940         u8 index;
2941         int err;
2942         DECLARE_MAC_BUF(mac);
2943
2944         if (modparam_nohwcrypt)
2945                 return -ENOSPC; /* User disabled HW-crypto */
2946
2947         mutex_lock(&wl->mutex);
2948         spin_lock_irqsave(&wl->irq_lock, flags);
2949
2950         dev = wl->current_dev;
2951         err = -ENODEV;
2952         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2953                 goto out_unlock;
2954
2955         err = -EINVAL;
2956         switch (key->alg) {
2957         case ALG_WEP:
2958                 if (key->keylen == 5)
2959                         algorithm = B43_SEC_ALGO_WEP40;
2960                 else
2961                         algorithm = B43_SEC_ALGO_WEP104;
2962                 break;
2963         case ALG_TKIP:
2964                 algorithm = B43_SEC_ALGO_TKIP;
2965                 break;
2966         case ALG_CCMP:
2967                 algorithm = B43_SEC_ALGO_AES;
2968                 break;
2969         default:
2970                 B43_WARN_ON(1);
2971                 goto out_unlock;
2972         }
2973         index = (u8) (key->keyidx);
2974         if (index > 3)
2975                 goto out_unlock;
2976
2977         switch (cmd) {
2978         case SET_KEY:
2979                 if (algorithm == B43_SEC_ALGO_TKIP) {
2980                         /* FIXME: No TKIP hardware encryption for now. */
2981                         err = -EOPNOTSUPP;
2982                         goto out_unlock;
2983                 }
2984
2985                 if (is_broadcast_ether_addr(addr)) {
2986                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2987                         err = b43_key_write(dev, index, algorithm,
2988                                             key->key, key->keylen, NULL, key);
2989                 } else {
2990                         /*
2991                          * either pairwise key or address is 00:00:00:00:00:00
2992                          * for transmit-only keys
2993                          */
2994                         err = b43_key_write(dev, -1, algorithm,
2995                                             key->key, key->keylen, addr, key);
2996                 }
2997                 if (err)
2998                         goto out_unlock;
2999
3000                 if (algorithm == B43_SEC_ALGO_WEP40 ||
3001                     algorithm == B43_SEC_ALGO_WEP104) {
3002                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3003                 } else {
3004                         b43_hf_write(dev,
3005                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3006                 }
3007                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3008                 break;
3009         case DISABLE_KEY: {
3010                 err = b43_key_clear(dev, key->hw_key_idx);
3011                 if (err)
3012                         goto out_unlock;
3013                 break;
3014         }
3015         default:
3016                 B43_WARN_ON(1);
3017         }
3018 out_unlock:
3019         spin_unlock_irqrestore(&wl->irq_lock, flags);
3020         mutex_unlock(&wl->mutex);
3021         if (!err) {
3022                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3023                        "mac: %s\n",
3024                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3025                        print_mac(mac, addr));
3026         }
3027         return err;
3028 }
3029
3030 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3031                                     unsigned int changed, unsigned int *fflags,
3032                                     int mc_count, struct dev_addr_list *mc_list)
3033 {
3034         struct b43_wl *wl = hw_to_b43_wl(hw);
3035         struct b43_wldev *dev = wl->current_dev;
3036         unsigned long flags;
3037
3038         if (!dev) {
3039                 *fflags = 0;
3040                 return;
3041         }
3042
3043         spin_lock_irqsave(&wl->irq_lock, flags);
3044         *fflags &= FIF_PROMISC_IN_BSS |
3045                   FIF_ALLMULTI |
3046                   FIF_FCSFAIL |
3047                   FIF_PLCPFAIL |
3048                   FIF_CONTROL |
3049                   FIF_OTHER_BSS |
3050                   FIF_BCN_PRBRESP_PROMISC;
3051
3052         changed &= FIF_PROMISC_IN_BSS |
3053                    FIF_ALLMULTI |
3054                    FIF_FCSFAIL |
3055                    FIF_PLCPFAIL |
3056                    FIF_CONTROL |
3057                    FIF_OTHER_BSS |
3058                    FIF_BCN_PRBRESP_PROMISC;
3059
3060         wl->filter_flags = *fflags;
3061
3062         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3063                 b43_adjust_opmode(dev);
3064         spin_unlock_irqrestore(&wl->irq_lock, flags);
3065 }
3066
3067 static int b43_op_config_interface(struct ieee80211_hw *hw,
3068                                    struct ieee80211_vif *vif,
3069                                    struct ieee80211_if_conf *conf)
3070 {
3071         struct b43_wl *wl = hw_to_b43_wl(hw);
3072         struct b43_wldev *dev = wl->current_dev;
3073         unsigned long flags;
3074
3075         if (!dev)
3076                 return -ENODEV;
3077         mutex_lock(&wl->mutex);
3078         spin_lock_irqsave(&wl->irq_lock, flags);
3079         B43_WARN_ON(wl->vif != vif);
3080         if (conf->bssid)
3081                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3082         else
3083                 memset(wl->bssid, 0, ETH_ALEN);
3084         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3085                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3086                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3087                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3088                         if (conf->beacon)
3089                                 b43_update_templates(wl, conf->beacon);
3090                 }
3091                 b43_write_mac_bssid_templates(dev);
3092         }
3093         spin_unlock_irqrestore(&wl->irq_lock, flags);
3094         mutex_unlock(&wl->mutex);
3095
3096         return 0;
3097 }
3098
3099 /* Locking: wl->mutex */
3100 static void b43_wireless_core_stop(struct b43_wldev *dev)
3101 {
3102         struct b43_wl *wl = dev->wl;
3103         unsigned long flags;
3104
3105         if (b43_status(dev) < B43_STAT_STARTED)
3106                 return;
3107
3108         /* Disable and sync interrupts. We must do this before than
3109          * setting the status to INITIALIZED, as the interrupt handler
3110          * won't care about IRQs then. */
3111         spin_lock_irqsave(&wl->irq_lock, flags);
3112         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3113         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3114         spin_unlock_irqrestore(&wl->irq_lock, flags);
3115         b43_synchronize_irq(dev);
3116
3117         b43_set_status(dev, B43_STAT_INITIALIZED);
3118
3119         mutex_unlock(&wl->mutex);
3120         /* Must unlock as it would otherwise deadlock. No races here.
3121          * Cancel the possibly running self-rearming periodic work. */
3122         cancel_delayed_work_sync(&dev->periodic_work);
3123         mutex_lock(&wl->mutex);
3124
3125         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3126
3127         b43_mac_suspend(dev);
3128         free_irq(dev->dev->irq, dev);
3129         b43dbg(wl, "Wireless interface stopped\n");
3130 }
3131
3132 /* Locking: wl->mutex */
3133 static int b43_wireless_core_start(struct b43_wldev *dev)
3134 {
3135         int err;
3136
3137         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3138
3139         drain_txstatus_queue(dev);
3140         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3141                           IRQF_SHARED, KBUILD_MODNAME, dev);
3142         if (err) {
3143                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3144                 goto out;
3145         }
3146
3147         /* We are ready to run. */
3148         b43_set_status(dev, B43_STAT_STARTED);
3149
3150         /* Start data flow (TX/RX). */
3151         b43_mac_enable(dev);
3152         b43_interrupt_enable(dev, dev->irq_savedstate);
3153         ieee80211_start_queues(dev->wl->hw);
3154
3155         /* Start maintainance work */
3156         b43_periodic_tasks_setup(dev);
3157
3158         b43dbg(dev->wl, "Wireless interface started\n");
3159       out:
3160         return err;
3161 }
3162
3163 /* Get PHY and RADIO versioning numbers */
3164 static int b43_phy_versioning(struct b43_wldev *dev)
3165 {
3166         struct b43_phy *phy = &dev->phy;
3167         u32 tmp;
3168         u8 analog_type;
3169         u8 phy_type;
3170         u8 phy_rev;
3171         u16 radio_manuf;
3172         u16 radio_ver;
3173         u16 radio_rev;
3174         int unsupported = 0;
3175
3176         /* Get PHY versioning */
3177         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3178         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3179         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3180         phy_rev = (tmp & B43_PHYVER_VERSION);
3181         switch (phy_type) {
3182         case B43_PHYTYPE_A:
3183                 if (phy_rev >= 4)
3184                         unsupported = 1;
3185                 break;
3186         case B43_PHYTYPE_B:
3187                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3188                     && phy_rev != 7)
3189                         unsupported = 1;
3190                 break;
3191         case B43_PHYTYPE_G:
3192                 if (phy_rev > 9)
3193                         unsupported = 1;
3194                 break;
3195 #ifdef CONFIG_B43_NPHY
3196         case B43_PHYTYPE_N:
3197                 if (phy_rev > 1)
3198                         unsupported = 1;
3199                 break;
3200 #endif
3201         default:
3202                 unsupported = 1;
3203         };
3204         if (unsupported) {
3205                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3206                        "(Analog %u, Type %u, Revision %u)\n",
3207                        analog_type, phy_type, phy_rev);
3208                 return -EOPNOTSUPP;
3209         }
3210         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3211                analog_type, phy_type, phy_rev);
3212
3213         /* Get RADIO versioning */
3214         if (dev->dev->bus->chip_id == 0x4317) {
3215                 if (dev->dev->bus->chip_rev == 0)
3216                         tmp = 0x3205017F;
3217                 else if (dev->dev->bus->chip_rev == 1)
3218                         tmp = 0x4205017F;
3219                 else
3220                         tmp = 0x5205017F;
3221         } else {
3222                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3223                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3224                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3225                 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3226         }
3227         radio_manuf = (tmp & 0x00000FFF);
3228         radio_ver = (tmp & 0x0FFFF000) >> 12;
3229         radio_rev = (tmp & 0xF0000000) >> 28;
3230         if (radio_manuf != 0x17F /* Broadcom */)
3231                 unsupported = 1;
3232         switch (phy_type) {
3233         case B43_PHYTYPE_A:
3234                 if (radio_ver != 0x2060)
3235                         unsupported = 1;
3236                 if (radio_rev != 1)
3237                         unsupported = 1;
3238                 if (radio_manuf != 0x17F)
3239                         unsupported = 1;
3240                 break;
3241         case B43_PHYTYPE_B:
3242                 if ((radio_ver & 0xFFF0) != 0x2050)
3243                         unsupported = 1;
3244                 break;
3245         case B43_PHYTYPE_G:
3246                 if (radio_ver != 0x2050)
3247                         unsupported = 1;
3248                 break;
3249         case B43_PHYTYPE_N:
3250                 if (radio_ver != 0x2055)
3251                         unsupported = 1;
3252                 break;
3253         default:
3254                 B43_WARN_ON(1);
3255         }
3256         if (unsupported) {
3257                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3258                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3259                        radio_manuf, radio_ver, radio_rev);
3260                 return -EOPNOTSUPP;
3261         }
3262         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3263                radio_manuf, radio_ver, radio_rev);
3264
3265         phy->radio_manuf = radio_manuf;
3266         phy->radio_ver = radio_ver;
3267         phy->radio_rev = radio_rev;
3268
3269         phy->analog = analog_type;
3270         phy->type = phy_type;
3271         phy->rev = phy_rev;
3272
3273         return 0;
3274 }
3275
3276 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3277                                       struct b43_phy *phy)
3278 {
3279         struct b43_txpower_lo_control *lo;
3280         int i;
3281
3282         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3283         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3284
3285         phy->aci_enable = 0;
3286         phy->aci_wlan_automatic = 0;
3287         phy->aci_hw_rssi = 0;
3288
3289         phy->radio_off_context.valid = 0;
3290
3291         lo = phy->lo_control;
3292         if (lo) {
3293                 memset(lo, 0, sizeof(*(phy->lo_control)));
3294                 lo->rebuild = 1;
3295                 lo->tx_bias = 0xFF;
3296         }
3297         phy->max_lb_gain = 0;
3298         phy->trsw_rx_gain = 0;
3299         phy->txpwr_offset = 0;
3300
3301         /* NRSSI */
3302         phy->nrssislope = 0;
3303         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3304                 phy->nrssi[i] = -1000;
3305         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3306                 phy->nrssi_lt[i] = i;
3307
3308         phy->lofcal = 0xFFFF;
3309         phy->initval = 0xFFFF;
3310
3311         phy->interfmode = B43_INTERFMODE_NONE;
3312         phy->channel = 0xFF;
3313
3314         phy->hardware_power_control = !!modparam_hwpctl;
3315
3316         /* PHY TX errors counter. */
3317         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3318
3319         /* OFDM-table address caching. */
3320         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3321 }
3322
3323 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3324 {
3325         dev->dfq_valid = 0;
3326
3327         /* Assume the radio is enabled. If it's not enabled, the state will
3328          * immediately get fixed on the first periodic work run. */
3329         dev->radio_hw_enable = 1;
3330
3331         /* Stats */
3332         memset(&dev->stats, 0, sizeof(dev->stats));
3333
3334         setup_struct_phy_for_init(dev, &dev->phy);
3335
3336         /* IRQ related flags */
3337         dev->irq_reason = 0;
3338         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3339         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3340
3341         dev->mac_suspended = 1;
3342
3343         /* Noise calculation context */
3344         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3345 }
3346
3347 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3348 {
3349         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3350         u32 hf;
3351
3352         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3353                 return;
3354         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3355                 return;
3356
3357         hf = b43_hf_read(dev);
3358         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3359                 hf |= B43_HF_BTCOEXALT;
3360         else
3361                 hf |= B43_HF_BTCOEX;
3362         b43_hf_write(dev, hf);
3363         //TODO
3364 }
3365
3366 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3367 {                               //TODO
3368 }
3369
3370 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3371 {
3372 #ifdef CONFIG_SSB_DRIVER_PCICORE
3373         struct ssb_bus *bus = dev->dev->bus;
3374         u32 tmp;
3375
3376         if (bus->pcicore.dev &&
3377             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3378             bus->pcicore.dev->id.revision <= 5) {
3379                 /* IMCFGLO timeouts workaround. */
3380                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3381                 tmp &= ~SSB_IMCFGLO_REQTO;
3382                 tmp &= ~SSB_IMCFGLO_SERTO;
3383                 switch (bus->bustype) {
3384                 case SSB_BUSTYPE_PCI:
3385                 case SSB_BUSTYPE_PCMCIA:
3386                         tmp |= 0x32;
3387                         break;
3388                 case SSB_BUSTYPE_SSB:
3389                         tmp |= 0x53;
3390                         break;
3391                 }
3392                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3393         }
3394 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3395 }
3396
3397 /* Write the short and long frame retry limit values. */
3398 static void b43_set_retry_limits(struct b43_wldev *dev,
3399                                  unsigned int short_retry,
3400                                  unsigned int long_retry)
3401 {
3402         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3403          * the chip-internal counter. */
3404         short_retry = min(short_retry, (unsigned int)0xF);
3405         long_retry = min(long_retry, (unsigned int)0xF);
3406
3407         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3408                         short_retry);
3409         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3410                         long_retry);
3411 }
3412
3413 /* Shutdown a wireless core */
3414 /* Locking: wl->mutex */
3415 static void b43_wireless_core_exit(struct b43_wldev *dev)
3416 {
3417         struct b43_phy *phy = &dev->phy;
3418         u32 macctl;
3419
3420         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3421         if (b43_status(dev) != B43_STAT_INITIALIZED)
3422                 return;
3423         b43_set_status(dev, B43_STAT_UNINIT);
3424
3425         /* Stop the microcode PSM. */
3426         macctl = b43_read32(dev, B43_MMIO_MACCTL);
3427         macctl &= ~B43_MACCTL_PSM_RUN;
3428         macctl |= B43_MACCTL_PSM_JMP0;
3429         b43_write32(dev, B43_MMIO_MACCTL, macctl);
3430
3431         b43_leds_exit(dev);
3432         b43_rng_exit(dev->wl);
3433         b43_dma_free(dev);
3434         b43_chip_exit(dev);
3435         b43_radio_turn_off(dev, 1);
3436         b43_switch_analog(dev, 0);
3437         if (phy->dyn_tssi_tbl)
3438                 kfree(phy->tssi2dbm);
3439         kfree(phy->lo_control);
3440         phy->lo_control = NULL;
3441         if (dev->wl->current_beacon) {
3442                 dev_kfree_skb_any(dev->wl->current_beacon);
3443                 dev->wl->current_beacon = NULL;
3444         }
3445
3446         ssb_device_disable(dev->dev, 0);
3447         ssb_bus_may_powerdown(dev->dev->bus);
3448 }
3449
3450 /* Initialize a wireless core */
3451 static int b43_wireless_core_init(struct b43_wldev *dev)
3452 {
3453         struct b43_wl *wl = dev->wl;
3454         struct ssb_bus *bus = dev->dev->bus;
3455         struct ssb_sprom *sprom = &bus->sprom;
3456         struct b43_phy *phy = &dev->phy;
3457         int err;
3458         u32 hf, tmp;
3459
3460         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3461
3462         err = ssb_bus_powerup(bus, 0);
3463         if (err)
3464                 goto out;
3465         if (!ssb_device_is_enabled(dev->dev)) {
3466                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3467                 b43_wireless_core_reset(dev, tmp);
3468         }
3469
3470         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3471                 phy->lo_control =
3472                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3473                 if (!phy->lo_control) {
3474                         err = -ENOMEM;
3475                         goto err_busdown;
3476                 }
3477         }
3478         setup_struct_wldev_for_init(dev);
3479
3480         err = b43_phy_init_tssi2dbm_table(dev);
3481         if (err)
3482                 goto err_kfree_lo_control;
3483
3484         /* Enable IRQ routing to this device. */
3485         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3486
3487         b43_imcfglo_timeouts_workaround(dev);
3488         b43_bluetooth_coext_disable(dev);
3489         b43_phy_early_init(dev);
3490         err = b43_chip_init(dev);
3491         if (err)
3492                 goto err_kfree_tssitbl;
3493         b43_shm_write16(dev, B43_SHM_SHARED,
3494                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3495         hf = b43_hf_read(dev);
3496         if (phy->type == B43_PHYTYPE_G) {
3497                 hf |= B43_HF_SYMW;
3498                 if (phy->rev == 1)
3499                         hf |= B43_HF_GDCW;
3500                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3501                         hf |= B43_HF_OFDMPABOOST;
3502         } else if (phy->type == B43_PHYTYPE_B) {
3503                 hf |= B43_HF_SYMW;
3504                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3505                         hf &= ~B43_HF_GDCW;
3506         }
3507         b43_hf_write(dev, hf);
3508
3509         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3510                              B43_DEFAULT_LONG_RETRY_LIMIT);
3511         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3512         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3513
3514         /* Disable sending probe responses from firmware.
3515          * Setting the MaxTime to one usec will always trigger
3516          * a timeout, so we never send any probe resp.
3517          * A timeout of zero is infinite. */
3518         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3519
3520         b43_rate_memory_init(dev);
3521
3522         /* Minimum Contention Window */
3523         if (phy->type == B43_PHYTYPE_B) {
3524                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3525         } else {
3526                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3527         }
3528         /* Maximum Contention Window */
3529         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3530
3531         err = b43_dma_init(dev);
3532         if (err)
3533                 goto err_chip_exit;
3534         b43_qos_init(dev);
3535
3536 //FIXME
3537 #if 1
3538         b43_write16(dev, 0x0612, 0x0050);
3539         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3540         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3541 #endif
3542
3543         b43_bluetooth_coext_enable(dev);
3544
3545         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3546         b43_upload_card_macaddress(dev);
3547         b43_security_init(dev);
3548         b43_rng_init(wl);
3549
3550         b43_set_status(dev, B43_STAT_INITIALIZED);
3551
3552         b43_leds_init(dev);
3553 out:
3554         return err;
3555
3556       err_chip_exit:
3557         b43_chip_exit(dev);
3558       err_kfree_tssitbl:
3559         if (phy->dyn_tssi_tbl)
3560                 kfree(phy->tssi2dbm);
3561       err_kfree_lo_control:
3562         kfree(phy->lo_control);
3563         phy->lo_control = NULL;
3564       err_busdown:
3565         ssb_bus_may_powerdown(bus);
3566         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3567         return err;
3568 }
3569
3570 static int b43_op_add_interface(struct ieee80211_hw *hw,
3571                                 struct ieee80211_if_init_conf *conf)
3572 {
3573         struct b43_wl *wl = hw_to_b43_wl(hw);
3574         struct b43_wldev *dev;
3575         unsigned long flags;
3576         int err = -EOPNOTSUPP;
3577
3578         /* TODO: allow WDS/AP devices to coexist */
3579
3580         if (conf->type != IEEE80211_IF_TYPE_AP &&
3581             conf->type != IEEE80211_IF_TYPE_STA &&
3582             conf->type != IEEE80211_IF_TYPE_WDS &&
3583             conf->type != IEEE80211_IF_TYPE_IBSS)
3584                 return -EOPNOTSUPP;
3585
3586         mutex_lock(&wl->mutex);
3587         if (wl->operating)
3588                 goto out_mutex_unlock;
3589
3590         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3591
3592         dev = wl->current_dev;
3593         wl->operating = 1;
3594         wl->vif = conf->vif;
3595         wl->if_type = conf->type;
3596         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3597
3598         spin_lock_irqsave(&wl->irq_lock, flags);
3599         b43_adjust_opmode(dev);
3600         b43_upload_card_macaddress(dev);
3601         spin_unlock_irqrestore(&wl->irq_lock, flags);
3602
3603         err = 0;
3604  out_mutex_unlock:
3605         mutex_unlock(&wl->mutex);
3606
3607         return err;
3608 }
3609
3610 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3611                                     struct ieee80211_if_init_conf *conf)
3612 {
3613         struct b43_wl *wl = hw_to_b43_wl(hw);
3614         struct b43_wldev *dev = wl->current_dev;
3615         unsigned long flags;
3616
3617         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3618
3619         mutex_lock(&wl->mutex);
3620
3621         B43_WARN_ON(!wl->operating);
3622         B43_WARN_ON(wl->vif != conf->vif);
3623         wl->vif = NULL;
3624
3625         wl->operating = 0;
3626
3627         spin_lock_irqsave(&wl->irq_lock, flags);
3628         b43_adjust_opmode(dev);
3629         memset(wl->mac_addr, 0, ETH_ALEN);
3630         b43_upload_card_macaddress(dev);
3631         spin_unlock_irqrestore(&wl->irq_lock, flags);
3632
3633         mutex_unlock(&wl->mutex);
3634 }
3635
3636 static int b43_op_start(struct ieee80211_hw *hw)
3637 {
3638         struct b43_wl *wl = hw_to_b43_wl(hw);
3639         struct b43_wldev *dev = wl->current_dev;
3640         int did_init = 0;
3641         int err = 0;
3642         bool do_rfkill_exit = 0;
3643
3644         /* Kill all old instance specific information to make sure
3645          * the card won't use it in the short timeframe between start
3646          * and mac80211 reconfiguring it. */
3647         memset(wl->bssid, 0, ETH_ALEN);
3648         memset(wl->mac_addr, 0, ETH_ALEN);
3649         wl->filter_flags = 0;
3650         wl->radiotap_enabled = 0;
3651
3652         /* First register RFkill.
3653          * LEDs that are registered later depend on it. */
3654         b43_rfkill_init(dev);
3655
3656         mutex_lock(&wl->mutex);
3657
3658         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3659                 err = b43_wireless_core_init(dev);
3660                 if (err) {
3661                         do_rfkill_exit = 1;
3662                         goto out_mutex_unlock;
3663                 }
3664                 did_init = 1;
3665         }
3666
3667         if (b43_status(dev) < B43_STAT_STARTED) {
3668                 err = b43_wireless_core_start(dev);
3669                 if (err) {
3670                         if (did_init)
3671                                 b43_wireless_core_exit(dev);
3672                         do_rfkill_exit = 1;
3673                         goto out_mutex_unlock;
3674                 }
3675         }
3676
3677  out_mutex_unlock:
3678         mutex_unlock(&wl->mutex);
3679
3680         if (do_rfkill_exit)
3681                 b43_rfkill_exit(dev);
3682
3683         return err;
3684 }
3685
3686 static void b43_op_stop(struct ieee80211_hw *hw)
3687 {
3688         struct b43_wl *wl = hw_to_b43_wl(hw);
3689         struct b43_wldev *dev = wl->current_dev;
3690
3691         b43_rfkill_exit(dev);
3692
3693         mutex_lock(&wl->mutex);
3694         if (b43_status(dev) >= B43_STAT_STARTED)
3695                 b43_wireless_core_stop(dev);
3696         b43_wireless_core_exit(dev);
3697         mutex_unlock(&wl->mutex);
3698 }
3699
3700 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3701                                   u32 short_retry_limit, u32 long_retry_limit)
3702 {
3703         struct b43_wl *wl = hw_to_b43_wl(hw);
3704         struct b43_wldev *dev;
3705         int err = 0;
3706
3707         mutex_lock(&wl->mutex);
3708         dev = wl->current_dev;
3709         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3710                 err = -ENODEV;
3711                 goto out_unlock;
3712         }
3713         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3714 out_unlock:
3715         mutex_unlock(&wl->mutex);
3716
3717         return err;
3718 }
3719
3720 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3721 {
3722         struct b43_wl *wl = hw_to_b43_wl(hw);
3723         struct sk_buff *beacon;
3724         unsigned long flags;
3725
3726         /* We could modify the existing beacon and set the aid bit in
3727          * the TIM field, but that would probably require resizing and
3728          * moving of data within the beacon template.
3729          * Simply request a new beacon and let mac80211 do the hard work. */
3730         beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3731         if (unlikely(!beacon))
3732                 return -ENOMEM;
3733         spin_lock_irqsave(&wl->irq_lock, flags);
3734         b43_update_templates(wl, beacon);
3735         spin_unlock_irqrestore(&wl->irq_lock, flags);
3736
3737         return 0;
3738 }
3739
3740 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3741                                      struct sk_buff *beacon,
3742                                      struct ieee80211_tx_control *ctl)
3743 {
3744         struct b43_wl *wl = hw_to_b43_wl(hw);
3745         unsigned long flags;
3746
3747         spin_lock_irqsave(&wl->irq_lock, flags);
3748         b43_update_templates(wl, beacon);
3749         spin_unlock_irqrestore(&wl->irq_lock, flags);
3750
3751         return 0;
3752 }
3753
3754 static const struct ieee80211_ops b43_hw_ops = {
3755         .tx                     = b43_op_tx,
3756         .conf_tx                = b43_op_conf_tx,
3757         .add_interface          = b43_op_add_interface,
3758         .remove_interface       = b43_op_remove_interface,
3759         .config                 = b43_op_config,
3760         .config_interface       = b43_op_config_interface,
3761         .configure_filter       = b43_op_configure_filter,
3762         .set_key                = b43_op_set_key,
3763         .get_stats              = b43_op_get_stats,
3764         .get_tx_stats           = b43_op_get_tx_stats,
3765         .start                  = b43_op_start,
3766         .stop                   = b43_op_stop,
3767         .set_retry_limit        = b43_op_set_retry_limit,
3768         .set_tim                = b43_op_beacon_set_tim,
3769         .beacon_update          = b43_op_ibss_beacon_update,
3770 };
3771
3772 /* Hard-reset the chip. Do not call this directly.
3773  * Use b43_controller_restart()
3774  */
3775 static void b43_chip_reset(struct work_struct *work)
3776 {
3777         struct b43_wldev *dev =
3778             container_of(work, struct b43_wldev, restart_work);
3779         struct b43_wl *wl = dev->wl;
3780         int err = 0;
3781         int prev_status;
3782
3783         mutex_lock(&wl->mutex);
3784
3785         prev_status = b43_status(dev);
3786         /* Bring the device down... */
3787         if (prev_status >= B43_STAT_STARTED)
3788                 b43_wireless_core_stop(dev);
3789         if (prev_status >= B43_STAT_INITIALIZED)
3790                 b43_wireless_core_exit(dev);
3791
3792         /* ...and up again. */
3793         if (prev_status >= B43_STAT_INITIALIZED) {
3794                 err = b43_wireless_core_init(dev);
3795                 if (err)
3796                         goto out;
3797         }
3798         if (prev_status >= B43_STAT_STARTED) {
3799                 err = b43_wireless_core_start(dev);
3800                 if (err) {
3801                         b43_wireless_core_exit(dev);
3802                         goto out;
3803                 }
3804         }
3805       out:
3806         mutex_unlock(&wl->mutex);
3807         if (err)
3808                 b43err(wl, "Controller restart FAILED\n");
3809         else
3810                 b43info(wl, "Controller restarted\n");
3811 }
3812
3813 static int b43_setup_modes(struct b43_wldev *dev,
3814                            bool have_2ghz_phy, bool have_5ghz_phy)
3815 {
3816         struct ieee80211_hw *hw = dev->wl->hw;
3817         struct b43_phy *phy = &dev->phy;
3818
3819         /* XXX: This function will go away soon, when mac80211
3820          *      band stuff is rewritten. So this is just a hack.
3821          *      For now we always claim GPHY mode, as there is no
3822          *      support for NPHY and APHY in the device, yet.
3823          *      This assumption is OK, as any B, N or A PHY will already
3824          *      have died a horrible sanity check death earlier. */
3825
3826         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
3827         phy->possible_phymodes |= B43_PHYMODE_G;
3828
3829         return 0;
3830 }
3831
3832 static void b43_wireless_core_detach(struct b43_wldev *dev)
3833 {
3834         /* We release firmware that late to not be required to re-request
3835          * is all the time when we reinit the core. */
3836         b43_release_firmware(dev);
3837 }
3838
3839 static int b43_wireless_core_attach(struct b43_wldev *dev)
3840 {
3841         struct b43_wl *wl = dev->wl;
3842         struct ssb_bus *bus = dev->dev->bus;
3843         struct pci_dev *pdev = bus->host_pci;
3844         int err;
3845         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3846         u32 tmp;
3847
3848         /* Do NOT do any device initialization here.
3849          * Do it in wireless_core_init() instead.
3850          * This function is for gathering basic information about the HW, only.
3851          * Also some structs may be set up here. But most likely you want to have
3852          * that in core_init(), too.
3853          */
3854
3855         err = ssb_bus_powerup(bus, 0);
3856         if (err) {
3857                 b43err(wl, "Bus powerup failed\n");
3858                 goto out;
3859         }
3860         /* Get the PHY type. */
3861         if (dev->dev->id.revision >= 5) {
3862                 u32 tmshigh;
3863
3864                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3865                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3866                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3867         } else
3868                 B43_WARN_ON(1);
3869
3870         dev->phy.gmode = have_2ghz_phy;
3871         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3872         b43_wireless_core_reset(dev, tmp);
3873
3874         err = b43_phy_versioning(dev);
3875         if (err)
3876                 goto err_powerdown;
3877         /* Check if this device supports multiband. */
3878         if (!pdev ||
3879             (pdev->device != 0x4312 &&
3880              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3881                 /* No multiband support. */
3882                 have_2ghz_phy = 0;
3883                 have_5ghz_phy = 0;
3884                 switch (dev->phy.type) {
3885                 case B43_PHYTYPE_A:
3886                         have_5ghz_phy = 1;
3887                         break;
3888                 case B43_PHYTYPE_G:
3889                 case B43_PHYTYPE_N:
3890                         have_2ghz_phy = 1;
3891                         break;
3892                 default:
3893                         B43_WARN_ON(1);
3894                 }
3895         }
3896         if (dev->phy.type == B43_PHYTYPE_A) {
3897                 /* FIXME */
3898                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3899                 err = -EOPNOTSUPP;
3900                 goto err_powerdown;
3901         }
3902         dev->phy.gmode = have_2ghz_phy;
3903         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3904         b43_wireless_core_reset(dev, tmp);
3905
3906         err = b43_validate_chipaccess(dev);
3907         if (err)
3908                 goto err_powerdown;
3909         err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3910         if (err)
3911                 goto err_powerdown;
3912
3913         /* Now set some default "current_dev" */
3914         if (!wl->current_dev)
3915                 wl->current_dev = dev;
3916         INIT_WORK(&dev->restart_work, b43_chip_reset);
3917
3918         b43_radio_turn_off(dev, 1);
3919         b43_switch_analog(dev, 0);
3920         ssb_device_disable(dev->dev, 0);
3921         ssb_bus_may_powerdown(bus);
3922
3923 out:
3924         return err;
3925
3926 err_powerdown:
3927         ssb_bus_may_powerdown(bus);
3928         return err;
3929 }
3930
3931 static void b43_one_core_detach(struct ssb_device *dev)
3932 {
3933         struct b43_wldev *wldev;
3934         struct b43_wl *wl;
3935
3936         wldev = ssb_get_drvdata(dev);
3937         wl = wldev->wl;
3938         cancel_work_sync(&wldev->restart_work);
3939         b43_debugfs_remove_device(wldev);
3940         b43_wireless_core_detach(wldev);
3941         list_del(&wldev->list);
3942         wl->nr_devs--;
3943         ssb_set_drvdata(dev, NULL);
3944         kfree(wldev);
3945 }
3946
3947 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3948 {
3949         struct b43_wldev *wldev;
3950         struct pci_dev *pdev;
3951         int err = -ENOMEM;
3952
3953         if (!list_empty(&wl->devlist)) {
3954                 /* We are not the first core on this chip. */
3955                 pdev = dev->bus->host_pci;
3956                 /* Only special chips support more than one wireless
3957                  * core, although some of the other chips have more than
3958                  * one wireless core as well. Check for this and
3959                  * bail out early.
3960                  */
3961                 if (!pdev ||
3962                     ((pdev->device != 0x4321) &&
3963                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3964                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3965                         return -ENODEV;
3966                 }
3967         }
3968
3969         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3970         if (!wldev)
3971                 goto out;
3972
3973         wldev->dev = dev;
3974         wldev->wl = wl;
3975         b43_set_status(wldev, B43_STAT_UNINIT);
3976         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3977         tasklet_init(&wldev->isr_tasklet,
3978                      (void (*)(unsigned long))b43_interrupt_tasklet,
3979                      (unsigned long)wldev);
3980         INIT_LIST_HEAD(&wldev->list);
3981
3982         err = b43_wireless_core_attach(wldev);
3983         if (err)
3984                 goto err_kfree_wldev;
3985
3986         list_add(&wldev->list, &wl->devlist);
3987         wl->nr_devs++;
3988         ssb_set_drvdata(dev, wldev);
3989         b43_debugfs_add_device(wldev);
3990
3991       out:
3992         return err;
3993
3994       err_kfree_wldev:
3995         kfree(wldev);
3996         return err;
3997 }
3998
3999 static void b43_sprom_fixup(struct ssb_bus *bus)
4000 {
4001         /* boardflags workarounds */
4002         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4003             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4004                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4005         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4006             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4007                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4008 }
4009
4010 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4011 {
4012         struct ieee80211_hw *hw = wl->hw;
4013
4014         ssb_set_devtypedata(dev, NULL);
4015         ieee80211_free_hw(hw);
4016 }
4017
4018 static int b43_wireless_init(struct ssb_device *dev)
4019 {
4020         struct ssb_sprom *sprom = &dev->bus->sprom;
4021         struct ieee80211_hw *hw;
4022         struct b43_wl *wl;
4023         int err = -ENOMEM;
4024
4025         b43_sprom_fixup(dev->bus);
4026
4027         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4028         if (!hw) {
4029                 b43err(NULL, "Could not allocate ieee80211 device\n");
4030                 goto out;
4031         }
4032
4033         /* fill hw info */
4034         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4035                     IEEE80211_HW_RX_INCLUDES_FCS;
4036         hw->max_signal = 100;
4037         hw->max_rssi = -110;
4038         hw->max_noise = -110;
4039         hw->queues = 1;         /* FIXME: hardware has more queues */
4040         SET_IEEE80211_DEV(hw, dev->dev);
4041         if (is_valid_ether_addr(sprom->et1mac))
4042                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4043         else
4044                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4045
4046         /* Get and initialize struct b43_wl */
4047         wl = hw_to_b43_wl(hw);
4048         memset(wl, 0, sizeof(*wl));
4049         wl->hw = hw;
4050         spin_lock_init(&wl->irq_lock);
4051         spin_lock_init(&wl->leds_lock);
4052         spin_lock_init(&wl->shm_lock);
4053         mutex_init(&wl->mutex);
4054         INIT_LIST_HEAD(&wl->devlist);
4055
4056         ssb_set_devtypedata(dev, wl);
4057         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4058         err = 0;
4059       out:
4060         return err;
4061 }
4062
4063 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4064 {
4065         struct b43_wl *wl;
4066         int err;
4067         int first = 0;
4068
4069         wl = ssb_get_devtypedata(dev);
4070         if (!wl) {
4071                 /* Probing the first core. Must setup common struct b43_wl */
4072                 first = 1;
4073                 err = b43_wireless_init(dev);
4074                 if (err)
4075                         goto out;
4076                 wl = ssb_get_devtypedata(dev);
4077                 B43_WARN_ON(!wl);
4078         }
4079         err = b43_one_core_attach(dev, wl);
4080         if (err)
4081                 goto err_wireless_exit;
4082
4083         if (first) {
4084                 err = ieee80211_register_hw(wl->hw);
4085                 if (err)
4086                         goto err_one_core_detach;
4087         }
4088
4089       out:
4090         return err;
4091
4092       err_one_core_detach:
4093         b43_one_core_detach(dev);
4094       err_wireless_exit:
4095         if (first)
4096                 b43_wireless_exit(dev, wl);
4097         return err;
4098 }
4099
4100 static void b43_remove(struct ssb_device *dev)
4101 {
4102         struct b43_wl *wl = ssb_get_devtypedata(dev);
4103         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4104
4105         B43_WARN_ON(!wl);
4106         if (wl->current_dev == wldev)
4107                 ieee80211_unregister_hw(wl->hw);
4108
4109         b43_one_core_detach(dev);
4110
4111         if (list_empty(&wl->devlist)) {
4112                 /* Last core on the chip unregistered.
4113                  * We can destroy common struct b43_wl.
4114                  */
4115                 b43_wireless_exit(dev, wl);
4116         }
4117 }
4118
4119 /* Perform a hardware reset. This can be called from any context. */
4120 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4121 {
4122         /* Must avoid requeueing, if we are in shutdown. */
4123         if (b43_status(dev) < B43_STAT_INITIALIZED)
4124                 return;
4125         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4126         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4127 }
4128
4129 #ifdef CONFIG_PM
4130
4131 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4132 {
4133         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4134         struct b43_wl *wl = wldev->wl;
4135
4136         b43dbg(wl, "Suspending...\n");
4137
4138         mutex_lock(&wl->mutex);
4139         wldev->suspend_init_status = b43_status(wldev);
4140         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4141                 b43_wireless_core_stop(wldev);
4142         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4143                 b43_wireless_core_exit(wldev);
4144         mutex_unlock(&wl->mutex);
4145
4146         b43dbg(wl, "Device suspended.\n");
4147
4148         return 0;
4149 }
4150
4151 static int b43_resume(struct ssb_device *dev)
4152 {
4153         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4154         struct b43_wl *wl = wldev->wl;
4155         int err = 0;
4156
4157         b43dbg(wl, "Resuming...\n");
4158
4159         mutex_lock(&wl->mutex);
4160         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4161                 err = b43_wireless_core_init(wldev);
4162                 if (err) {
4163                         b43err(wl, "Resume failed at core init\n");
4164                         goto out;
4165                 }
4166         }
4167         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4168                 err = b43_wireless_core_start(wldev);
4169                 if (err) {
4170                         b43_wireless_core_exit(wldev);
4171                         b43err(wl, "Resume failed at core start\n");
4172                         goto out;
4173                 }
4174         }
4175         mutex_unlock(&wl->mutex);
4176
4177         b43dbg(wl, "Device resumed.\n");
4178       out:
4179         return err;
4180 }
4181
4182 #else /* CONFIG_PM */
4183 # define b43_suspend    NULL
4184 # define b43_resume     NULL
4185 #endif /* CONFIG_PM */
4186
4187 static struct ssb_driver b43_ssb_driver = {
4188         .name           = KBUILD_MODNAME,
4189         .id_table       = b43_ssb_tbl,
4190         .probe          = b43_probe,
4191         .remove         = b43_remove,
4192         .suspend        = b43_suspend,
4193         .resume         = b43_resume,
4194 };
4195
4196 static int __init b43_init(void)
4197 {
4198         int err;
4199
4200         b43_debugfs_init();
4201         err = b43_pcmcia_init();
4202         if (err)
4203                 goto err_dfs_exit;
4204         err = ssb_driver_register(&b43_ssb_driver);
4205         if (err)
4206                 goto err_pcmcia_exit;
4207
4208         return err;
4209
4210 err_pcmcia_exit:
4211         b43_pcmcia_exit();
4212 err_dfs_exit:
4213         b43_debugfs_exit();
4214         return err;
4215 }
4216
4217 static void __exit b43_exit(void)
4218 {
4219         ssb_driver_unregister(&b43_ssb_driver);
4220         b43_pcmcia_exit();
4221         b43_debugfs_exit();
4222 }
4223
4224 module_init(b43_init)
4225 module_exit(b43_exit)