2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #define ATHEROS_VENDOR_ID 0x168c
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
30 #define AR5416_AR9100_DEVID 0x000b
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
51 #define howmany(x, y) (((x)+((y)-1))/(y))
54 struct ath_tx_status {
80 struct ath_rx_status {
105 #define ATH9K_RXERR_CRC 0x01
106 #define ATH9K_RXERR_PHY 0x02
107 #define ATH9K_RXERR_FIFO 0x04
108 #define ATH9K_RXERR_DECRYPT 0x08
109 #define ATH9K_RXERR_MIC 0x10
111 #define ATH9K_RX_MORE 0x01
112 #define ATH9K_RX_MORE_AGGR 0x02
113 #define ATH9K_RX_GI 0x04
114 #define ATH9K_RX_2040 0x08
115 #define ATH9K_RX_DELIM_CRC_PRE 0x10
116 #define ATH9K_RX_DELIM_CRC_POST 0x20
117 #define ATH9K_RX_DECRYPT_BUSY 0x40
119 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
120 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
129 struct ath_tx_status tx;
130 struct ath_rx_status rx;
136 #define ds_txstat ds_us.tx
137 #define ds_rxstat ds_us.rx
138 #define ds_stat ds_us.stats
140 #define ATH9K_TXDESC_CLRDMASK 0x0001
141 #define ATH9K_TXDESC_NOACK 0x0002
142 #define ATH9K_TXDESC_RTSENA 0x0004
143 #define ATH9K_TXDESC_CTSENA 0x0008
144 #define ATH9K_TXDESC_INTREQ 0x0010
145 #define ATH9K_TXDESC_VEOL 0x0020
146 #define ATH9K_TXDESC_EXT_ONLY 0x0040
147 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
148 #define ATH9K_TXDESC_VMF 0x0100
149 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
151 #define ATH9K_RXDESC_INTREQ 0x0020
153 enum hal_capability_type {
162 HAL_CAP_MCAST_KEYSRCH,
166 HAL_CAP_ANT_CFG_2GHZ,
170 struct hal_capabilities {
171 u32 halChanSpreadSupport:1,
172 halChapTuningSupport:1,
173 halMicAesCcmSupport:1,
176 halCipherAesCcmSupport:1,
177 halCipherCkipSupport:1,
178 halCipherTkipSupport:1,
180 halBssIdMaskSupport:1,
181 halMcastKeySrchSupport:1,
184 halChanQuarterRate:1,
188 halRfSilentSupport:1,
191 halEnhancedPmSupport:1,
192 halAutoSleepSupport:1,
193 hal4kbSplitTransSupport:1,
194 halWowMatchPatternExact:1;
195 u32 halWirelessModes;
198 u16 halLow5GhzChan, halHigh5GhzChan;
199 u16 halLow2GhzChan, halHigh2GhzChan;
204 u16 halTxTrigLevelMax;
211 struct hal_ops_config {
212 int ath_hal_dma_beacon_response_time;
213 int ath_hal_sw_beacon_response_time;
214 int ath_hal_additional_swba_backoff;
216 int ath_hal_cwmIgnoreExtCCA;
217 u8 ath_hal_pciePowerSaveEnable;
218 u8 ath_hal_pcieL1SKPEnable;
219 u8 ath_hal_pcieClockReq;
220 u32 ath_hal_pcieWaen;
221 int ath_hal_pciePowerReset;
222 u8 ath_hal_pcieRestore;
223 u8 ath_hal_analogShiftReg;
225 u32 ath_hal_ofdmTrigLow;
226 u32 ath_hal_ofdmTrigHigh;
227 u32 ath_hal_cckTrigHigh;
228 u32 ath_hal_cckTrigLow;
229 u32 ath_hal_enableANI;
230 u8 ath_hal_noiseImmunityLvl;
231 u32 ath_hal_ofdmWeakSigDet;
232 u32 ath_hal_cckWeakSigThr;
233 u8 ath_hal_spurImmunityLvl;
234 u8 ath_hal_firStepLvl;
235 int8_t ath_hal_rssiThrHigh;
236 int8_t ath_hal_rssiThrLow;
237 u16 ath_hal_diversityControl;
238 u16 ath_hal_antennaSwitchSwap;
239 int ath_hal_serializeRegMode;
240 int ath_hal_intrMitigation;
241 #define SPUR_DISABLE 0
242 #define SPUR_ENABLE_IOCTL 1
243 #define SPUR_ENABLE_EEPROM 2
244 #define AR_EEPROM_MODAL_SPURS 5
245 #define AR_SPUR_5413_1 1640
246 #define AR_SPUR_5413_2 1200
247 #define AR_NO_SPUR 0x8000
248 #define AR_BASE_FREQ_2GHZ 2300
249 #define AR_BASE_FREQ_5GHZ 4900
250 #define AR_SPUR_FEEQ_BOUND_HT40 19
251 #define AR_SPUR_FEEQ_BOUND_HT20 10
252 int ath_hal_spurMode;
253 u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
256 enum ath9k_tx_queue {
257 ATH9K_TX_QUEUE_INACTIVE = 0,
259 ATH9K_TX_QUEUE_BEACON,
261 ATH9K_TX_QUEUE_UAPSD,
262 ATH9K_TX_QUEUE_PSPOLL
265 #define ATH9K_NUM_TX_QUEUES 10
267 enum ath9k_tx_queue_subtype {
275 enum ath9k_tx_queue_flags {
276 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
277 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
278 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
279 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
280 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
281 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
282 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
283 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
284 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
287 struct ath9k_txq_info {
289 enum ath9k_tx_queue_subtype tqi_subtype;
290 enum ath9k_tx_queue_flags tqi_qflags;
298 u32 tqi_cbrOverflowLimit;
304 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
306 #define ATH9K_DECOMP_MASK_SIZE 128
307 #define ATH9K_READY_TIME_LO_BOUND 50
308 #define ATH9K_READY_TIME_HI_BOUND 96
310 enum ath9k_pkt_type {
311 ATH9K_PKT_TYPE_NORMAL = 0,
313 ATH9K_PKT_TYPE_PSPOLL,
314 ATH9K_PKT_TYPE_BEACON,
315 ATH9K_PKT_TYPE_PROBE_RESP,
316 ATH9K_PKT_TYPE_CHIRP,
317 ATH9K_PKT_TYPE_GRP_POLL,
320 struct ath9k_tx_queue_info {
322 enum ath9k_tx_queue tqi_type;
323 enum ath9k_tx_queue_subtype tqi_subtype;
324 enum ath9k_tx_queue_flags tqi_qflags;
332 u32 tqi_cbrOverflowLimit;
339 enum ath9k_rx_filter {
340 ATH9K_RX_FILTER_UCAST = 0x00000001,
341 ATH9K_RX_FILTER_MCAST = 0x00000002,
342 ATH9K_RX_FILTER_BCAST = 0x00000004,
343 ATH9K_RX_FILTER_CONTROL = 0x00000008,
344 ATH9K_RX_FILTER_BEACON = 0x00000010,
345 ATH9K_RX_FILTER_PROM = 0x00000020,
346 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
347 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
348 ATH9K_RX_FILTER_PHYERR = 0x00000100,
349 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
353 ATH9K_INT_RX = 0x00000001,
354 ATH9K_INT_RXDESC = 0x00000002,
355 ATH9K_INT_RXNOFRM = 0x00000008,
356 ATH9K_INT_RXEOL = 0x00000010,
357 ATH9K_INT_RXORN = 0x00000020,
358 ATH9K_INT_TX = 0x00000040,
359 ATH9K_INT_TXDESC = 0x00000080,
360 ATH9K_INT_TIM_TIMER = 0x00000100,
361 ATH9K_INT_TXURN = 0x00000800,
362 ATH9K_INT_MIB = 0x00001000,
363 ATH9K_INT_RXPHY = 0x00004000,
364 ATH9K_INT_RXKCM = 0x00008000,
365 ATH9K_INT_SWBA = 0x00010000,
366 ATH9K_INT_BMISS = 0x00040000,
367 ATH9K_INT_BNR = 0x00100000,
368 ATH9K_INT_TIM = 0x00200000,
369 ATH9K_INT_DTIM = 0x00400000,
370 ATH9K_INT_DTIMSYNC = 0x00800000,
371 ATH9K_INT_GPIO = 0x01000000,
372 ATH9K_INT_CABEND = 0x02000000,
373 ATH9K_INT_CST = 0x10000000,
374 ATH9K_INT_GTT = 0x20000000,
375 ATH9K_INT_FATAL = 0x40000000,
376 ATH9K_INT_GLOBAL = 0x80000000,
377 ATH9K_INT_BMISC = ATH9K_INT_TIM |
381 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
393 ATH9K_INT_NOCARD = 0xffffffff
396 struct ath9k_rate_table {
398 u8 rateCodeToIndex[256];
412 #define ATH9K_RATESERIES_RTS_CTS 0x0001
413 #define ATH9K_RATESERIES_2040 0x0002
414 #define ATH9K_RATESERIES_HALFGI 0x0004
416 struct ath9k_11n_rate_series {
424 #define CHANNEL_CW_INT 0x00002
425 #define CHANNEL_CCK 0x00020
426 #define CHANNEL_OFDM 0x00040
427 #define CHANNEL_2GHZ 0x00080
428 #define CHANNEL_5GHZ 0x00100
429 #define CHANNEL_PASSIVE 0x00200
430 #define CHANNEL_DYN 0x00400
431 #define CHANNEL_HALF 0x04000
432 #define CHANNEL_QUARTER 0x08000
433 #define CHANNEL_HT20 0x10000
434 #define CHANNEL_HT40PLUS 0x20000
435 #define CHANNEL_HT40MINUS 0x40000
437 #define CHANNEL_INTERFERENCE 0x01
438 #define CHANNEL_DFS 0x02
439 #define CHANNEL_4MS_LIMIT 0x04
440 #define CHANNEL_DFS_CLEAR 0x08
441 #define CHANNEL_DISALLOW_ADHOC 0x10
442 #define CHANNEL_PER_11D_ADHOC 0x20
444 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
445 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
446 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
447 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
448 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
449 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
450 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
451 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
452 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
453 #define CHANNEL_ALL \
462 struct ath9k_channel {
466 int8_t maxRegTxPower;
471 bool oneTimeCalsDone;
474 int16_t rawNoiseFloor;
477 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
478 #ifdef ATH_NF_PER_CHAN
479 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
483 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
484 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
485 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
486 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
487 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
488 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
489 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
490 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
491 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
492 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
493 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
494 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
495 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
496 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
497 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
498 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
500 /* These macros check chanmode and not channelFlags */
501 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
502 ((_c)->chanmode == CHANNEL_G_HT20))
503 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
504 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
505 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
506 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
507 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
509 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
510 #define IS_CHAN_A_5MHZ_SPACED(_c) \
511 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
512 (((_c)->channel % 20) != 0) && \
513 (((_c)->channel % 10) != 0))
515 struct ath9k_keyval {
524 enum ath9k_key_type {
525 ATH9K_KEY_TYPE_CLEAR,
532 ATH9K_CIPHER_WEP = 0,
533 ATH9K_CIPHER_AES_OCB = 1,
534 ATH9K_CIPHER_AES_CCM = 2,
535 ATH9K_CIPHER_CKIP = 3,
536 ATH9K_CIPHER_TKIP = 4,
537 ATH9K_CIPHER_CLR = 5,
538 ATH9K_CIPHER_MIC = 127
541 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
542 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
543 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
544 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
545 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
546 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
547 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
548 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
549 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
551 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
552 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
553 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
554 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
555 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
556 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
558 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
559 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
561 #define SD_NO_CTL 0xE0
572 #define AR_EEPROM_MAC(i) (0x1d+(i))
573 #define EEP_SCALE 100
576 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
577 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
578 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
579 #define AR_EEPROM_RFSILENT_POLARITY_S 1
581 #define CTRY_DEBUG 0x1ff
582 #define CTRY_DEFAULT 0
584 enum reg_ext_bitmap {
585 REG_EXT_JAPAN_MIDBAND = 1,
586 REG_EXT_FCC_DFS_HT40 = 2,
587 REG_EXT_JAPAN_NONDFS_HT40 = 3,
588 REG_EXT_JAPAN_DFS_HT40 = 4
591 struct ath9k_country_entry {
600 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
601 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
603 #define SM(_v, _f) (((_v) << _f##_S) & _f)
604 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
605 #define REG_RMW(_a, _r, _set, _clr) \
606 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
607 #define REG_RMW_FIELD(_a, _r, _f, _v) \
609 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
610 #define REG_SET_BIT(_a, _r, _f) \
611 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
612 #define REG_CLR_BIT(_a, _r, _f) \
613 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
615 #define ATH9K_COMP_BUF_MAX_SIZE 9216
616 #define ATH9K_COMP_BUF_ALIGN_SIZE 512
618 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
621 #define INIT_CWMIN 15
622 #define INIT_CWMIN_11B 31
623 #define INIT_CWMAX 1023
624 #define INIT_SH_RETRY 10
625 #define INIT_LG_RETRY 10
626 #define INIT_SSH_RETRY 32
627 #define INIT_SLG_RETRY 32
629 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
631 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
632 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
634 #define IEEE80211_WEP_IVLEN 3
635 #define IEEE80211_WEP_KIDLEN 1
636 #define IEEE80211_WEP_CRCLEN 4
637 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
638 (IEEE80211_WEP_IVLEN + \
639 IEEE80211_WEP_KIDLEN + \
640 IEEE80211_WEP_CRCLEN))
641 #define IEEE80211_MAX_LEN (2300 + FCS_LEN + \
642 (IEEE80211_WEP_IVLEN + \
643 IEEE80211_WEP_KIDLEN + \
644 IEEE80211_WEP_CRCLEN))
646 #define MAX_REG_ADD_COUNT 129
647 #define MAX_RATE_POWER 63
649 #define LE_READ_2(p) \
651 ((((const u8 *)(p))[0]) | \
652 (((const u8 *)(p))[1] << 8)))
654 #define LE_READ_4(p) \
656 ((((const u8 *)(p))[0]) | \
657 (((const u8 *)(p))[1] << 8) | \
658 (((const u8 *)(p))[2] << 16) | \
659 (((const u8 *)(p))[3] << 24)))
661 enum ath9k_power_mode {
664 ATH9K_PM_NETWORK_SLEEP,
668 #define HAL_ANTENNA_MIN_MODE 0
669 #define HAL_ANTENNA_FIXED_A 1
670 #define HAL_ANTENNA_FIXED_B 2
671 #define HAL_ANTENNA_MAX_MODE 3
673 struct ath9k_mib_stats {
681 enum ath9k_ant_setting {
682 ATH9K_ANT_VARIABLE = 0,
694 #define ATH9K_SLOT_TIME_6 6
695 #define ATH9K_SLOT_TIME_9 9
696 #define ATH9K_SLOT_TIME_20 20
698 enum ath9k_ht_macmode {
699 ATH9K_HT_MACMODE_20 = 0,
700 ATH9K_HT_MACMODE_2040 = 1,
703 enum ath9k_ht_extprotspacing {
704 ATH9K_HT_EXTPROTSPACING_20 = 0,
705 ATH9K_HT_EXTPROTSPACING_25 = 1,
708 struct ath9k_ht_cwm {
709 enum ath9k_ht_macmode ht_macmode;
710 enum ath9k_ht_extprotspacing ht_extprotspacing;
714 HAL_FREQ_BAND_5GHZ = 0,
715 HAL_FREQ_BAND_2GHZ = 1,
719 ATH9K_ANI_PRESENT = 0x1,
720 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
721 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
722 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
723 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
724 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
725 ATH9K_ANI_MODE = 0x40,
726 ATH9K_ANI_PHYERR_RESET = 0x80,
737 #define PHY_CCK PHY_DS
739 enum start_adhoc_option {
746 enum ath9k_tp_scale {
747 ATH9K_TP_SCALE_MAX = 0,
755 SER_REG_MODE_OFF = 0,
757 SER_REG_MODE_AUTO = 2,
760 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
761 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
762 #define AR_PHY_CCA_MIN_BAD_VALUE -121
763 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
764 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
766 #define ATH9K_NF_CAL_HIST_MAX 5
767 #define NUM_NF_READINGS 6
769 struct ath9k_nfcal_hist {
770 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
776 struct ath9k_beacon_state {
780 #define ATH9K_BEACON_PERIOD 0x0000ffff
781 #define ATH9K_BEACON_ENA 0x00800000
782 #define ATH9K_BEACON_RESET_TSF 0x01000000
785 u16 bs_cfpmaxduration;
788 u16 bs_bmissthreshold;
789 u32 bs_sleepduration;
792 struct ath9k_node_stats {
799 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
801 enum ath9k_gpio_output_mux_type {
802 ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
803 ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
804 ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
805 ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
806 ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
807 ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
811 ATH9K_RESET_POWER_ON,
816 #define AH_USE_EEPROM 0x1
822 struct ath_softc *ah_sc;
828 u16 ah_analog5GhzRev;
829 u16 ah_analog2GhzRev;
830 u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
832 enum ath9k_opmode ah_opmode;
833 struct hal_ops_config ah_config;
834 struct hal_capabilities ah_caps;
835 int16_t ah_powerLimit;
836 u16 ah_maxPowerLevel;
840 u16 ah_currentRDInUse;
844 enum start_adhoc_option ah_adHocMode;
846 struct ath9k_channel ah_channels[150];
848 struct ath9k_channel *ah_curchan;
850 bool ah_rfkillEnabled;
851 bool ah_isPciExpress;
853 #ifndef ATH_NF_PER_CHAN
854 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
859 WIRELESS_MODE_11a = 0,
860 WIRELESS_MODE_11b = 2,
861 WIRELESS_MODE_11g = 3,
862 WIRELESS_MODE_11NA_HT20 = 6,
863 WIRELESS_MODE_11NG_HT20 = 7,
864 WIRELESS_MODE_11NA_HT40PLUS = 8,
865 WIRELESS_MODE_11NA_HT40MINUS = 9,
866 WIRELESS_MODE_11NG_HT40PLUS = 10,
867 WIRELESS_MODE_11NG_HT40MINUS = 11,
872 ATH9K_MODE_SEL_11A = 0x00001,
873 ATH9K_MODE_SEL_11B = 0x00002,
874 ATH9K_MODE_SEL_11G = 0x00004,
875 ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
876 ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
877 ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
878 ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
879 ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
880 ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
881 ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
883 ATH9K_MODE_SEL_11NG_HT20),
884 ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
885 ATH9K_MODE_SEL_11NA_HT20),
886 ATH9K_MODE_SEL_ALL = 0xffffffff
889 struct chan_centers {
895 int ath_hal_getcapability(struct ath_hal *ah,
896 enum hal_capability_type type,
899 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
901 void ath9k_hw_detach(struct ath_hal *ah);
902 struct ath_hal *ath9k_hw_attach(u16 devid,
903 struct ath_softc *sc,
906 bool ath9k_regd_init_channels(struct ath_hal *ah,
907 u32 maxchans, u32 *nchans,
909 u32 maxregids, u32 *nregids,
910 u16 cc, u32 modeSelect,
912 bool enableExtendedChannels);
913 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
914 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
915 enum ath9k_int ints);
916 bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
917 struct ath9k_channel *chan,
918 enum ath9k_ht_macmode macmode,
919 u8 txchainmask, u8 rxchainmask,
920 enum ath9k_ht_extprotspacing extprotspacing,
923 bool ath9k_hw_phy_disable(struct ath_hal *ah);
924 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
926 void ath9k_hw_ani_monitor(struct ath_hal *ah,
927 const struct ath9k_node_stats *stats,
928 struct ath9k_channel *chan);
929 bool ath9k_hw_calibrate(struct ath_hal *ah,
930 struct ath9k_channel *chan,
934 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
935 struct ath9k_channel *chan);
936 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
938 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
939 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
941 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
942 void ath9k_hw_reset_tsf(struct ath_hal *ah);
943 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
944 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
946 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
948 const struct ath9k_keyval *k,
951 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
953 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
954 bool ath9k_hw_intrpend(struct ath_hal *ah);
955 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
956 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
958 void ath9k_hw_procmibevent(struct ath_hal *ah,
959 const struct ath9k_node_stats *stats);
960 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
961 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
962 bool ath9k_hw_phycounters(struct ath_hal *ah);
963 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
964 bool ath9k_hw_getcapability(struct ath_hal *ah,
965 enum hal_capability_type type,
968 bool ath9k_hw_setcapability(struct ath_hal *ah,
969 enum hal_capability_type type,
973 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
974 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
975 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
976 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
978 bool ath9k_hw_setpower(struct ath_hal *ah,
979 enum ath9k_power_mode mode);
980 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
981 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
982 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
983 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
984 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
985 enum ath9k_ant_setting settings,
986 struct ath9k_channel *chan,
990 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
991 int ath9k_hw_select_antconfig(struct ath_hal *ah,
993 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
995 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
996 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
997 const struct ath9k_rate_table *rates,
998 u32 frameLen, u16 rateix,
1000 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1001 struct ath_desc *lastds,
1002 u32 durUpdateEn, u32 rtsctsRate,
1004 struct ath9k_11n_rate_series series[],
1005 u32 nseries, u32 flags);
1006 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
1007 struct ath_desc *ds,
1009 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1010 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1011 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
1012 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
1013 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
1014 struct ath9k_channel *chan);
1015 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
1016 bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
1017 struct ath9k_txq_info *qInfo);
1018 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
1019 const struct ath9k_txq_info *qInfo);
1020 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
1021 const struct ath9k_channel *c);
1022 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1023 u32 pktLen, enum ath9k_pkt_type type,
1024 u32 txPower, u32 keyIx,
1025 enum ath9k_key_type keyType, u32 flags);
1026 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1027 u32 segLen, bool firstSeg,
1029 const struct ath_desc *ds0);
1030 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1034 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1035 void ath9k_hw_beaconinit(struct ath_hal *ah,
1036 u32 next_beacon, u32 beacon_period);
1037 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1038 const struct ath9k_beacon_state *bs);
1039 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1040 u32 size, u32 flags);
1041 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1042 void ath9k_hw_rxena(struct ath_hal *ah);
1043 void ath9k_hw_setopmode(struct ath_hal *ah);
1044 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
1045 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
1047 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
1048 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1049 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1050 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1051 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
1052 struct ath_desc *ds, u32 pa,
1053 struct ath_desc *nds, u64 tsf);
1054 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1055 int ath9k_hw_txprocdesc(struct ath_hal *ah,
1056 struct ath_desc *ds);
1057 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1059 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1061 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1062 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1063 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1064 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1065 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1066 struct ath_desc *ds, u32 vmf);
1067 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1068 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1069 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1070 const struct ath9k_txq_info *qInfo);
1071 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1072 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1073 bool ath9k_hw_disable(struct ath_hal *ah);
1074 void ath9k_hw_rfdetach(struct ath_hal *ah);
1075 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1076 struct ath9k_channel *chan,
1077 struct chan_centers *centers);
1078 bool ath9k_get_channel_edges(struct ath_hal *ah,
1079 u16 flags, u16 *low,