openwrt/target/linux/linux-2.4/patches/ar7/003-net_driver_cpmac.patch

   1 diff -urN linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.c
   2 --- linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.c      1970-01-01 01:00:00.000000000 +0100
   3 +++ linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.c      2005-07-12 02:48:41.996601000 +0200
   4 @@ -0,0 +1,728 @@
   5 +#ifndef _INC_CPCOMMON_C
   6 +#define _INC_CPCOMMON_C
   7 +
   8 +#ifdef _CPHAL_CPMAC
   9 +#include "cpremap_cpmac.c"
  10 +#endif
  11 +
  12 +#ifdef _CPHAL_AAL5
  13 +#include "cpremap_cpaal5.c"
  14 +#endif
  15 +
  16 +#ifdef _CPHAL_CPSAR
  17 +#include "cpremap_cpsar.c"
  18 +#endif
  19 +
  20 +#ifdef _CPHAL_AAL2
  21 +#include "cpremap_cpaal2.c"
  22 +#endif
  23 +
  24 +/**
  25 +@defgroup Common_Config_Params Common Configuration Parameters
  26 +
  27 +This section documents the configuration parameters that are valid across
  28 +all CPHAL devices.
  29 +@{
  30 +*/
  31 +/** This is the debug level.  The field is bit defined, such that the user
  32 +should set to 1 all the bits corresponding to desired debug outputs.  The following
  33 +are the meanings for each debug bit:
  34 +- bit0 (LSB): CPHAL Function Trace
  35 +- b1 : OS Function call trace
  36 +- b2 : Critical section entry/exit
  37 +- b3 : Memory allocation/destruction
  38 +- b4 : Detailed information in Rx path
  39 +- b5 : Detailed information in Tx path
  40 +- b6 : Extended error information
  41 +- b7 : General info
  42 +*/
  43 +static const char pszDebug[]        = "debug";
  44 +/** CPU Frequency. */
  45 +/*static const char pszCpuFreq[]      = "CpuFreq";*/               /*MJH-030403*/
  46 +/** Base address for the module. */
  47 +static const char pszBase[]         = "base";
  48 +/** Reset bit for the module. */
  49 +static const char pszResetBit[]     = "reset_bit";
  50 +/** Reset base address for the module. */
  51 +static const char pszResetBase[]    = "ResetBase";
  52 +/** Interrupt line for the module. */
  53 +static const char pszIntLine[]      = "int_line";
  54 +/** VLYNQ offset for the module.  Disregard if not using VLYNQ. */
  55 +static const char pszOffset[]       = "offset";
  56 +/** The OS may "Get" this parameter, which is a pointer
  57 +    to a character string that indicates the version of CPHAL. */
  58 +static const char pszVer[]          = "Version";
  59 +/*@}*/
  60 +
  61 +/**
  62 +@defgroup Common_Control_Params Common Keys for [os]Control()
  63 +
  64 +This section documents the keys used with the OS @c Control() interface that
  65 +are required by CPHAL devices.
  66 +
  67 +@{
  68 +*/
  69 +/** Used to wait for an integer number of clock ticks, given as an integer
  70 +    pointer in the @p Value parameter.  No actions are defined. */
  71 +static const char pszSleep[]             = "Sleep";
  72 +/** Requests the OS to flush it's IO buffers.  No actions are defined. */
  73 +static const char pszSioFlush[]          = "SioFlush";
  74 +/*@}*/
  75 +
  76 +static const char pszStateChange[]       = "StateChange";
  77 +static const char pszStatus[]            = "Status";
  78 +
  79 +static const char pszGET[]               = "Get";
  80 +static const char pszSET[]               = "Set";
  81 +static const char pszCLEAR[]             = "Clear";
  82 +static const char pszNULL[]              = "";
  83 +static const char pszLocator[]           = "Locator";
  84 +static const char pszOff[]               = "Off";
  85 +static const char pszOn[]                = "On";
  86 +static const char hcMaxFrags[]           = "MaxFrags";
  87 +
  88 +#ifdef _CPHAL_CPMAC
  89 +
  90 +/*  New method for string constants */
  91 +const char hcClear[]  = "Clear";
  92 +const char hcGet[]    = "Get";
  93 +const char hcSet[]    = "Set";
  94 +
  95 +const char hcTick[]   = "Tick";
  96 +
  97 +static const CONTROL_KEY KeyCommon[] =
  98 +   {
  99 +     {""                   , enCommonStart},
 100 +     {pszStatus            , enStatus},
 101 +     {pszOff               , enOff},
 102 +     {pszOn                , enOn},
 103 +     {pszDebug             , enDebug},
 104 +     {hcCpuFrequency       , enCpuFreq},                           /*MJH~030403*/
 105 +     {""                   , enCommonEnd}
 106 +   };
 107 +#endif
 108 +
 109 +/**
 110 +@defgroup Common_Statistics Statistics
 111 +
 112 +A broad array of module statistics is available.  Statistics values are accessed
 113 +through the @c Control() interface of the CPHAL.  There are 5 different levels
 114 +of statistics, each of which correspond to a unique set of data.  Furthermore,
 115 +certain statistics data is indexed by using a channel number and Tx queue number.
 116 +The following is a brief description of each statistics level, along with the
 117 +indexes used for the level:
 118 +
 119 +- Level 0:  Hardware Statistics (index with channel)
 120 +- Level 1:  CPHAL Software Statistics (channel, queue)
 121 +- Level 2:  CPHAL Flags (channel, queue)
 122 +- Level 3:  CPHAL Channel Configuration (channel)
 123 +- Level 4:  CPHAL General Configuration (no index)
 124 +
 125 +The caller requests statistics information by providing a Key string to the
 126 +@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
 127 +The only valid Action parameter for statistics usage is "Get".
 128 +
 129 +Code Examples:
 130 +@code
 131 +unsigned int *StatsData;
 132 +
 133 +# Get Level 0 stats for Channel 1
 134 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
 135 +
 136 +# Get Level 2 stats for Channel 0, Queue 0
 137 +HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
 138 +
 139 +# Get Level 4 stats
 140 +HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
 141 +@endcode
 142 +
 143 +The information returned in the Value parameter of @c Control() is an
 144 +array of pointers to strings.  The pointers are arranged in pairs.
 145 +The first pointer is a pointer to a name string for a particular statistic.
 146 +The next pointer is a pointer to a string containing the representation of
 147 +the integer statistic value corresponding to the first pointer.  This is followed
 148 +by another pair of pointers, and so on, until a NULL pointer is encountered.  The
 149 +following is example code for processing the statistics data.  Note that the OS
 150 +is responsible for freeing the memory passed back through the Value parameter of
 151 +@c Control().
 152 +
 153 +@code
 154 +unsigned int *StatsData;
 155 +
 156 +# Get Level 0 stats for Channel 1
 157 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
 158 +
 159 +# output Statistics data
 160 +PrintStats(StatsData);
 161 +
 162 +# the upper layer is responsible for freeing stats info
 163 +free(&StatsPtr);
 164 +
 165 +...
 166 +
 167 +void PrintStats(unsigned int *StatsPtr)
 168 +  {
 169 +   while(*StatsPtr)
 170 +     {
 171 +      printf("%20s:",  (char *)*StatsPtr);
 172 +      StatsPtr++;
 173 +      printf("%11s\n", (char *)*StatsPtr);
 174 +      StatsPtr++;
 175 +     }
 176 +   MySioFlush();
 177 +  }
 178 +@endcode
 179 +
 180 +Within each statistics level, there are several statistics defined.  The statistics that
 181 +are common to every CPPI module are listed below.  In addition, each module may define
 182 +extra statistics in each level, which will be documented within the module-specific
 183 +documentation appendices.
 184 +
 185 +- Level 0 Statistics
 186 +  - All level 0 statistics are module-specific.
 187 +- Level 1 Statistics (CPHAL Software Statistics)
 188 +  - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
 189 +  - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
 190 +transmitting the previous last packet in the queue (per channel and queue).
 191 +  - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
 192 +reception of the previous last packet in the queue (per channel).
 193 +  - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
 194 +  - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
 195 +  - RxPacketsServiced: Number of received packets (per channel).
 196 +  - TxPacketsServiced: Number of transmitted packets (per channel and queue).
 197 +  - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
 198 +  - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
 199 +  - RxTotal: Total number of received packets, all channels.
 200 +  - TxTotal: Total number of transmitted packets, all channels and queues.
 201 +- Level 2 Statistics (CPHAL Flags)
 202 +  - RcbPool: Pointer to receive descriptor pool (per channel).
 203 +  - RxActQueueCount: Number of buffers currently available for receive (per channel).
 204 +  - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
 205 +  - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
 206 +  - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
 207 +  - RcbStart: Pointer to block of receive descriptors.
 208 +  - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
 209 +  - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
 210 +  - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
 211 +  - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
 212 +  - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
 213 +  - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
 214 +  - TcbStart: Pointer to block of transmit descriptors.
 215 +  - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
 216 +- Level 3 Statistics (CPHAL Channel Configuration)
 217 +  - RxBufSize: Rx buffer size.
 218 +  - RxBufferOffset: Rx buffer offset.
 219 +  - RxNumBuffers: Number of Rx buffers.
 220 +  - RxServiceMax: Maximum number of receive packets to service at a time.
 221 +  - TxNumBuffers: Number of Tx buffer descriptors.
 222 +  - TxNumQueues: Number of Tx queues to use.
 223 +  - TxServiceMax: Maximum number of transmit packets to service at a time.
 224 +- Level 4 Statistics (CPHAL General Configuration)
 225 +  - Base Address: Base address of the module.
 226 +  - Offset (VLYNQ): VLYNQ relative module offset.
 227 +  - Interrupt Line: Interrupt number.
 228 +  - Debug: Debug flag, 1 to enable debug.
 229 +  - Inst: Instance number.
 230 +*/
 231 +
 232 +/*
 233 +   Data Type 0 = int display
 234 +   Data Type 1 = hex display
 235 +   Data Type 2 = channel structure, int display
 236 +   Data Type 3 = queue index and int display
 237 +   Data Type 4 = queue index and hex display
 238 +*/
 239 +#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
 240 +static STATS_TABLE StatsTable0[] =
 241 +  {
 242 +#ifdef _CPHAL_AAL5
 243 +   /* Name ,        Data Ptr,   Data Type */
 244 +   {"Crc Errors",          0,          0},
 245 +   {"Len Errors",          0,          0},
 246 +   {"Abort Errors",        0,          0},
 247 +   {"Starv Errors",        0,          0}
 248 +#endif
 249 +#ifdef _CPHAL_CPMAC
 250 +   {"Rx Good Frames",      0,          0}
 251 +#endif
 252 +  };
 253 +
 254 +static STATS_TABLE StatsTable1[] =
 255 +  {
 256 +   /* Name ,        Data Ptr,   Data Type */
 257 +   {"DmaLenErrors",        0,          0},
 258 +   {"TxMisQCnt",           0,          3},
 259 +   {"RxMisQCnt",           0,          0},
 260 +   {"TxEOQCnt",            0,          3},
 261 +   {"RxEOQCnt",            0,          0},
 262 +   {"RxPacketsServiced",   0,          0},
 263 +   {"TxPacketsServiced",   0,          3},
 264 +   {"RxMaxServiced",       0,          0},
 265 +   {"TxMaxServiced",       0,          3},
 266 +   {"RxTotal",             0,          0},
 267 +   {"TxTotal",             0,          0},
 268 +  };
 269 +
 270 +static STATS_TABLE StatsTable2[] =
 271 +  {
 272 +   /* Name ,        Data Ptr,   Data Type */
 273 +   {"RcbPool",             0,          1},
 274 +   {"RxActQueueCount",     0,          0},
 275 +   {"RxActQueueHead",      0,          1},
 276 +   {"RxActQueueTail",      0,          1},
 277 +   {"RxActive",            0,          0},
 278 +   {"RcbStart",            0,          1},
 279 +   {"RxTeardownPending",   0,          0},
 280 +   {"TcbPool",             0,          4},
 281 +   {"TxActQueueCount",     0,          3},
 282 +   {"TxActQueueHead",      0,          4},
 283 +   {"TxActQueueTail",      0,          4},
 284 +   {"TxActive",            0,          3},
 285 +   {"TcbStart",            0,          4},
 286 +   {"TxTeardownPending",   0,          0}
 287 +  };
 288 +
 289 +static STATS_TABLE StatsTable3[] =
 290 +  {
 291 +   /* Name ,        Data Ptr,   Data Type */
 292 +   {"RxBufSize",           0,          2},
 293 +   {"RxBufferOffset",      0,          2},
 294 +   {"RxNumBuffers",        0,          2},
 295 +   {"RxServiceMax",        0,          2},
 296 +   {"TxNumBuffers",        0,          2},
 297 +   {"TxNumQueues",         0,          2},
 298 +   {"TxServiceMax",        0,          2},
 299 +#ifdef _CPHAL_AAL5
 300 +   {"CpcsUU",              0,          2},
 301 +   {"Gfc",                 0,          2},
 302 +   {"Clp",                 0,          2},
 303 +   {"Pti",                 0,          2},
 304 +   {"DaMask",              0,          2},
 305 +   {"Priority",            0,          2},
 306 +   {"PktType",             0,          2},
 307 +   {"Vci",                 0,          2},
 308 +   {"Vpi",                 0,          2},
 309 +   {"CellRate",            0,          2},
 310 +   {"QosType",             0,          2},
 311 +   {"Mbs",                 0,          2},
 312 +   {"Pcr",                 0,          2}
 313 +#endif
 314 +  };
 315 +
 316 +static STATS_TABLE StatsTable4[] =
 317 +  {
 318 +   {"Base Address",        0,          1},
 319 +   {"Offset (VLYNQ)",      0,          0},
 320 +   {"Interrupt Line",      0,          0},
 321 +   {"Debug",               0,          0},
 322 +   {"Instance",            0,          0},
 323 +#ifdef _CPHAL_AAL5
 324 +   {"UniNni",              0,          0}
 325 +#endif
 326 +  };
 327 +
 328 +static STATS_DB StatsDb[] =
 329 +  {
 330 +    {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
 331 +    {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
 332 +    {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
 333 +    {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
 334 +    {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
 335 +  };
 336 +#endif /* +GSG 030307 */
 337 +
 338 +#ifdef _CPHAL_CPMAC /* +RC 3.02 */
 339 +static void resetWait(HAL_DEVICE *HalDev)
 340 +  {                                                                  /*+RC3.02*/
 341 +  const int TickReset=64;
 342 +  osfuncSleep((int*)&TickReset);
 343 +  }                                                                  /*+RC3.02*/
 344 +#endif /* +RC 3.02 */
 345 +
 346 +/* I only define the reset base function for the modules
 347 +   that can perform a reset.  The AAL5 and AAL2 modules
 348 +   do not perform a reset, that is done by the shared module
 349 +   CPSAR */
 350 +#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
 351 +/*
 352 + *  Determines the reset register address to be used for a particular device.
 353 + *  It will search the current device entry for Locator information.  If the
 354 + *  device is a root device, there will be no Locator information, and the
 355 + *  function will find and return the root reset register.  If a Locator value
 356 + *  is found, the function will search each VLYNQ device entry in the system
 357 + *  looking for a matching Locator.  Once it finds a VLYNQ device entry with
 358 + *  a matching Locator, it will extract the "ResetBase" parameter from that
 359 + *  VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
 360 + *
 361 + *  @param  HalDev   CPHAL module instance. (set by xxxInitModule())
 362 + *  @param  ResetBase Pointer to integer address of reset register.
 363 + *
 364 + *  @return 0 OK, Non-zero not OK
 365 + */
 366 +static int ResetBaseGet(HAL_DEVICE *HalDev, bit32u *ResetBase)
 367 +  {
 368 +   char *DeviceInfo = HalDev->DeviceInfo;
 369 +   char *MyLocator, *NextLocator;
 370 +   int Inst=1;
 371 +   bit32u error_code;
 372 +
 373 +#ifdef __CPHAL_DEBUG
 374 +   if (DBG(0))
 375 +     {
 376 +      dbgPrintf("[cpcommon]ResetBaseGet(HalDev:%08x, ResetBase:%08x)\n", (bit32u)HalDev, ResetBase);
 377 +      osfuncSioFlush();
 378 +     }
 379 +#endif
 380 +
 381 +   error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &MyLocator);
 382 +   if (error_code)
 383 +     {
 384 +      /* if no Locator value, device is on the root, so get the "reset" device */
 385 +      error_code = HalDev->OsFunc->DeviceFindInfo(0, "reset", &DeviceInfo);
 386 +      if  (error_code)
 387 +        {
 388 +         return(EC_VAL_DEVICE_NOT_FOUND);
 389 +        }
 390 +
 391 +      error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "base", ResetBase);
 392 +      if (error_code)
 393 +        {
 394 +         return(EC_VAL_BASE_ADDR_NOT_FOUND);
 395 +        }
 396 +
 397 +      *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
 398 +
 399 +      /* found base address for root device, so we're done */
 400 +      return (EC_NO_ERRORS);
 401 +     }
 402 +    else
 403 +     {
 404 +      /* we have a Locator value, so the device is remote */
 405 +
 406 +      /* Find a vlynq device with a matching locator value */
 407 +      while ((HalDev->OsFunc->DeviceFindInfo(Inst, "vlynq", &DeviceInfo)) == EC_NO_ERRORS)
 408 +        {
 409 +         error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &NextLocator);
 410 +         if (error_code)
 411 +           {
 412 +            /* no Locator value for this VLYNQ, so move on */
 413 +            continue;
 414 +           }
 415 +         if (HalDev->OsFunc->Strcmpi(MyLocator, NextLocator)==0)
 416 +           {
 417 +            /* we have found a VLYNQ with a matching Locator, so extract the ResetBase */
 418 +            error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "ResetBase", ResetBase);
 419 +            if (error_code)
 420 +              {
 421 +               return(EC_VAL_BASE_ADDR_NOT_FOUND);
 422 +              }
 423 +            *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
 424 +
 425 +            /* found base address for root device, so we're done */
 426 +            return (EC_NO_ERRORS);
 427 +           }
 428 +         Inst++;
 429 +        } /* while */
 430 +     } /* else */
 431 +
 432 +   return (EC_NO_ERRORS);
 433 +  }
 434 +#endif
 435 +
 436 +#ifndef _CPHAL_AAL2 /* + RC 3.02 */
 437 +static bit32u ConfigGetCommon(HAL_DEVICE *HalDev)
 438 +  {
 439 +   bit32u ParmValue;
 440 +   bit32 error_code;
 441 +   char *DeviceInfo = HalDev->DeviceInfo;
 442 +
 443 +#ifdef __CPHAL_DEBUG
 444 +   if (DBG(0))
 445 +     {
 446 +      dbgPrintf("[cpcommon]ConfigGetCommon(HalDev:%08x)\n", (bit32u)HalDev);
 447 +      osfuncSioFlush();
 448 +     }
 449 +#endif
 450 +
 451 +   error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszBase, &ParmValue);
 452 +   if (error_code)
 453 +     {
 454 +      return(EC_FUNC_HAL_INIT|EC_VAL_BASE_ADDR_NOT_FOUND);
 455 +     }
 456 +   HalDev->dev_base = ((bit32u)PhysToVirtNoCache(ParmValue));
 457 +
 458 +#ifndef _CPHAL_AAL5
 459 +#ifndef _CPHAL_AAL2
 460 +   error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszResetBit, &ParmValue);
 461 +   if(error_code)
 462 +     {
 463 +      return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BIT_NOT_FOUND);
 464 +     }
 465 +   HalDev->ResetBit = ParmValue;
 466 +
 467 +   /* Get reset base address */
 468 +   error_code = ResetBaseGet(HalDev, &ParmValue);
 469 +   if (error_code)
 470 +     return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BASE_NOT_FOUND);
 471 +   HalDev->ResetBase = ParmValue;
 472 +#endif
 473 +#endif
 474 +
 475 +#ifndef _CPHAL_CPSAR
 476 +   error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszIntLine,&ParmValue);
 477 +   if (error_code)
 478 +     {
 479 +      return(EC_FUNC_HAL_INIT|EC_VAL_INTERRUPT_NOT_FOUND);
 480 +     }
 481 +   HalDev->interrupt = ParmValue;
 482 +#endif
 483 +
 484 +   /* only look for the offset if there is a Locator field, which indicates that
 485 +      the module is a VLYNQ module */
 486 +   error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszLocator,&ParmValue);
 487 +   if (!error_code)
 488 +     {
 489 +      error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszOffset,&ParmValue);
 490 +      if (error_code)
 491 +        {
 492 +         return(EC_FUNC_HAL_INIT|EC_VAL_OFFSET_NOT_FOUND);
 493 +        }
 494 +      HalDev->offset = ParmValue;
 495 +     }
 496 +    else
 497 +      HalDev->offset = 0;
 498 +
 499 +   error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszDebug, &ParmValue);
 500 +   if (!error_code) HalDev->debug = ParmValue;
 501 +
 502 +   return (EC_NO_ERRORS);
 503 +  }
 504 +#endif /* +RC 3.02 */
 505 +
 506 +#ifdef _CPHAL_CPMAC /* +RC 3.02 */
 507 +static void StatsInit(HAL_DEVICE *HalDev)                             /* +() RC3.02 */
 508 +  {
 509 +   /* even though these statistics may be for multiple channels and
 510 +      queues, i need only configure the pointer to the beginning
 511 +      of the array, and I can index from there if necessary */
 512 +
 513 +#ifdef _CPHAL_AAL5
 514 +   StatsTable0[0].StatPtr  = &HalDev->Stats.CrcErrors[0];
 515 +   StatsTable0[1].StatPtr  = &HalDev->Stats.LenErrors[0];
 516 +   StatsTable0[2].StatPtr  = &HalDev->Stats.AbortErrors[0];
 517 +   StatsTable0[3].StatPtr  = &HalDev->Stats.StarvErrors[0];
 518 +
 519 +   StatsTable1[0].StatPtr  = &HalDev->Stats.DmaLenErrors[0];
 520 +   StatsTable1[1].StatPtr  = &HalDev->Stats.TxMisQCnt[0][0];
 521 +   StatsTable1[2].StatPtr  = &HalDev->Stats.RxMisQCnt[0];
 522 +   StatsTable1[3].StatPtr  = &HalDev->Stats.TxEOQCnt[0][0];
 523 +   StatsTable1[4].StatPtr  = &HalDev->Stats.RxEOQCnt[0];
 524 +   StatsTable1[5].StatPtr  = &HalDev->Stats.RxPacketsServiced[0];
 525 +   StatsTable1[6].StatPtr  = &HalDev->Stats.TxPacketsServiced[0][0];
 526 +   StatsTable1[7].StatPtr  = &HalDev->Stats.RxMaxServiced;
 527 +   StatsTable1[8].StatPtr  = &HalDev->Stats.TxMaxServiced[0][0];
 528 +   StatsTable1[9].StatPtr  = &HalDev->Stats.RxTotal;
 529 +   StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
 530 +#endif
 531 +
 532 +#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC))
 533 +   StatsTable2[0].StatPtr  = (bit32u *)&HalDev->RcbPool[0];
 534 +   StatsTable2[1].StatPtr  = &HalDev->RxActQueueCount[0];
 535 +   StatsTable2[2].StatPtr  = (bit32u *)&HalDev->RxActQueueHead[0];
 536 +   StatsTable2[3].StatPtr  = (bit32u *)&HalDev->RxActQueueTail[0];
 537 +   StatsTable2[4].StatPtr  = &HalDev->RxActive[0];
 538 +   StatsTable2[5].StatPtr  = (bit32u *)&HalDev->RcbStart[0];
 539 +   StatsTable2[6].StatPtr  = &HalDev->RxTeardownPending[0];
 540 +   StatsTable2[7].StatPtr  = (bit32u *)&HalDev->TcbPool[0][0];
 541 +   StatsTable2[8].StatPtr  = &HalDev->TxActQueueCount[0][0];
 542 +   StatsTable2[9].StatPtr  = (bit32u *)&HalDev->TxActQueueHead[0][0];
 543 +   StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
 544 +   StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
 545 +   StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
 546 +   StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
 547 +
 548 +   StatsTable3[0].StatPtr  = &HalDev->ChData[0].RxBufSize;
 549 +   StatsTable3[1].StatPtr  = &HalDev->ChData[0].RxBufferOffset;
 550 +   StatsTable3[2].StatPtr  = &HalDev->ChData[0].RxNumBuffers;
 551 +   StatsTable3[3].StatPtr  = &HalDev->ChData[0].RxServiceMax;
 552 +   StatsTable3[4].StatPtr  = &HalDev->ChData[0].TxNumBuffers;
 553 +   StatsTable3[5].StatPtr  = &HalDev->ChData[0].TxNumQueues;
 554 +   StatsTable3[6].StatPtr  = &HalDev->ChData[0].TxServiceMax;
 555 +#ifdef _CPHAL_AAL5
 556 +   StatsTable3[7].StatPtr  = &HalDev->ChData[0].CpcsUU;
 557 +   StatsTable3[8].StatPtr  = &HalDev->ChData[0].Gfc;
 558 +   StatsTable3[9].StatPtr  = &HalDev->ChData[0].Clp;
 559 +   StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
 560 +   StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
 561 +   StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
 562 +   StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
 563 +   StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
 564 +   StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
 565 +   StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
 566 +   StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
 567 +   StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
 568 +   StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
 569 +#endif
 570 +#endif
 571 +
 572 +   StatsTable4[0].StatPtr  = &HalDev->dev_base;
 573 +   StatsTable4[1].StatPtr  = &HalDev->offset;
 574 +   StatsTable4[2].StatPtr  = &HalDev->interrupt;
 575 +   StatsTable4[3].StatPtr  = &HalDev->debug;
 576 +   StatsTable4[4].StatPtr  = &HalDev->Inst;
 577 +  }
 578 +#endif /* +RC 3.02 */
 579 +
 580 +#ifndef _CPHAL_CPSAR /* +RC 3.02 */
 581 +#ifndef _CPHAL_AAL2 /* +RC 3.02 */
 582 +/*
 583 + *  Returns statistics information.
 584 + *
 585 + *  @param  HalDev   CPHAL module instance. (set by xxxInitModule())
 586 + *
 587 + *  @return 0
 588 + */
 589 +static int StatsGet(HAL_DEVICE *HalDev, void **StatPtr, int Index, int Ch, int Queue)
 590 +  {
 591 +   int Size;
 592 +   bit32u *AddrPtr;
 593 +   char *DataPtr;
 594 +   STATS_TABLE *StatsTable;
 595 +   int i, NumberOfStats;
 596 +
 597 +#ifdef __CPHAL_DEBUG
 598 +   if (DBG(0))
 599 +     {
 600 +      dbgPrintf("[cpcommon]StatsGet(HalDev:%08x, StatPtr:%08x)\n",
 601 +                (bit32u)HalDev, (bit32u)StatPtr);
 602 +      osfuncSioFlush();
 603 +     }
 604 +#endif
 605 +
 606 +   StatsTable = StatsDb[Index].StatTable;
 607 +   NumberOfStats = StatsDb[Index].NumberOfStats;
 608 +
 609 +   Size = sizeof(bit32u)*((NumberOfStats*2)+1);
 610 +   Size += (NumberOfStats*11);
 611 +   *StatPtr = (bit32u *)HalDev->OsFunc->Malloc(Size);
 612 +
 613 +   AddrPtr = (bit32u *) *StatPtr;
 614 +   DataPtr = (char *)AddrPtr;
 615 +   DataPtr += sizeof(bit32u)*((NumberOfStats*2)+1);
 616 +
 617 +   for (i=0; i<NumberOfStats; i++)
 618 +     {
 619 +      *AddrPtr++ = (bit32u)StatsTable[i].StatName;
 620 +      *AddrPtr++ = (bit32u)DataPtr;
 621 +      if (&StatsTable[i].StatPtr[Ch] != 0)
 622 +        {
 623 +         switch(StatsTable[i].DataType)
 624 +           {
 625 +            case 0:
 626 +              HalDev->OsFunc->Sprintf(DataPtr, "%d", (bit32u *)StatsTable[i].StatPtr[Ch]);
 627 +              break;
 628 +            case 1:
 629 +              HalDev->OsFunc->Sprintf(DataPtr, "0x%x", (bit32u *)StatsTable[i].StatPtr[Ch]);
 630 +              break;
 631 +            case 2:
 632 +              HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch * (sizeof(CHANNEL_INFO)/4))));
 633 +              break;
 634 +            case 3:
 635 +              HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
 636 +              break;
 637 +            case 4:
 638 +              HalDev->OsFunc->Sprintf(DataPtr, "0x%x", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
 639 +              break;
 640 +            default:
 641 +              /* invalid data type, due to CPHAL programming error */
 642 +              break;
 643 +           }
 644 +        }
 645 +       else
 646 +        {
 647 +         /* invalid statistics pointer, probably was not initialized */
 648 +        }
 649 +      DataPtr += HalDev->OsFunc->Strlen(DataPtr) + 1;
 650 +     }
 651 +
 652 +   *AddrPtr = (bit32u) 0;
 653 +
 654 +   return (EC_NO_ERRORS);
 655 +  }
 656 +#endif /* +RC 3.02 */
 657 +#endif /* +RC 3.02 */
 658 +
 659 +#ifdef _CPHAL_CPMAC
 660 +static void gpioFunctional(int base, int bit)
 661 +  {                                                                  /*+RC3.02*/
 662 +  bit32u GpioEnr = base + 0xC;
 663 +  /*  To make functional, set to zero  */
 664 +  *(volatile bit32u *)(GpioEnr) &= ~(1 << bit);                      /*+RC3.02*/
 665 +  }                                                                  /*+RC3.02*/
 666 +
 667 +
 668 +/*+RC3.02*/
 669 +/* Common function, Checks to see if GPIO should be in functional mode */
 670 +static void gpioCheck(HAL_DEVICE *HalDev, void *moduleDeviceInfo)
 671 +  {                                                                  /*+RC3.02*/
 672 +  int rc;
 673 +  void *DeviceInfo;
 674 +  char *pszMuxBits;
 675 +  char pszMuxBit[20];
 676 +  char *pszTmp;
 677 +  char szMuxBit[20];
 678 +  char *ptr;
 679 +  int base;
 680 +  int reset_bit;
 681 +  int bit;
 682 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
 683 +
 684 +  rc = OsFunc->DeviceFindParmValue(moduleDeviceInfo, "gpio_mux",&pszTmp);
 685 +  if(rc) return;
 686 +  /*  gpio entry found, get GPIO register info and make functional  */
 687 +
 688 +  /* temp copy until FinParmValue fixed */
 689 +  ptr = &szMuxBit[0];
 690 +  while ((*ptr++ = *pszTmp++));
 691 +
 692 +  pszMuxBits = &szMuxBit[0];
 693 +
 694 +  rc = OsFunc->DeviceFindInfo(0,"gpio",&DeviceInfo);
 695 +  if(rc) return;
 696 +
 697 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",&base);
 698 +  if(rc) return;
 699 +
 700 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
 701 +  if(rc) return;
 702 +
 703 +  /* If GPIO still in reset, then exit  */
 704 +  if((VOLATILE32(HalDev->ResetBase) & (1 << reset_bit)) == 0)
 705 +    return;
 706 +  /*  format for gpio_mux is  gpio_mux = <int>;<int>;<int>...*/
 707 +  while (*pszMuxBits)
 708 +    {
 709 +    pszTmp = &pszMuxBit[0];
 710 +    if(*pszMuxBits == ';') pszMuxBits++;
 711 +    while ((*pszMuxBits != ';') && (*pszMuxBits != '\0'))
 712 +      {
 713 +      osfuncSioFlush();
 714 +      /*If value not a number, skip */
 715 +      if((*pszMuxBits < '0') || (*pszMuxBits > '9'))
 716 +        pszMuxBits++;
 717 +      else
 718 +        *pszTmp++ = *pszMuxBits++;
 719 +      }
 720 +    *pszTmp = '\0';
 721 +    bit = OsFunc->Strtoul(pszMuxBit, &pszTmp, 10);
 722 +    gpioFunctional(base, bit);
 723 +    resetWait(HalDev);  /* not sure if this is needed */
 724 +    }
 725 +  }                                                                  /*+RC3.02*/
 726 +#endif  /* CPMAC  */
 727 +
 728 +#ifdef _CPHAL_AAL5
 729 +const char hcSarFrequency[] = "SarFreq";
 730 +#endif
 731 +
 732 +#endif  /* _INC  */
 733 diff -urN linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.h
 734 --- linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.h      1970-01-01 01:00:00.000000000 +0100
 735 +++ linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.h      2005-07-12 02:48:41.996601000 +0200
 736 @@ -0,0 +1,79 @@
 737 +#ifndef _INC_CPCOMMON_H
 738 +#define _INC_CPCOMMON_H
 739 +
 740 +#define VOLATILE32(addr)  (*(volatile bit32u *)(addr))
 741 +#ifndef dbgPrintf
 742 +#define dbgPrintf HalDev->OsFunc->Printf
 743 +#endif
 744 +
 745 +#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
 746 +
 747 +#define DBG(level)  (HalDev->debug & (1<<(level)))
 748 +/*
 749 +#define DBG0()      DBG(0)
 750 +#define DBG1()      DBG(1)
 751 +#define DBG2()      DBG(2)
 752 +#define DBG3()      DBG(3)
 753 +#define DBG4()      DBG(4)
 754 +#define DBG5()      DBG(5)
 755 +#define DBG6()      DBG(6)
 756 +#define DBG7()      DBG(7)
 757 +*/
 758 +
 759 +/*
 760 + *  List of defined actions for use with Control().
 761 + */
 762 +typedef enum
 763 +  {
 764 +   enGET=0,     /**< Get the value associated with a key */
 765 +   enSET,       /**< Set the value associates with a key */
 766 +   enCLEAR,     /**<Clear the value */
 767 +   enNULL       /**< No data action, used to initiate a service or send a message */
 768 +  }ACTION;
 769 +
 770 +/*
 771 + *  Enumerated hardware states.
 772 + */
 773 +typedef enum
 774 +  {
 775 +   enConnected=1, enDevFound, enInitialized, enOpened
 776 +  }DEVICE_STATE;
 777 +
 778 +typedef enum
 779 +  {
 780 +   enCommonStart=0,
 781 +   /* General  */
 782 +   enOff, enOn, enDebug,
 783 +   /* Module General */
 784 +   enCpuFreq,
 785 +   enStatus,
 786 +   enCommonEnd
 787 +   }COMMON_KEY;
 788 +
 789 +typedef struct
 790 +  {
 791 +   const char  *strKey;
 792 +   int  enKey;
 793 +  }CONTROL_KEY;
 794 +
 795 +typedef struct
 796 +  {
 797 +   char *StatName;
 798 +   unsigned int *StatPtr;
 799 +   int DataType; /* 0: int, 1: hex int, 2:channel data */
 800 +  }STATS_TABLE;
 801 +
 802 +typedef struct
 803 +  {
 804 +   int NumberOfStats;
 805 +   STATS_TABLE *StatTable;
 806 +  }STATS_DB;
 807 +
 808 +#define osfuncSioFlush()    HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",pszNULL,0)
 809 +#define osfuncSleep(Ticks)  HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)
 810 +#define osfuncStateChange() HalDev->OsFunc->Control(HalDev->OsDev,pszStateChange,pszNULL,0)
 811 +
 812 +#define CHANNEL_NAMES {"Ch0","Ch1","Ch2","Ch3","Ch4","Ch5","Ch6","Ch7","Ch8","Ch9","Ch10","Ch11","Ch12","Ch13","Ch14","Ch15"}
 813 +
 814 +#endif
 815 +
 816 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpmac.c
 817 --- linux.old/drivers/net/avalanche_cpmac/cpmac.c       1970-01-01 01:00:00.000000000 +0100
 818 +++ linux.dev/drivers/net/avalanche_cpmac/cpmac.c       2005-07-12 03:21:00.298934472 +0200
 819 @@ -0,0 +1,2509 @@
 820 +/******************************************************************************
 821 + * FILE PURPOSE:    CPMAC Linux Network Device Driver Source
 822 + ******************************************************************************
 823 + * FILE NAME:       cpmac.c
 824 + *
 825 + * DESCRIPTION:     CPMAC Network Device Driver Source
 826 + *
 827 + * REVISION HISTORY:
 828 + *
 829 + * Date           Description                               Author
 830 + *-----------------------------------------------------------------------------
 831 + * 27 Nov 2002    Initial Creation                          Suraj S Iyer
 832 + * 09 Jun 2003    Updates for GA                            Suraj S Iyer
 833 + * 30 Sep 2003    Updates for LED, Reset stats              Suraj S Iyer
 834 + *
 835 + * (C) Copyright 2003, Texas Instruments, Inc
 836 + *******************************************************************************/
 837 +#include <linux/kernel.h>
 838 +#include <linux/module.h>
 839 +#include <linux/init.h>
 840 +#include <linux/netdevice.h>
 841 +#include <linux/etherdevice.h>
 842 +#include <linux/delay.h>
 843 +#include <linux/spinlock.h>
 844 +#include <linux/proc_fs.h>
 845 +#include <linux/ioport.h>
 846 +#include <asm/io.h>
 847 +
 848 +#include <linux/skbuff.h>
 849 +
 850 +#include <asm/mips-boards/prom.h>
 851 +#include <linux/string.h>
 852 +#include <asm/uaccess.h>
 853 +#include <linux/config.h>
 854 +#include <asm/ar7/if_port.h>
 855 +
 856 +extern void build_psp_config(void);
 857 +extern void psp_config_cleanup(void);
 858 +
 859 +#include "cpmacHalLx.h"
 860 +#include "cpmac.h"
 861 +
 862 +static struct net_device *last_cpmac_device = NULL;
 863 +static int    cpmac_devices_installed = 0;
 864 +
 865 +void xdump( u_char*  cp, int  length, char*  prefix );
 866 +
 867 +unsigned int  cpmac_cpu_freq = 0;
 868 +
 869 +char cpmac_version[] = "1.5";
 870 +
 871 +char l3_align_array[]            = {0x02, 0x01, 0x00, 0x03};
 872 +#define L3_ALIGN(i)                l3_align_array[i]
 873 +
 874 +char add_for_4byte_align[]       = {0x04, 0x03, 0x02, 0x05};
 875 +#define ADD_FOR_4BYTE_ALIGN(i)     add_for_4byte_align[i]
 876 +
 877 +
 878 +#define TPID                       0x8100
 879 +#define IS_802_1Q_FRAME(byte_ptr)  (*(unsigned short*)byte_ptr == TPID)
 880 +#define TPID_START_OFFSET          12
 881 +#define TCI_START_OFFSET           14
 882 +#define TCI_LENGTH                 2
 883 +#define TPID_LENGTH                2
 884 +#define TPID_END_OFFSET            (TPID_START_OFFSET + TPID_LENGTH)
 885 +#define TCI_END_OFFSET             (TCI_START_OFFSET  + TCI_LENGTH)
 886 +#define IS_VALID_VLAN_ID(byte_ptr) ((*(unsigned short*)byte_ptr) && 0xfff != 0)
 887 +#define MAX_CLASSES                8
 888 +#define MAX_USER_PRIORITY          8
 889 +#define CONTROL_802_1Q_SIZE        (TCI_LENGTH + TPID_LENGTH)
 890 +
 891 +unsigned char user_priority_to_traffic_class_map[MAX_CLASSES][MAX_USER_PRIORITY] =
 892 +{
 893 +  {0, 0, 0, 1, 1, 1, 1, 2},
 894 +  {0, 0, 0, 0, 0, 0, 0, 0},
 895 +  {0, 0, 0, 0, 0, 0, 0, 1},
 896 +  {0, 0, 0, 1, 1, 2, 2, 3},
 897 +  {0, 1, 1, 2, 2, 3, 3, 4},
 898 +  {0, 1, 1, 2, 3, 4, 4, 5},
 899 +  {0, 1, 2, 3, 4, 5, 5, 6},
 900 +  {0, 1, 2, 3, 4, 5, 6, 7}
 901 +};
 902 +
 903 +#define GET_802_1P_CHAN(x,y) user_priority_to_traffic_class_map[x][(y & 0xe0)]
 904 +
 905 +#if defined(CONFIG_MIPS_SEAD2)
 906 +unsigned long temp_base_address[2] = {0xa8610000, 0xa8612800};
 907 +unsigned long temp_reset_value[2] = { 1<< 17,1<<21};
 908 +#define RESET_REG_PRCR   (*(volatile unsigned int *)((0xa8611600 + 0x0)))
 909 +#define VERSION(base)   (*(volatile unsigned int *)(((base)|0xa0000000) + 0x0))
 910 +#endif
 911 +
 912 +MODULE_AUTHOR("Maintainer: Suraj S Iyer <ssiyer@ti.com>");
 913 +MODULE_DESCRIPTION("Driver for TI CPMAC");
 914 +
 915 +static int cfg_link_speed = 0;
 916 +MODULE_PARM(cfg_link_speed, "i");
 917 +MODULE_PARM_DESC(cfg_link_speed, "Fixed speed of the Link: <100/10>");
 918 +
 919 +static char *cfg_link_mode = NULL;
 920 +MODULE_PARM(cfg_link_mode, "1-3s");
 921 +MODULE_PARM_DESC(cfg_link_mode, "Fixed mode of the Link: <fd/hd>");
 922 +
 923 +int cpmac_debug_mode = 0;
 924 +MODULE_PARM(debug_mode, "i");
 925 +MODULE_PARM_DESC(debug_mode, "Turn on the debug info: <0/1>. Default is 0 (off)");
 926 +
 927 +#define dbgPrint if (cpmac_debug_mode) printk
 928 +#define errPrint printk
 929 +
 930 +static int g_cfg_start_link_params = CFG_START_LINK_SPEED;
 931 +static int g_init_enable_flag      = 0;
 932 +static int cfg_start_link_speed;
 933 +static int cpmac_max_frame_size;
 934 +
 935 +static struct net_device *g_dev_array[2];
 936 +static struct proc_dir_entry *gp_stats_file = NULL;
 937 +
 938 +//-----------------------------------------------------------------------------
 939 +// Statistics related private functions.
 940 +//-----------------------------------------------------------------------------
 941 +static int  cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *len);
 942 +static int  cpmac_p_read_rfc2665_stats(char *buf, char **start, off_t offset, int count, int *eof, void *data);
 943 +static int  cpmac_p_read_link(char *buf, char **start, off_t offset, int count, int *eof, void *data);
 944 +static int  cpmac_p_read_stats(char* buf, char **start, off_t offset, int count, int *eof, void *data);
 945 +static int  cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data);
 946 +static int  cpmac_p_reset_statistics (struct net_device *p_dev);
 947 +static int  cpmac_p_get_version(char *buf, char **start, off_t offset, int count, int *eof, void *data);
 948 +
 949 +static int  cpmac_p_detect_manual_cfg(int, char*, int);
 950 +static int  cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
 951 +
 952 +//-----------------------------------------------------------------------------
 953 +// Timer related private functions.
 954 +//-----------------------------------------------------------------------------
 955 +static int  cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
 956 +// static int  cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
 957 +static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param);
 958 +inline static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks);
 959 +static int  cpmac_p_stop_timer(struct timer_list *p_timer);
 960 +
 961 +//------------------------------------------------------------------------------
 962 +// Device configuration and setup related private functions.
 963 +//------------------------------------------------------------------------------
 964 +static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv, unsigned long *p_dev_flags);
 965 +static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
 966 +inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan);
 967 +
 968 +//-----------------------------------------------------------------------------
 969 +// Net device related private functions.
 970 +//-----------------------------------------------------------------------------
 971 +static int  cpmac_dev_init(struct net_device *p_dev);
 972 +static int  cpmac_dev_open( struct net_device *dev );
 973 +static int  cpmac_dev_close(struct net_device *p_dev);
 974 +static void cpmac_dev_mcast_set(struct net_device *p_dev);
 975 +static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr);
 976 +static int  cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev);
 977 +static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *dev);
 978 +
 979 +static int cpmac_p_dev_enable( struct net_device *p_dev);
 980 +
 981 +
 982 +
 983 +/* Max. Reserved headroom in front of each packet so that the headers can be added to
 984 + * a packet. Worst case scenario would be PPPoE + 2684 LLC Encapsulation + Ethernet
 985 + * header. */
 986 +#define MAX_RESERVED_HEADROOM       20
 987 +
 988 +/* This is the MAX size of the static buffer for pure data. */
 989 +#define MAX_SIZE_STATIC_BUFFER      1600
 990 +
 991 +typedef struct DRIVER_BUFFER
 992 +{
 993 +       /* Pointer to the allocated data buffer. This is the static data buffer
 994 +     * allocated for the TI-Cache. 60 bytes out of the below buffer are required
 995 +     * by the SKB shared info. We always reserve at least MAX_RESERVED_HEADROOM bytes
 996 +     * so that the packets always have sufficient headroom. */
 997 +       char                                    ptr_buffer[MAX_SIZE_STATIC_BUFFER + MAX_RESERVED_HEADROOM + 60];
 998 +
 999 +       /* List of the driver buffers. */
1000 +       struct DRIVER_BUFFER*   ptr_next;
1001 +}DRIVER_BUFFER;
1002 +
1003 +typedef struct DRIVER_BUFFER_MCB
1004 +{
1005 +       /* List of the driver buffers. */
1006 +       DRIVER_BUFFER*  ptr_available_driver_buffers;
1007 +
1008 +    /* The number of available buffers. */
1009 +    int                     num_available_buffers;
1010 +}DRIVER_BUFFER_MCB;
1011 +
1012 +DRIVER_BUFFER_MCB      driver_mcb;
1013 +int                 hybrid_mode = 0;
1014 +
1015 +static union {
1016 +       struct sk_buff_head     list;
1017 +       char                    pad[SMP_CACHE_BYTES];
1018 +} skb_head_pool[NR_CPUS];
1019 +
1020 +/**************************************************************************
1021 + * FUNCTION NAME : ti_release_skb
1022 + **************************************************************************
1023 + * DESCRIPTION   :
1024 + *  This function is called from the ti_alloc_skb when there were no more
1025 + *  data buffers available. The allocated SKB had to released back to the
1026 + *  data pool. The reason why this function was moved from the fast path
1027 + *  below was because '__skb_queue_head' is an inline function which adds
1028 + *  a large code chunk on the fast path.
1029 + *
1030 + * NOTES         :
1031 + *  This function is called with interrupts disabled.
1032 + **************************************************************************/
1033 +static void ti_release_skb (struct sk_buff_head* list, struct sk_buff* skb)
1034 +{
1035 +    __skb_queue_head(list, skb);
1036 +    return;
1037 +}
1038 +
1039 +/**************************************************************************
1040 + * FUNCTION NAME : ti_alloc_skb
1041 + **************************************************************************
1042 + * DESCRIPTION   :
1043 + *  The function is called to allocate memory from the static allocated
1044 + *  TI-Cached memory pool.
1045 + *
1046 + * RETURNS       :
1047 + *      Allocated static memory buffer - Success
1048 + *      NULL                           - Error.
1049 + **************************************************************************/
1050 +struct sk_buff *ti_alloc_skb(unsigned int size,int gfp_mask)
1051 +{
1052 +    register struct sk_buff*    skb;
1053 +    unsigned long               flags;
1054 +       struct sk_buff_head*        list;
1055 +       DRIVER_BUFFER*              ptr_node = NULL;
1056 +
1057 +    /* Critical Section Begin: Lock out interrupts. */
1058 +    local_irq_save(flags);
1059 +
1060 +    /* Get the SKB Pool list associated with the processor and dequeue the head. */
1061 +    list = &skb_head_pool[smp_processor_id()].list;
1062 +    skb = __skb_dequeue(list);
1063 +
1064 +    /* Align the data size. */
1065 +    size = SKB_DATA_ALIGN(size);
1066 +
1067 +    /* Did we get one. */
1068 +    if (skb != NULL)
1069 +    {
1070 +        /* YES. Now get a data block from the head of statically allocated block. */
1071 +        ptr_node = driver_mcb.ptr_available_driver_buffers;
1072 +           if (ptr_node != NULL)
1073 +        {
1074 +            /* YES. Got a data block. Advance the free list pointer to the next available buffer. */
1075 +               driver_mcb.ptr_available_driver_buffers = ptr_node->ptr_next;
1076 +            ptr_node->ptr_next = NULL;
1077 +
1078 +            /* Decrement the number of available data buffers. */
1079 +            driver_mcb.num_available_buffers = driver_mcb.num_available_buffers - 1;
1080 +        }
1081 +        else
1082 +        {
1083 +          /* NO. Was unable to get a data block. So put the SKB back on the free list.
1084 +           * This is slow path. */
1085 +#ifdef DEBUG_SKB
1086 +           printk ("DEBUG: No Buffer memory available: Number of free buffer:%d.\n",
1087 +                   driver_mcb.num_available_buffers);
1088 +#endif
1089 +           ti_release_skb (list, skb);
1090 +        }
1091 +    }
1092 +
1093 +    /* Critical Section End: Unlock interrupts. */
1094 +    local_irq_restore(flags);
1095 +
1096 +    /* Did we get an SKB and data buffer. Proceed only if we were succesful in getting both else drop */
1097 +    if (skb != NULL && ptr_node != NULL)
1098 +    {
1099 +               /* XXX: does not include slab overhead */
1100 +        skb->truesize = size + sizeof(struct sk_buff);
1101 +
1102 +        /* Load the data pointers. */
1103 +       skb->head = ptr_node->ptr_buffer;
1104 +        skb->data = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
1105 +           skb->tail = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
1106 +        skb->end  = ptr_node->ptr_buffer + size + MAX_RESERVED_HEADROOM;
1107 +
1108 +           /* Set up other state */
1109 +       skb->len    = 0;
1110 +       skb->cloned = 0;
1111 +        skb->data_len = 0;
1112 +
1113 +        /* Mark the SKB indicating that the SKB is from the TI cache. */
1114 +        skb->cb[45] = 1;
1115 +
1116 +       atomic_set(&skb->users, 1);
1117 +       atomic_set(&(skb_shinfo(skb)->dataref), 1);
1118 +        skb_shinfo(skb)->nr_frags = 0;
1119 +           skb_shinfo(skb)->frag_list = NULL;
1120 +        return skb;
1121 +    }
1122 +    else
1123 +    {
1124 +        /* Control comes here only when there is no statically allocated data buffers
1125 +         * available. This case is handled using the mode selected
1126 +         *
1127 +         * 1. Hybrid Mode.
1128 +         *  In that case lets jump to the old allocation code. This way we
1129 +         *  can allocate a small number of data buffers upfront and the rest will hit
1130 +         *  this portion of the code, which is slow path. Note the number of hits here
1131 +         *  should be kept as low as possible to satisfy performance requirements.
1132 +         *
1133 +         * 2. Pure Static Mode.
1134 +         *  Return NULL the user should have tuned the number of static buffers for
1135 +         *  worst case scenario. So return NULL and let the drivers handle the error. */
1136 +        if (hybrid_mode == 1)
1137 +        {
1138 +            /* Hybrid Mode: Old allocation. */
1139 +            return dev_alloc_skb(size);
1140 +        }
1141 +        else
1142 +        {
1143 +            /* Pure Static Mode: No buffers available. */
1144 +            return NULL;
1145 +        }
1146 +    }
1147 +}
1148 +
1149 +/**************************************************************************
1150 + * FUNCTION NAME : ti_skb_release_fragment
1151 + **************************************************************************
1152 + * DESCRIPTION   :
1153 + *  This function is called to release fragmented packets. This is NOT in
1154 + *  the fast path and this function requires some work.
1155 + **************************************************************************/
1156 +static void ti_skb_release_fragment(struct sk_buff *skb)
1157 +{
1158 +    if (skb_shinfo(skb)->nr_frags)
1159 +    {
1160 +        /* PANKAJ TODO: This portion has not been tested. */
1161 +           int i;
1162 +#ifdef DEBUG_SKB
1163 +        printk ("DEBUG: Releasing fragments in TI-Cached code.\n");
1164 +#endif
1165 +               for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1166 +                   printk ("DEBUG: Fragmented Page = 0x%p.\n", skb_shinfo(skb)->frags[i].page);
1167 +    }
1168 +
1169 +    /* Check if there were any fragments present and if so clean all the SKB's.
1170 +     * This is required to recursivly clean the SKB's. */
1171 +       if (skb_shinfo(skb)->frag_list)
1172 +           skb_drop_fraglist(skb);
1173 +
1174 +    return;
1175 +}
1176 +
1177 +/**************************************************************************
1178 + * FUNCTION NAME : ti_skb_release_data
1179 + **************************************************************************
1180 + * DESCRIPTION   :
1181 + *  The function is called to release the SKB back into the TI-Cached static
1182 + *  memory pool.
1183 + **************************************************************************/
1184 +static void ti_skb_release_data(struct sk_buff *skb)
1185 +{
1186 +    DRIVER_BUFFER*     ptr_node;
1187 +    unsigned long   flags;
1188 +
1189 +    /* The SKB data can be cleaned only if the packet has not been cloned and we
1190 +     * are the only one holding a reference to the data. */
1191 +       if (!skb->cloned || atomic_dec_and_test(&(skb_shinfo(skb)->dataref)))
1192 +    {
1193 +        /* Are there any fragments associated with the SKB ?*/
1194 +               if ((skb_shinfo(skb)->nr_frags != 0) || (skb_shinfo(skb)->frag_list != NULL))
1195 +        {
1196 +            /* Slow Path: Try and clean up the fragments. */
1197 +            ti_skb_release_fragment (skb);
1198 +        }
1199 +
1200 +        /* Cleanup the SKB data memory. This is fast path. */
1201 +        ptr_node = (DRIVER_BUFFER *)skb->head;
1202 +
1203 +        /* Critical Section: Lock out interrupts. */
1204 +        local_irq_save(flags);
1205 +
1206 +        /* Add the data buffer to the list of available buffers. */
1207 +        ptr_node->ptr_next = driver_mcb.ptr_available_driver_buffers;
1208 +           driver_mcb.ptr_available_driver_buffers = ptr_node;
1209 +
1210 +        /* Increment the number of available data buffers. */
1211 +        driver_mcb.num_available_buffers = driver_mcb.num_available_buffers + 1;
1212 +
1213 +        /* Criticial Section: Unlock interrupts. */
1214 +        local_irq_restore(flags);
1215 +       }
1216 +    return;
1217 +}
1218 +
1219 +
1220 +
1221 +
1222 +static unsigned char str2hexnum(unsigned char c)
1223 +{
1224 +        if(c >= '0' && c <= '9')
1225 +                return c - '0';
1226 +        if(c >= 'a' && c <= 'f')
1227 +                return c - 'a' + 10;
1228 +        if(c >= 'A' && c <= 'F')
1229 +                return c - 'A' + 10;
1230 +        return 0;
1231 +}
1232 +
1233 +static void str2eaddr(unsigned char *ea, unsigned char *str)
1234 +{
1235 +    int i;
1236 +    unsigned char num;
1237 +    for(i = 0; i < 6; i++) {
1238 +        if((*str == '.') || (*str == ':'))
1239 +            str++;
1240 +        num = str2hexnum(*str++) << 4;
1241 +        num |= (str2hexnum(*str++));
1242 +        ea[i] = num;
1243 +    }
1244 +}
1245 +
1246 +//-----------------------------------------------------------------------------
1247 +// Statistics related private functions.
1248 +//-----------------------------------------------------------------------------
1249 +static int cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *p_len)
1250 +{
1251 +    int                 ret_val   = -1;
1252 +    unsigned long rx_hal_errors   = 0;
1253 +    unsigned long rx_hal_discards = 0;
1254 +    unsigned long tx_hal_errors   = 0;
1255 +    unsigned long ifOutDiscards   = 0;
1256 +    unsigned long ifInDiscards    = 0;
1257 +    unsigned long ifOutErrors     = 0;
1258 +    unsigned long ifInErrors      = 0;
1259 +
1260 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1261 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cpmac_priv->drv_hal;
1262 +    CPMAC_DEVICE_MIB_T   *p_device_mib = p_cpmac_priv->device_mib;
1263 +    CPMAC_DRV_STATS_T    *p_stats      = p_cpmac_priv->stats;
1264 +    CPMAC_DEVICE_MIB_T   local_mib;
1265 +    CPMAC_DEVICE_MIB_T   *p_local_mib  = &local_mib;
1266 +
1267 +    struct net_device_stats *p_net_dev_stats = &p_cpmac_priv->net_dev_stats;
1268 +
1269 +    int                 len      = 0;
1270 +    int  dev_mib_elem_count      = 0;
1271 +
1272 +    /* do not access the hardware if it is in the reset state. */
1273 +    if(!test_bit(0, &p_cpmac_priv->set_to_close))
1274 +    {
1275 +        if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsDump", "Get",
1276 +                                        p_local_mib) != 0)
1277 +        {
1278 +            errPrint("The stats dump for %s is failing.\n", p_dev->name);
1279 +            return(ret_val);
1280 +        }
1281 +
1282 +        p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
1283 +
1284 +        dev_mib_elem_count = sizeof(CPMAC_DEVICE_MIB_T)/sizeof(unsigned long);
1285 +
1286 +        /* Update the history of the stats. This takes care of any reset of the
1287 +         * device and stats that might have taken place during the life time of
1288 +         * the driver.
1289 +         */
1290 +        while(dev_mib_elem_count--)
1291 +        {
1292 +            *((unsigned long*) p_device_mib + dev_mib_elem_count) +=
1293 +            *((unsigned long*) p_local_mib  + dev_mib_elem_count);
1294 +        }
1295 +    }
1296 +
1297 +    /* RFC2665, section 3.2.7, page 9 */
1298 +    rx_hal_errors          = p_device_mib->ifInFragments       +
1299 +                            p_device_mib->ifInCRCErrors       +
1300 +                            p_device_mib->ifInAlignCodeErrors +
1301 +                            p_device_mib->ifInJabberFrames;
1302 +
1303 +    /* RFC2233 */
1304 +    rx_hal_discards        = p_device_mib->ifRxDMAOverruns;
1305 +
1306 +    /* RFC2665, section 3.2.7, page 9 */
1307 +    tx_hal_errors          = p_device_mib->ifExcessiveCollisionFrames +
1308 +                             p_device_mib->ifLateCollisions           +
1309 +                             p_device_mib->ifCarrierSenseErrors       +
1310 +                             p_device_mib->ifOutUnderrun;
1311 +
1312 +    /* if not set, the short frames (< 64 bytes) are considered as errors */
1313 +    if(!p_cpmac_priv->flags & IFF_PRIV_SHORT_FRAMES)
1314 +        rx_hal_errors += p_device_mib->ifInUndersizedFrames;
1315 +
1316 +    /* if not set, the long frames ( > 1518) are considered as errors
1317 +     * RFC2665, section 3.2.7, page 9. */
1318 +    if(!p_cpmac_priv->flags & IFF_PRIV_JUMBO_FRAMES)
1319 +        rx_hal_errors += p_device_mib->ifInOversizedFrames;
1320 +
1321 +    /* if not in promiscous, then non addr matching frames are discarded */
1322 +    /* CPMAC 2.0 Manual Section 2.8.1.14 */
1323 +    if(!p_dev->flags & IFF_PROMISC)
1324 +    {
1325 +        ifInDiscards  +=  p_device_mib->ifInFilteredFrames;
1326 +    }
1327 +
1328 +     /* total rx discards = hal discards + driver discards. */
1329 +    ifInDiscards  = rx_hal_discards + p_net_dev_stats->rx_dropped;
1330 +    ifInErrors    = rx_hal_errors;
1331 +
1332 +    ifOutErrors   = tx_hal_errors;
1333 +    ifOutDiscards = p_net_dev_stats->tx_dropped;
1334 +
1335 +    /* Let us update the net device stats struct. To be updated in the later releases.*/
1336 +    p_cpmac_priv->net_dev_stats.rx_errors  = ifInErrors;
1337 +    p_cpmac_priv->net_dev_stats.collisions = p_device_mib->ifCollisionFrames;
1338 +
1339 +    if(buf == NULL || limit == 0)
1340 +    {
1341 +        return(0);
1342 +    }
1343 +
1344 +    if(len <= limit)
1345 +        len+= sprintf(buf + len, "%-35s: %ld\n", "ifSpeed",                                 (long)p_cpmac_priv->link_speed);
1346 +    if(len <= limit)
1347 +        len+= sprintf(buf + len, "%-35s: %lu\n", "dot3StatsDuplexStatus",                   (long)p_cpmac_priv->link_mode);
1348 +    if(len <= limit)
1349 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifAdminStatus",                           (long)(p_dev->flags & IFF_UP ? 1:2));
1350 +    if(len <= limit)
1351 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOperStatus",                            (long)(((p_dev->flags & IFF_UP) && netif_carrier_ok(p_dev)) ? 1:2));
1352 +    if(len <= limit)
1353 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifLastChange",                            p_stats->start_tick);
1354 +    if(len <= limit)
1355 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInDiscards",                            ifInDiscards);
1356 +    if(len <= limit)
1357 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInErrors",                              ifInErrors);
1358 +    if(len <= limit)
1359 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutDiscards",                           ifOutDiscards);
1360 +    if(len <= limit)
1361 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutErrors",                             ifOutErrors);
1362 +    if(len <= limit)
1363 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInGoodFrames",                          p_device_mib->ifInGoodFrames);
1364 +    if(len <= limit)
1365 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInBroadcasts",                          p_device_mib->ifInBroadcasts);
1366 +    if(len <= limit)
1367 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInMulticasts",                          p_device_mib->ifInMulticasts);
1368 +    if(len <= limit)
1369 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInPauseFrames",                         p_device_mib->ifInPauseFrames);
1370 +    if(len <= limit)
1371 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInCRCErrors",                           p_device_mib->ifInCRCErrors);
1372 +    if(len <= limit)
1373 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInAlignCodeErrors",                     p_device_mib->ifInAlignCodeErrors);
1374 +    if(len <= limit)
1375 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOversizedFrames",                     p_device_mib->ifInOversizedFrames);
1376 +    if(len <= limit)
1377 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInJabberFrames",                        p_device_mib->ifInJabberFrames);
1378 +    if(len <= limit)
1379 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInUndersizedFrames",                    p_device_mib->ifInUndersizedFrames);
1380 +    if(len <= limit)
1381 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFragments",                           p_device_mib->ifInFragments);
1382 +    if(len <= limit)
1383 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFilteredFrames",                      p_device_mib->ifInFilteredFrames);
1384 +    if(len <= limit)
1385 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInQosFilteredFrames",                   p_device_mib->ifInQosFilteredFrames);
1386 +    if(len <= limit)
1387 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOctets",                              p_device_mib->ifInOctets);
1388 +    if(len <= limit)
1389 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutGoodFrames",                         p_device_mib->ifOutGoodFrames);
1390 +    if(len <= limit)
1391 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutBroadcasts",                         p_device_mib->ifOutBroadcasts);
1392 +    if(len <= limit)
1393 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutMulticasts",                         p_device_mib->ifOutMulticasts);
1394 +    if(len <= limit)
1395 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutPauseFrames",                        p_device_mib->ifOutPauseFrames);
1396 +    if(len <= limit)
1397 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifDeferredTransmissions",                 p_device_mib->ifDeferredTransmissions);
1398 +    if(len <= limit)
1399 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifCollisionFrames",                       p_device_mib->ifCollisionFrames);
1400 +    if(len <= limit)
1401 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifSingleCollisionFrames",                 p_device_mib->ifSingleCollisionFrames);
1402 +    if(len <= limit)
1403 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifMultipleCollisionFrames",               p_device_mib->ifMultipleCollisionFrames);
1404 +    if(len <= limit)
1405 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifExcessiveCollisionFrames",              p_device_mib->ifExcessiveCollisionFrames);
1406 +    if(len <= limit)
1407 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifLateCollisions",                        p_device_mib->ifLateCollisions);
1408 +    if(len <= limit)
1409 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutUnderrun",                           p_device_mib->ifOutUnderrun);
1410 +    if(len <= limit)
1411 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifCarrierSenseErrors",                    p_device_mib->ifCarrierSenseErrors);
1412 +    if(len <= limit)
1413 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutOctets",                             p_device_mib->ifOutOctets);
1414 +    if(len <= limit)
1415 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if64OctetFrames",                         p_device_mib->if64OctetFrames);
1416 +    if(len <= limit)
1417 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if65To127POctetFrames",                   p_device_mib->if65To127OctetFrames);
1418 +    if(len <= limit)
1419 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if128To255OctetFrames",                   p_device_mib->if128To255OctetFrames);
1420 +    if(len <= limit)
1421 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if256To511OctetFrames",                   p_device_mib->if256To511OctetFrames);
1422 +    if(len <= limit)
1423 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if512To1023OctetFrames",                  p_device_mib->if512To1023OctetFrames);
1424 +    if(len <= limit)
1425 +        len+= sprintf(buf + len, "%-35s: %lu\n", "if1024ToUpOctetFrames",                   p_device_mib->if1024ToUPOctetFrames);
1426 +    if(len <= limit)
1427 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifNetOctets",                             p_device_mib->ifNetOctets);
1428 +    if(len <= limit)
1429 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxSofOverruns",                         p_device_mib->ifRxSofOverruns);
1430 +    if(len <= limit)
1431 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxMofOverruns",                         p_device_mib->ifRxMofOverruns);
1432 +    if(len <= limit)
1433 +        len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxDMAOverruns",                         p_device_mib->ifRxDMAOverruns);
1434 +
1435 +    *p_len = len;
1436 +
1437 +    return(0);
1438 +}
1439 +
1440 +
1441 +static int cpmac_p_read_rfc2665_stats(char* buf, char **start, off_t offset,
1442 +                              int count, int *eof, void *data)
1443 +{
1444 +    int limit = count - 80;
1445 +    int len   = 0;
1446 +    struct net_device *p_dev = (struct net_device*)data;
1447 +
1448 +    cpmac_p_update_statistics(p_dev, buf, limit, &len);
1449 +
1450 +    *eof = 1;
1451 +
1452 +    return len;
1453 +}
1454 +
1455 +static int cpmac_p_read_link(char *buf, char **start, off_t offset, int count,
1456 +                             int *eof, void *data)
1457 +{
1458 +    int len = 0;
1459 +
1460 +    struct net_device    *p_dev;
1461 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
1462 +    struct net_device    *cpmac_dev_list[cpmac_devices_installed];
1463 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal;
1464 +
1465 +    int                  i;
1466 +    int                  phy;            /* what phy are we using? */
1467 +
1468 +    len += sprintf(buf+len, "CPMAC devices = %d\n",cpmac_devices_installed);
1469 +
1470 +    p_dev        = last_cpmac_device;
1471 +
1472 +    /* Reverse the the device link list to list eth0,eth1...in correct order */
1473 +    for(i=0; i< cpmac_devices_installed; i++)
1474 +    {
1475 +        cpmac_dev_list[cpmac_devices_installed -(i+1)] = p_dev;
1476 +        p_cpmac_priv = p_dev->priv;
1477 +        p_dev = p_cpmac_priv->next_device;
1478 +    }
1479 +
1480 +    for(i=0; i< cpmac_devices_installed; i++)
1481 +    {
1482 +        p_dev        = cpmac_dev_list[i];
1483 +        p_cpmac_priv = p_dev->priv;
1484 +        p_drv_hal    = p_cpmac_priv->drv_hal;
1485 +
1486 +        /*  This prints them out from high to low because of how the devices are linked */
1487 +        if(netif_carrier_ok(p_dev))
1488 +        {
1489 +            p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "PhyNum", "Get", &phy);
1490 +
1491 +
1492 +            len += sprintf(buf+len,"eth%d: Link State: %s    Phy:0x%x, Speed = %s, Duplex = %s\n",
1493 +                           p_cpmac_priv->instance_num, "UP", phy,
1494 +                           (p_cpmac_priv->link_speed == 100000000) ? "100":"10",
1495 +                           (p_cpmac_priv->link_mode  == 2) ? "Half":"Full");
1496 +
1497 +        }
1498 +        else
1499 +            len += sprintf(buf+len,"eth%d: Link State: DOWN\n",p_cpmac_priv->instance_num);
1500 +
1501 +        p_dev = p_cpmac_priv->next_device;
1502 +    }
1503 +
1504 +    return len;
1505 +
1506 +}
1507 +
1508 +static int cpmac_p_read_stats(char* buf, char **start, off_t offset, int count,
1509 +                              int *eof, void *data)
1510 +{
1511 +    struct net_device *p_dev = last_cpmac_device;
1512 +    int                len   = 0;
1513 +    int                limit = count - 80;
1514 +    int i;
1515 +    struct net_device     *cpmac_dev_list[cpmac_devices_installed];
1516 +    CPMAC_PRIVATE_INFO_T  *p_cpmac_priv;
1517 +    CPMAC_DEVICE_MIB_T    *p_device_mib;
1518 +
1519 +    /* Reverse the the device link list to list eth0,eth1...in correct order */
1520 +    for(i=0; i< cpmac_devices_installed; i++)
1521 +    {
1522 +        cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
1523 +        p_cpmac_priv = p_dev->priv;
1524 +        p_dev = p_cpmac_priv->next_device;
1525 +    }
1526 +
1527 +    for(i=0; i< cpmac_devices_installed; i++)
1528 +    {
1529 +        p_dev = cpmac_dev_list[i];
1530 +
1531 +        if(!p_dev)
1532 +          goto proc_error;
1533 +
1534 +        /* Get Stats */
1535 +        cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
1536 +
1537 +        p_cpmac_priv = p_dev->priv;
1538 +        p_device_mib = p_cpmac_priv->device_mib;
1539 +
1540 +        /* Transmit stats */
1541 +        if(len<=limit)
1542 +          len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1, p_dev->base_addr);
1543 +        if(len<=limit)
1544 +          len+= sprintf(buf+len, " Transmit Stats\n");
1545 +        if(len<=limit)
1546 +          len+= sprintf(buf+len, "   Tx Valid Bytes Sent        :%lu\n",p_device_mib->ifOutOctets);
1547 +        if(len<=limit)
1548 +          len+= sprintf(buf+len, "   Good Tx Frames (Hardware)  :%lu\n",p_device_mib->ifOutGoodFrames);
1549 +        if(len<=limit)
1550 +          len+= sprintf(buf+len, "   Good Tx Frames (Software)  :%lu\n",p_cpmac_priv->net_dev_stats.tx_packets);
1551 +        if(len<=limit)
1552 +          len+= sprintf(buf+len, "   Good Tx Broadcast Frames   :%lu\n",p_device_mib->ifOutBroadcasts);
1553 +        if(len<=limit)
1554 +          len+= sprintf(buf+len, "   Good Tx Multicast Frames   :%lu\n",p_device_mib->ifOutMulticasts);
1555 +        if(len<=limit)
1556 +          len+= sprintf(buf+len, "   Pause Frames Sent          :%lu\n",p_device_mib->ifOutPauseFrames);
1557 +        if(len<=limit)
1558 +          len+= sprintf(buf+len, "   Collisions                 :%lu\n",p_device_mib->ifCollisionFrames);
1559 +        if(len<=limit)
1560 +          len+= sprintf(buf+len, "   Tx Error Frames            :%lu\n",p_cpmac_priv->net_dev_stats.tx_errors);
1561 +        if(len<=limit)
1562 +          len+= sprintf(buf+len, "   Carrier Sense Errors       :%lu\n",p_device_mib->ifCarrierSenseErrors);
1563 +        if(len<=limit)
1564 +          len+= sprintf(buf+len, "\n");
1565 +
1566 +
1567 +        /* Receive Stats */
1568 +        if(len<=limit)
1569 +          len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1,p_dev->base_addr);
1570 +        if(len<=limit)
1571 +          len+= sprintf(buf+len, " Receive Stats\n");
1572 +        if(len<=limit)
1573 +          len+= sprintf(buf+len, "   Rx Valid Bytes Received    :%lu\n",p_device_mib->ifInOctets);
1574 +        if(len<=limit)
1575 +          len+= sprintf(buf+len, "   Good Rx Frames (Hardware)  :%lu\n",p_device_mib->ifInGoodFrames);
1576 +        if(len<=limit)
1577 +          len+= sprintf(buf+len, "   Good Rx Frames (Software)  :%lu\n",p_cpmac_priv->net_dev_stats.rx_packets);
1578 +        if(len<=limit)
1579 +          len+= sprintf(buf+len, "   Good Rx Broadcast Frames   :%lu\n",p_device_mib->ifInBroadcasts);
1580 +        if(len<=limit)
1581 +          len+= sprintf(buf+len, "   Good Rx Multicast Frames   :%lu\n",p_device_mib->ifInMulticasts);
1582 +        if(len<=limit)
1583 +          len+= sprintf(buf+len, "   Pause Frames Received      :%lu\n",p_device_mib->ifInPauseFrames);
1584 +        if(len<=limit)
1585 +          len+= sprintf(buf+len, "   Rx CRC Errors              :%lu\n",p_device_mib->ifInCRCErrors);
1586 +        if(len<=limit)
1587 +          len+= sprintf(buf+len, "   Rx Align/Code Errors       :%lu\n",p_device_mib->ifInAlignCodeErrors);
1588 +        if(len<=limit)
1589 +          len+= sprintf(buf+len, "   Rx Jabbers                 :%lu\n",p_device_mib->ifInOversizedFrames);
1590 +        if(len<=limit)
1591 +          len+= sprintf(buf+len, "   Rx Filtered Frames         :%lu\n",p_device_mib->ifInFilteredFrames);
1592 +        if(len<=limit)
1593 +          len+= sprintf(buf+len, "   Rx Fragments               :%lu\n",p_device_mib->ifInFragments);
1594 +        if(len<=limit)
1595 +          len+= sprintf(buf+len, "   Rx Undersized Frames       :%lu\n",p_device_mib->ifInUndersizedFrames);
1596 +        if(len<=limit)
1597 +          len+= sprintf(buf+len, "   Rx Overruns                :%lu\n",p_device_mib->ifRxDMAOverruns);
1598 +    }
1599 +
1600 +
1601 +    return len;
1602 +
1603 + proc_error:
1604 +    *eof=1;
1605 +    return len;
1606 +}
1607 +
1608 +static int cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data)
1609 +{
1610 +       char local_buf[31];
1611 +        int  ret_val = 0;
1612 +
1613 +       if(count > 30)
1614 +       {
1615 +               printk("Error : Buffer Overflow\n");
1616 +               printk("Use \"echo 0 > cpmac_stat\" to reset the statistics\n");
1617 +               return -EFAULT;
1618 +       }
1619 +
1620 +       copy_from_user(local_buf,buf,count);
1621 +       local_buf[count-1]='\0'; /* Ignoring last \n char */
1622 +        ret_val = count;
1623 +
1624 +       if(strcmp("0",local_buf)==0)
1625 +       {
1626 +            struct net_device *p_dev = last_cpmac_device;
1627 +            int i;
1628 +            struct net_device     *cpmac_dev_list[cpmac_devices_installed];
1629 +            CPMAC_PRIVATE_INFO_T  *p_cpmac_priv;
1630 +
1631 +            /* Valid command */
1632 +           printk("Resetting statistics for CPMAC interface.\n");
1633 +
1634 +            /* Reverse the the device link list to list eth0,eth1...in correct order */
1635 +            for(i=0; i< cpmac_devices_installed; i++)
1636 +            {
1637 +                cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
1638 +                p_cpmac_priv = p_dev->priv;
1639 +                p_dev = p_cpmac_priv->next_device;
1640 +            }
1641 +
1642 +            for(i=0; i< cpmac_devices_installed; i++)
1643 +             {
1644 +                p_dev = cpmac_dev_list[i];
1645 +                if(!p_dev)
1646 +                {
1647 +                    ret_val = -EFAULT;
1648 +                    break;
1649 +                }
1650 +
1651 +                cpmac_p_reset_statistics(p_dev);
1652 +            }
1653 +       }
1654 +       else
1655 +       {
1656 +               printk("Error: Unknown operation on cpmac statistics\n");
1657 +               printk("Use \"echo 0 > cpmac_stats\" to reset the statistics\n");
1658 +               return -EFAULT;
1659 +       }
1660 +
1661 +       return ret_val;
1662 +}
1663 +
1664 +static int cpmac_p_reset_statistics(struct net_device *p_dev)
1665 +{
1666 +    int                       ret_val  = 0;
1667 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1668 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cpmac_priv->drv_hal;
1669 +
1670 +    memset(p_cpmac_priv->device_mib, 0, sizeof(CPMAC_DEVICE_MIB_T));
1671 +    memset(p_cpmac_priv->stats, 0, sizeof(CPMAC_DRV_STATS_T));
1672 +    memset(&p_cpmac_priv->net_dev_stats, 0, sizeof(struct net_device_stats));
1673 +
1674 +    p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
1675 +
1676 +    return(ret_val);
1677 +}
1678 +
1679 +static int cpmac_p_get_version(char* buf, char **start, off_t offset, int count,int *eof, void *data)
1680 +{
1681 +    int  len                           = 0;
1682 +    int  limit                         = count - 80;
1683 +    char *hal_version                  = NULL;
1684 +    struct net_device *p_dev           = last_cpmac_device;
1685 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1686 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cpmac_priv->drv_hal;
1687 +
1688 +    p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Version", "Get", &hal_version);
1689 +
1690 +    len += sprintf(buf+len, "Texas Instruments CPMAC driver version: %s\n", cpmac_version);
1691 +
1692 +    if(len <= limit && hal_version)
1693 +        len += sprintf(buf+len, "Texas Instruments CPMAC HAL version: %s\n", hal_version);
1694 +
1695 +    return len;
1696 +}
1697 +
1698 +static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *p_dev)
1699 +{
1700 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
1701 +
1702 +    cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
1703 +
1704 +    return &p_cpmac_priv->net_dev_stats;
1705 +}
1706 +
1707 +static int cpmac_p_detect_manual_cfg(int link_speed, char* link_mode, int debug)
1708 +{
1709 +    char *pSpeed = NULL;
1710 +
1711 +    if(debug == 1)
1712 +    {
1713 +        cpmac_debug_mode = 1;
1714 +        dbgPrint("Enabled the debug print.\n");
1715 +    }
1716 +
1717 +    if(!link_speed && !link_mode)
1718 +    {
1719 +        dbgPrint("No manual link params, defaulting to auto negotiation.\n");
1720 +        return (0);
1721 +    }
1722 +
1723 +    if(!link_speed || (link_speed != 10 && link_speed != 100))
1724 +    {
1725 +        dbgPrint("Invalid or No value of link speed specified, defaulting to auto speed.\n");
1726 +        pSpeed = "auto";
1727 +    }
1728 +    else if(link_speed == 10)
1729 +    {
1730 +        g_cfg_start_link_params &= ~(_CPMDIO_100);
1731 +        pSpeed = "10 Mbps";
1732 +    }
1733 +    else
1734 +    {
1735 +       g_cfg_start_link_params &= ~(_CPMDIO_10);
1736 +        pSpeed = "100 Mbps";
1737 +    }
1738 +
1739 +    if(!link_mode || (!strcmp(link_mode, "fd") && !strcmp(link_mode, "hd")))
1740 +    {
1741 +        dbgPrint("Invalid or No value of link mode specified, defaulting to auto mode.\n");
1742 +    }
1743 +    else if(!strcmp(link_mode, "hd"))
1744 +    {
1745 +        g_cfg_start_link_params &= ~(_CPMDIO_FD);
1746 +    }
1747 +    else
1748 +    {
1749 +        g_cfg_start_link_params &= ~(_CPMDIO_HD);
1750 +    }
1751 +
1752 +    dbgPrint("Link is manually set to the speed of %s speed and %s mode.\n",
1753 +              pSpeed, link_mode ? link_mode : "auto");
1754 +
1755 +    return(0);
1756 +}
1757 +
1758 +//------------------------------------------------------------------------------
1759 +// Call back from the HAL.
1760 +//------------------------------------------------------------------------------
1761 +static int cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1762 +{
1763 +    struct net_device    *p_dev        = p_cpmac_priv->owner;
1764 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cpmac_priv->drv_hal;
1765 +    int status;
1766 +
1767 +    p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Status", "Get", &status);
1768 +
1769 +    /* We do not reflect the real link status if in loopback.
1770 +     * After all, we want the packets to reach the hardware so
1771 +     * that Send() should work. */
1772 +    if(p_dev->flags & IFF_LOOPBACK)
1773 +    {
1774 +        dbgPrint("Maintaining the link up loopback for %s.\n", p_dev->name);
1775 +       netif_carrier_on(p_dev);
1776 +
1777 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
1778 +//        avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
1779 +//#endif
1780 +
1781 +        return(0);
1782 +    }
1783 +
1784 +    if(status & CPMAC_STATUS_ADAPTER_CHECK) /* ???? */
1785 +    {
1786 +        ; /* what to do ? */
1787 +    }
1788 +    else if(status)
1789 +    {
1790 +        if(!netif_carrier_ok(p_dev))
1791 +       {
1792 +            netif_carrier_on(p_cpmac_priv->owner);
1793 +
1794 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
1795 +//            avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
1796 +//#endif
1797 +           dbgPrint("Found the Link for the CPMAC instance %s.\n", p_dev->name);
1798 +        }
1799 +
1800 +        if(netif_running(p_dev) & netif_queue_stopped(p_dev))
1801 +        {
1802 +            netif_wake_queue(p_dev);
1803 +        }
1804 +
1805 +       p_cpmac_priv->link_speed = status & CPMAC_STATUS_LINK_SPEED ? 100000000:10000000;
1806 +       p_cpmac_priv->link_mode  = status & CPMAC_STATUS_LINK_DUPLEX? 3:2;
1807 +
1808 +    }
1809 +    else
1810 +    {
1811 +        if(netif_carrier_ok(p_dev))
1812 +       {
1813 +           /* do we need to register synchronization issues with stats here. */
1814 +           p_cpmac_priv->link_speed        = 100000000;
1815 +           p_cpmac_priv->link_mode         = 1;
1816 +
1817 +           netif_carrier_off(p_dev);
1818 +
1819 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
1820 +//            avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
1821 +//#endif
1822 +
1823 +           dbgPrint("Lost the Link for the CPMAC for %s.\n", p_dev->name);
1824 +       }
1825 +
1826 +        if(!netif_queue_stopped(p_dev))
1827 +        {
1828 +            netif_stop_queue(p_dev);     /* So that kernel does not keep on xmiting pkts. */
1829 +        }
1830 +    }
1831 +
1832 +    return(0);
1833 +}
1834 +
1835 +//-----------------------------------------------------------------------------
1836 +// Timer related private functions.
1837 +//-----------------------------------------------------------------------------
1838 +static int cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1839 +{
1840 +    struct timer_list *p_timer = p_cpmac_priv->timer;
1841 +
1842 +    init_timer(p_timer);
1843 +
1844 +    p_timer                    = p_cpmac_priv->timer + TICK_TIMER;
1845 +    p_timer->expires           = 0;
1846 +    p_timer->data              = (unsigned long)p_cpmac_priv;
1847 +    p_timer->function          = cpmac_p_tick_timer_expiry;
1848 +
1849 +    return(0);
1850 +}
1851 +
1852 +#if 0
1853 +static int cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1854 +{
1855 +    struct timer_list *p_timer;
1856 +
1857 +    p_timer = p_cpmac_priv->timer + TICK_TIMER;
1858 +
1859 +    /* use spin lock to establish synchronization with the dispatch */
1860 +    if(p_timer->function) del_timer_sync(p_timer);
1861 +    p_timer->function = NULL;
1862 +
1863 +    return (0);
1864 +}
1865 +#endif
1866 +
1867 +static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks)
1868 +{
1869 +    p_timer->expires        = jiffies + delay_ticks;
1870 +
1871 +    if(p_timer->function)
1872 +    {
1873 +        add_timer(p_timer);
1874 +    }
1875 +
1876 +    return(0);
1877 +}
1878 +
1879 +static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param)
1880 +{
1881 +    CPMAC_PRIVATE_INFO_T   *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T*) p_cb_param;
1882 +    CPMAC_DRV_HAL_INFO_T   *p_drv_hal    = p_cpmac_priv->drv_hal;
1883 +    struct timer_list       *p_timer     = p_cpmac_priv->timer + TICK_TIMER;
1884 +
1885 +    if(test_bit(0, &p_cpmac_priv->set_to_close))
1886 +    {
1887 +        return;
1888 +    }
1889 +
1890 +    p_drv_hal->hal_funcs->Tick(p_drv_hal->hal_dev);
1891 +
1892 +    cpmac_p_start_timer(p_timer, p_cpmac_priv->delay_ticks);
1893 +}
1894 +
1895 +static int cpmac_p_stop_timer(struct timer_list *p_timer)
1896 +{
1897 +    /* Ideally we need to a set flag indicating not to start the timer again
1898 +       before del_timer_sync() is called up. But here we assume that the
1899 +       caller has set the p_cpmac_priv->set_to_close (ok for now). */
1900 +    del_timer_sync(p_timer);
1901 +
1902 +    return(0);
1903 +}
1904 +
1905 +//------------------------------------------------------------------------------
1906 +// Device configuration and setup related private functions.
1907 +//------------------------------------------------------------------------------
1908 +static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv,
1909 +                                         unsigned long *p_dev_flags)
1910 +{
1911 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal   = p_cpmac_priv->drv_hal;
1912 +    HAL_FUNCTIONS        *p_hal_funcs = p_drv_hal->hal_funcs;
1913 +    HAL_DEVICE           *p_hal_dev   = p_drv_hal->hal_dev;
1914 +    CPMAC_ABILITY_INFO_T *p_capability= p_cpmac_priv->ability_info;
1915 +    unsigned int         val          = 0;
1916 +    int                  channel      = 0;
1917 +
1918 +    p_cpmac_priv->flags                  = 0;
1919 +
1920 +    p_capability->promiscous             = CFG_PROMISCOUS;
1921 +    p_capability->broadcast              = CFG_BROADCAST;
1922 +    p_capability->multicast              = CFG_MULTICAST;
1923 +    p_capability->all_multi              = CFG_ALL_MULTI;
1924 +    p_capability->jumbo_frames           = CFG_JUMBO_FRAMES;
1925 +    p_capability->short_frames           = CFG_SHORT_FRAMES;
1926 +    p_capability->auto_negotiation       = CFG_AUTO_NEGOTIATION;
1927 +    p_capability->link_speed             = cfg_start_link_speed;
1928 +    p_capability->loop_back              = CFG_LOOP_BACK;
1929 +    p_capability->tx_flow_control        = CFG_TX_FLOW_CNTL;
1930 +    p_capability->rx_flow_control        = CFG_RX_FLOW_CNTL;
1931 +    p_capability->tx_pacing              = CFG_TX_PACING;
1932 +    p_capability->rx_pass_crc            = CFG_RX_PASS_CRC;
1933 +    p_capability->qos_802_1q             = CFG_QOS_802_1Q;
1934 +    p_capability->tx_num_chan            = CFG_TX_NUM_CHAN;
1935 +
1936 +    /* Lets probe the device for the configured capabilities (netdev specific).*/
1937 +
1938 +    /* Following are set in the set_multi_list, when indicated by the kernel
1939 +     * Promiscous and all multi.
1940 +     */
1941 +
1942 +    if(p_capability->broadcast)
1943 +    {
1944 +        channel = 0;
1945 +       val     = 1;
1946 +        if((p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_EN, pszSet, &val) == 0) &&
1947 +           (p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_CH, pszSet, &channel) == 0))
1948 +           *p_dev_flags |= IFF_BROADCAST;
1949 +       else
1950 +           p_capability->broadcast = 0; /* no broadcast capabilities */
1951 +    }
1952 +
1953 +    if(p_capability->multicast)
1954 +    {
1955 +        val     = 1;
1956 +       channel = 0;
1957 +       if((p_hal_funcs->Control(p_hal_dev, pszRX_MULT_EN, pszSet, &val) == 0) &&
1958 +          (p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel) == 0))
1959 +           *p_dev_flags |= IFF_MULTICAST;
1960 +       else
1961 +       {
1962 +           p_capability->multicast = 0;
1963 +           p_capability->all_multi = 0; /* no multicast, no all-multi. */
1964 +       }
1965 +    }
1966 +
1967 +    if(p_capability->loop_back)
1968 +    {
1969 +        ;  /* We do not put the device in loopback, if required use ioctl */
1970 +    }
1971 +
1972 +    /* Lets probe the device for the configured capabilities (Non net device specific).*/
1973 +
1974 +    if(p_capability->jumbo_frames)
1975 +    {
1976 +       val = 0;
1977 +        if(p_hal_funcs->Control(p_hal_dev, pszRX_NO_CHAIN, pszSet, &val) == 0)
1978 +            p_cpmac_priv->flags |= IFF_PRIV_JUMBO_FRAMES;
1979 +       else
1980 +           p_capability->jumbo_frames = 0;
1981 +    }
1982 +
1983 +    if(p_capability->short_frames)
1984 +    {
1985 +       val = 1;
1986 +        if(p_hal_funcs->Control(p_hal_dev, pszRX_CSF_EN, pszSet, &val) == 0)
1987 +            p_cpmac_priv->flags |= IFF_PRIV_SHORT_FRAMES;
1988 +       else
1989 +           p_capability->short_frames = 0;
1990 +    }
1991 +
1992 +    val = g_cfg_start_link_params;
1993 +
1994 +#ifdef CONFIG_AR7_MDIX
1995 +    if( avalanche_is_mdix_on_chip() )
1996 +    {
1997 +        val |= _CPMDIO_AUTOMDIX;
1998 +    }
1999 +#endif
2000 +
2001 +    if(p_hal_funcs->Control(p_hal_dev,pszMdioConnect,pszSet, &val) !=0)
2002 +    {
2003 +        p_capability->link_speed = 0;
2004 +    }
2005 +    else
2006 +    {
2007 +       if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD | _CPMDIO_10))
2008 +            p_cpmac_priv->flags |= IFF_PRIV_AUTOSPEED;
2009 +       else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD))
2010 +           p_cpmac_priv->flags |= IFF_PRIV_LINK100_HD;
2011 +       else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_FD))
2012 +           p_cpmac_priv->flags |= IFF_PRIV_LINK100_FD;
2013 +       else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_HD))
2014 +           p_cpmac_priv->flags |= IFF_PRIV_LINK10_HD;
2015 +       else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_FD))
2016 +           p_cpmac_priv->flags |= IFF_PRIV_LINK10_FD;
2017 +       else
2018 +           ;
2019 +    }
2020 +
2021 +    if(p_capability->tx_flow_control)
2022 +    {
2023 +       val = 1;
2024 +        if(p_hal_funcs->Control(p_hal_dev,pszTX_FLOW_EN, pszSet, &val) ==0)
2025 +            p_cpmac_priv->flags |= IFF_PRIV_TX_FLOW_CNTL;
2026 +       else
2027 +            p_capability->tx_flow_control = 0;
2028 +    }
2029 +
2030 +    if(p_capability->rx_flow_control)
2031 +    {
2032 +       val = 1;
2033 +        if(p_hal_funcs->Control(p_hal_dev, pszRX_FLOW_EN, pszSet, &val) ==0)
2034 +           p_cpmac_priv->flags |= IFF_PRIV_RX_FLOW_CNTL;
2035 +       else
2036 +            p_capability->rx_flow_control = 0;
2037 +    }
2038 +
2039 +    if(p_capability->tx_pacing)
2040 +    {
2041 +       val = 1;
2042 +        if(p_hal_funcs->Control(p_hal_dev, pszTX_PACE, pszSet, &val) ==0)
2043 +            p_cpmac_priv->flags |= IFF_PRIV_TX_PACING;
2044 +       else
2045 +           p_capability->tx_pacing = 0;
2046 +    }
2047 +
2048 +    if(p_capability->rx_pass_crc)
2049 +    {
2050 +       val = 1;
2051 +       if(p_hal_funcs->Control(p_hal_dev, pszRX_PASS_CRC, pszSet, &val) == 0)
2052 +           p_cpmac_priv->flags |= IFF_PRIV_RX_PASS_CRC;
2053 +       else
2054 +            p_capability->rx_pass_crc = 0;
2055 +    }
2056 +
2057 +    if(p_capability->qos_802_1q)
2058 +    {
2059 +       val  = 1;
2060 +        if(p_hal_funcs->Control(p_hal_dev, pszRX_QOS_EN, pszSet, &val) == 0)
2061 +            p_cpmac_priv->flags |= IFF_PRIV_8021Q_EN;
2062 +       else
2063 +       {
2064 +           p_capability->qos_802_1q = 0;
2065 +           p_capability->tx_num_chan= 1;
2066 +        }
2067 +    }
2068 +
2069 +    if(p_capability->tx_num_chan > 1)
2070 +    {
2071 +       int cfg_tx_num_chan = p_capability->tx_num_chan;
2072 +        val = 0;
2073 +#ifdef TEST
2074 +       if(p_hal_funcs->Control(p_hal_dev, pszTX_NUM_CH, pszGet, &val) == 0)
2075 +           cfg_tx_num_chan = cfg_tx_num_chan > val ? val : cfg_tx_num_chan;
2076 +       else
2077 +           cfg_tx_num_chan = 1;
2078 +#endif
2079 +       p_capability->tx_num_chan = cfg_tx_num_chan;
2080 +    }
2081 +
2082 +    return(0);
2083 +}
2084 +
2085 +static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
2086 +{
2087 +   int i=0;
2088 +   int threshold = CFG_TX_NUM_BUF_SERVICE;
2089 +
2090 +   char *tx_threshold_ptr = prom_getenv("threshold");
2091 +
2092 +    CPMAC_TX_CHAN_INFO_T *p_tx_chan_info = p_cpmac_priv->tx_chan_info;
2093 +    CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
2094 +    CPMAC_ABILITY_INFO_T *p_capability   = p_cpmac_priv->ability_info;
2095 +
2096 +    /* Timer stuff */
2097 +    p_cpmac_priv->timer_count      = 1; /* should be < or = the MAX TIMER */
2098 +    p_cpmac_priv->timer_created    = 0;
2099 +    p_cpmac_priv->timer_access_hal = 1;
2100 +
2101 +    for(i=0; i < MAX_TIMER; i++)
2102 +        p_cpmac_priv->timer[i].function = NULL;
2103 +
2104 +    p_cpmac_priv->enable_802_1q  = p_capability->qos_802_1q;
2105 +
2106 +    /* Tx channel related.*/
2107 +    p_tx_chan_info->cfg_chan     = p_capability->tx_num_chan;
2108 +    p_tx_chan_info->opened_chan  = 0;
2109 +
2110 +    if(tx_threshold_ptr)
2111 +       threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
2112 +
2113 +    if((threshold <= 0) && tx_threshold_ptr) /* If threshold set to 0 then Enable the TX interrupt */
2114 +    {
2115 +       threshold  = CFG_TX_NUM_BUF_SERVICE;
2116 +       p_tx_chan_info->tx_int_disable = 0;
2117 +
2118 +    }
2119 +    else
2120 +    {
2121 +       p_tx_chan_info->tx_int_disable = CFG_TX_INT_DISABLE;
2122 +    }
2123 +
2124 +    for(i=0; i < MAX_TX_CHAN; i++)
2125 +    {
2126 +
2127 +
2128 +
2129 +       p_tx_chan_info->chan[i].state         = CHAN_CLOSE;
2130 +       p_tx_chan_info->chan[i].num_BD        = CFG_TX_NUM_BUF_DESC;
2131 +       p_tx_chan_info->chan[i].buffer_size   = cpmac_max_frame_size;
2132 +       p_tx_chan_info->chan[i].buffer_offset = CFG_TX_BUF_OFFSET;
2133 +
2134 +
2135 +
2136 +       p_tx_chan_info->chan[i].service_max   = threshold;
2137 +    }
2138 +
2139 +    if (p_tx_chan_info->tx_int_disable)
2140 +       printk("Cpmac driver Disable TX complete interrupt setting threshold to %d.\n",threshold);
2141 +    else
2142 +       printk("Cpmac driver Enable TX complete interrupt\n");
2143 +
2144 +
2145 +    /* Assuming just one rx channel for now */
2146 +    p_rx_chan_info->cfg_chan            = 1;
2147 +    p_rx_chan_info->opened_chan         = 0;
2148 +    p_rx_chan_info->chan->state         = CHAN_CLOSE;
2149 +    p_rx_chan_info->chan->num_BD        = CFG_RX_NUM_BUF_DESC;
2150 +    p_rx_chan_info->chan->buffer_size   = cpmac_max_frame_size;
2151 +    p_rx_chan_info->chan->buffer_offset = CFG_RX_BUF_OFFSET;
2152 +    p_rx_chan_info->chan->service_max   = CFG_RX_NUM_BUF_SERVICE;
2153 +
2154 +    /* Set as per RFC 2665 */
2155 +    p_cpmac_priv->link_speed     = 100000000;
2156 +    p_cpmac_priv->link_mode      = 1;
2157 +
2158 +    p_cpmac_priv->loop_back      = 0;
2159 +
2160 +    return(0);
2161 +}
2162 +
2163 +inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan)
2164 +{
2165 +    /* Number of ethernet packets & max pkt length */
2166 +    p_rx_chan->chan->tot_buf_size  = p_rx_chan->chan->buffer_size   +
2167 +                                     2*(CONTROL_802_1Q_SIZE)        +
2168 +                                    p_rx_chan->chan->buffer_offset +
2169 +                                     ADD_FOR_4BYTE_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
2170 +
2171 +    p_rx_chan->chan->tot_reserve_bytes = CONTROL_802_1Q_SIZE +
2172 +                                         p_rx_chan->chan->buffer_offset +
2173 +                                        L3_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
2174 +
2175 +    return(0);
2176 +}
2177 +
2178 +//-----------------------------------------------------------------------------
2179 +// Net device related private functions.
2180 +//-----------------------------------------------------------------------------
2181 +
2182 +/***************************************************************
2183 + *     cpmac_dev_init
2184 + *
2185 + *     Returns:
2186 + *             0 on success, error code otherwise.
2187 + *     Parms:
2188 + *             dev     The structure of the device to be
2189 + *                     init'ed.
2190 + *
2191 + *     This function completes the initialization of the
2192 + *     device structure and driver.  It reserves the IO
2193 + *     addresses and assignes the device's methods.
2194 + *
2195 + *
2196 + **************************************************************/
2197 +
2198 +static int cpmac_dev_init(struct net_device *p_dev)
2199 +{
2200 +    int retVal = -1;
2201 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2202 +    int instance_num                   = p_cpmac_priv->instance_num;
2203 +    unsigned long net_flags = 0;
2204 +    char *mac_name          = NULL;
2205 +    char *mac_string        = NULL;
2206 +
2207 +    CPMAC_TX_CHAN_INFO_T *p_tx_chan_info;
2208 +    CPMAC_RX_CHAN_INFO_T *p_rx_chan_info;
2209 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal;
2210 +    int i;
2211 +
2212 +    int mem_size =    sizeof(CPMAC_DRV_HAL_INFO_T)
2213 +                   + sizeof(CPMAC_TX_CHAN_INFO_T)
2214 +                   + sizeof(CPMAC_RX_CHAN_INFO_T)
2215 +                   + sizeof(CPMAC_ABILITY_INFO_T)
2216 +                    + sizeof(CPMAC_DEVICE_MIB_T)
2217 +                    + sizeof(CPMAC_DRV_STATS_T);
2218 +
2219 +
2220 +#if defined(CONFIG_MIPS_SEAD2)
2221 +    int prev_reset_val = RESET_REG_PRCR;
2222 +    /* Bring the module out of reset */
2223 +    RESET_REG_PRCR |= temp_reset_value[p_cpmac_priv->instance_num];
2224 +
2225 +    /* Read the version id of the device to check if the device really exists */
2226 +    if( VERSION(temp_base_address[p_cpmac_priv->instance_num]) == 0)
2227 +    {
2228 +        printk(" CPMAC:Device not found\n");
2229 +       RESET_REG_PRCR = prev_reset_val;
2230 +        return -ENODEV;
2231 +    }
2232 +
2233 +    RESET_REG_PRCR = prev_reset_val;
2234 +#endif
2235 +
2236 +
2237 +    if((p_drv_hal = kmalloc(mem_size,  GFP_KERNEL)) == NULL)
2238 +    {
2239 +        errPrint("Failed to allocate memory; rewinding.\n");
2240 +        return(-1);
2241 +    }
2242 +
2243 +    memset(p_drv_hal, 0, mem_size);
2244 +
2245 +    /* build the cpmac private object */
2246 +    p_cpmac_priv->drv_hal       = p_drv_hal;
2247 +    p_cpmac_priv->tx_chan_info  = p_tx_chan_info
2248 +                                = (CPMAC_TX_CHAN_INFO_T*)((char*)p_drv_hal
2249 +                                 + sizeof(CPMAC_DRV_HAL_INFO_T));
2250 +    p_cpmac_priv->rx_chan_info  = p_rx_chan_info
2251 +                                = (CPMAC_RX_CHAN_INFO_T*)((char *)p_tx_chan_info
2252 +                                 + sizeof(CPMAC_TX_CHAN_INFO_T));
2253 +    p_cpmac_priv->ability_info  = (CPMAC_ABILITY_INFO_T *)((char *)p_rx_chan_info
2254 +                                 + sizeof(CPMAC_RX_CHAN_INFO_T));
2255 +    p_cpmac_priv->device_mib    = (CPMAC_DEVICE_MIB_T *)((char *)p_cpmac_priv->ability_info
2256 +                                 + sizeof(CPMAC_ABILITY_INFO_T));
2257 +    p_cpmac_priv->stats         = (CPMAC_DRV_STATS_T *)((char *)p_cpmac_priv->device_mib
2258 +                                 + sizeof(CPMAC_DEVICE_MIB_T));
2259 +
2260 +    p_drv_hal->owner            = p_cpmac_priv;
2261 +
2262 +
2263 +    switch(instance_num)
2264 +    {
2265 +
2266 +        case 0:
2267 +            mac_name="maca";
2268 +
2269 +            /* Also setting port information */
2270 +            p_dev->if_port =  AVALANCHE_CPMAC_LOW_PORT_ID;
2271 +
2272 +            break;
2273 +
2274 +        case 1:
2275 +            mac_name="macb";
2276 +
2277 +            /* Also setting port information */
2278 +            p_dev->if_port =  AVALANCHE_CPMAC_HIGH_PORT_ID;
2279 +
2280 +            break;
2281 +    }
2282 +
2283 +    if(mac_name)
2284 +        mac_string=prom_getenv(mac_name);
2285 +
2286 +    if(!mac_string)
2287 +    {
2288 +        mac_string="08.00.28.32.06.02";
2289 +        printk("Error getting mac from Boot enviroment for %s\n",p_dev->name);
2290 +        printk("Using default mac address: %s\n",mac_string);
2291 +        if(mac_name)
2292 +        {
2293 +            printk("Use Bootloader command:\n");
2294 +            printk("    setenv %s xx.xx.xx.xx.xx.xx\n","<env_name>");
2295 +            printk("to set mac address\n");
2296 +        }
2297 +    }
2298 +
2299 +    str2eaddr(p_cpmac_priv->mac_addr,mac_string);
2300 +
2301 +    for (i=0; i <= ETH_ALEN; i++)
2302 +    {
2303 +        /* This sets the hardware address */
2304 +       p_dev->dev_addr[i] = p_cpmac_priv->mac_addr[i];
2305 +    }
2306 +
2307 +    p_cpmac_priv->set_to_close          = 1;
2308 +    p_cpmac_priv->non_data_irq_expected = 0;
2309 +
2310 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
2311 +//    if((p_cpmac_priv->led_handle = avalanche_led_register("cpmac", instance_num)) == NULL)
2312 +//   {
2313 +//        errPrint("Could not allocate handle for CPMAC[%d] LED.\n", instance_num);
2314 +//       goto cpmac_init_mod_error;
2315 +//    }
2316 +//#endif
2317 +
2318 +    if(cpmac_drv_init_module(p_drv_hal, p_dev, instance_num) != 0)
2319 +    {
2320 +        errPrint("Could not initialize the HAL for %s.\n", p_dev->name);
2321 +        goto cpmac_init_mod_error;
2322 +    }
2323 +
2324 +    /* initialize the CPMAC device */
2325 +    if (cpmac_drv_init(p_drv_hal) == -1)
2326 +    {
2327 +       errPrint("HAL init failed for %s.\n", p_dev->name);
2328 +       goto cpmac_init_device_error;
2329 +    }
2330 +
2331 +    if(cpmac_p_probe_and_setup_device(p_cpmac_priv, &net_flags) == -1)
2332 +    {
2333 +        errPrint("Failed to configure up %s.\n", p_dev->name);
2334 +        goto cpmac_init_device_error;
2335 +    }
2336 +
2337 +    if(cpmac_p_setup_driver_params(p_cpmac_priv) == -1)
2338 +    {
2339 +        errPrint("Failed to set driver parameters for %s.\n", p_dev->name);
2340 +        goto cpmac_init_device_error;
2341 +    }
2342 +
2343 +    cpmac_p_rx_buf_setup(p_rx_chan_info);
2344 +
2345 +    /* initialize the timers for the net device */
2346 +    if(cpmac_p_timer_init(p_cpmac_priv) == -1)
2347 +    {
2348 +        errPrint("Failed to set timer(s) for %s.\n", p_dev->name);
2349 +        goto cpmac_timer_init_error;
2350 +    }
2351 +
2352 +    p_dev->addr_len           = 6;
2353 +
2354 +    p_dev->open               = &cpmac_dev_open;    /*  i.e. Start Device  */
2355 +    p_dev->hard_start_xmit    = &cpmac_dev_tx;
2356 +    p_dev->stop               = &cpmac_dev_close;
2357 +    p_dev->get_stats          = &cpmac_dev_get_net_stats;
2358 +
2359 +    p_dev->set_multicast_list = &cpmac_dev_mcast_set;
2360 +    p_dev->set_mac_address    = cpmac_dev_set_mac_addr;
2361 +    /* Knocking off the default broadcast and multicast flags. Allowing the
2362 +       device configuration to control the flags. */
2363 +    p_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST);
2364 +    p_dev->flags |= net_flags;
2365 +
2366 +    netif_carrier_off(p_dev);
2367 +
2368 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
2369 +//    avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
2370 +//#endif
2371 +
2372 +    /* Tasklet is initialized at the isr registeration time. */
2373 +    p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacBase", "Get", &p_dev->base_addr);
2374 +    p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacSize", "Get", &p_cpmac_priv->dev_size);
2375 +
2376 +    request_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size, p_dev->name);
2377 +
2378 +    retVal = 0;
2379 +
2380 +    if(g_init_enable_flag)
2381 +        cpmac_p_dev_enable(p_dev);
2382 +
2383 +    return(retVal);
2384 +
2385 +cpmac_timer_init_error:
2386 +cpmac_init_device_error  :
2387 +    cpmac_drv_cleanup(p_drv_hal);
2388 +
2389 +cpmac_init_mod_error:
2390 +    kfree(p_drv_hal);
2391 +
2392 +    return (retVal);
2393 +
2394 +} /* cpmac_dev_init */
2395 +
2396 +
2397 +/***************************************************************
2398 + *     cpmac_p_dev_enable
2399 + *
2400 + *     Returns:
2401 + *             0 on success, error code otherwise.
2402 + *     Parms:
2403 + *             dev     Structure of device to be opened.
2404 + *
2405 + *     This routine puts the driver and CPMAC adapter in a
2406 + *     state where it is ready to send and receive packets.
2407 + *
2408 + *
2409 + **************************************************************/
2410 +int cpmac_p_dev_enable( struct net_device *p_dev)
2411 +{
2412 +    int ret_val = 0;
2413 +    int channel = 0;
2414 +
2415 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_dev->priv;
2416 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal      = p_cpmac_priv->drv_hal;
2417 +    CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
2418 +    int max_length                       = p_rx_chan_info->chan->tot_buf_size;
2419 +
2420 +    p_cpmac_priv->set_to_close = 0;
2421 +
2422 +    if((ret_val = cpmac_drv_start(p_drv_hal, p_cpmac_priv->tx_chan_info,
2423 +                                 p_cpmac_priv->rx_chan_info, CHAN_SETUP))==-1)
2424 +    {
2425 +        errPrint("%s error: failed to start the device.\n", p_dev->name);
2426 +        ret_val = -1;
2427 +    }
2428 +    else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev,"RX_UNICAST_SET",
2429 +                                         "Set", &channel)!=0)
2430 +    {
2431 +        errPrint("%s error: device chan 0 could not be enabled.\n", p_dev->name);
2432 +       ret_val = -1;
2433 +    }
2434 +    else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, pszRX_MAXLEN, pszSet, &max_length) != 0)
2435 +    {
2436 +        errPrint(" CPMAC registers can't be written \n");
2437 +        ret_val = -1;
2438 +    }
2439 +    else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "TxIntDisable", "Set",
2440 +            &p_cpmac_priv->tx_chan_info->tx_int_disable) != 0)
2441 +    {
2442 +        errPrint(" CPMAC registers can't be written \n");
2443 +        ret_val = -1;
2444 +    }
2445 +    else
2446 +    {
2447 +        ; // Every thing went OK.
2448 +    }
2449 +
2450 +    return(ret_val);
2451 +} /* cpmac_dev_enable */
2452 +
2453 +
2454 +static int cpmac_dev_open(struct net_device *p_dev)
2455 +{
2456 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_dev->priv;
2457 +    CPMAC_ISR_INFO_T     *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
2458 +
2459 +    if(!g_init_enable_flag)
2460 +        cpmac_p_dev_enable(p_dev);
2461 +
2462 +    if(request_irq(p_isr_cb_param->intr, cpmac_hal_isr, SA_INTERRUPT,
2463 +                   "Cpmac Driver", p_isr_cb_param))
2464 +    {
2465 +        errPrint("Failed to register the irq %d for Cpmac %s.\n",
2466 +                  p_isr_cb_param->intr, p_dev->name);
2467 +        return (-1);
2468 +    }
2469 +
2470 +    netif_start_queue(p_dev);
2471 +
2472 +    MOD_INC_USE_COUNT;
2473 +    p_cpmac_priv->stats->start_tick = jiffies;
2474 +    dbgPrint("Started the network queue for %s.\n", p_dev->name);
2475 +    return(0);
2476 +}
2477 +
2478 +/***************************************************************
2479 + *     cpmac_p_dev_disable
2480 + *
2481 + *     Returns:
2482 + *             An error code.
2483 + *     Parms:
2484 + *             dev     The device structure of the device to
2485 + *                     close.
2486 + *
2487 + *     This function shuts down the adapter.
2488 + *
2489 + **************************************************************/
2490 +int cpmac_p_dev_disable(struct net_device *p_dev)
2491 +{
2492 +    int ret_val = 0;
2493 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2494 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cpmac_priv->drv_hal;
2495 +
2496 +    set_bit(0, &p_cpmac_priv->set_to_close);
2497 +    set_bit(0, &p_cpmac_priv->non_data_irq_expected);
2498 +
2499 +    /* The driver does not re-schedule the tasklet after kill is called. So, this
2500 +       should take care of the bug in the kernel. */
2501 +    tasklet_kill(&p_cpmac_priv->cpmac_isr.tasklet);
2502 +
2503 +    if(cpmac_drv_stop(p_drv_hal, p_cpmac_priv->tx_chan_info,
2504 +                     p_cpmac_priv->rx_chan_info,
2505 +                     CHAN_TEARDOWN | FREE_BUFFER | BLOCKING | COMPLETE) == -1)
2506 +    {
2507 +        ret_val = -1;
2508 +    }
2509 +    else
2510 +    {
2511 +        /* hope that the HAL closes down the tick timer.*/
2512 +
2513 +        dbgPrint("Device %s Closed.\n", p_dev->name);
2514 +        p_cpmac_priv->stats->start_tick = jiffies;
2515 +
2516 +        p_cpmac_priv->link_speed        = 100000000;
2517 +        p_cpmac_priv->link_mode         = 1;
2518 +        netif_carrier_off(p_dev);
2519 +
2520 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
2521 +//        avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
2522 +//#endif
2523 +
2524 +        clear_bit(0, &p_cpmac_priv->non_data_irq_expected);
2525 +
2526 +    }
2527 +
2528 +    return (ret_val);
2529 +
2530 +} /* cpmac_dev_close */
2531 +
2532 +
2533 +/***************************************************************
2534 + *     cpmac_dev_close
2535 + *
2536 + *     Returns:
2537 + *             An error code.
2538 + *     Parms:
2539 + *             dev     The device structure of the device to
2540 + *                     close.
2541 + *
2542 + *     This function shuts down the adapter.
2543 + *
2544 + **************************************************************/
2545 +static int cpmac_dev_close(struct net_device *p_dev)
2546 +{
2547 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_dev->priv;
2548 +    CPMAC_ISR_INFO_T     *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
2549 +
2550 +    /* inform the upper layers. */
2551 +    netif_stop_queue(p_dev);
2552 +
2553 +    if(!g_init_enable_flag)
2554 +        cpmac_p_dev_disable(p_dev);
2555 +    else
2556 +        free_irq(p_isr_cb_param->intr, p_isr_cb_param);
2557 +
2558 +    MOD_DEC_USE_COUNT;
2559 +
2560 +    return(0);
2561 +}
2562 +
2563 +static void cpmac_dev_mcast_set(struct net_device *p_dev)
2564 +{
2565 +    CPMAC_PRIVATE_INFO_T    *p_cpmac_priv = p_dev->priv;
2566 +    CPMAC_DRV_HAL_INFO_T    *p_drv_hal    = p_cpmac_priv->drv_hal;
2567 +    CPMAC_ABILITY_INFO_T    *p_capability = p_cpmac_priv->ability_info;
2568 +    HAL_FUNCTIONS           *p_hal_funcs  = p_drv_hal->hal_funcs;
2569 +    HAL_DEVICE              *p_hal_dev    = p_drv_hal->hal_dev;
2570 +    int                     val           = 1;
2571 +    int                     channel       = 0;
2572 +
2573 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
2574 +//    if(netif_carrier_ok(p_dev))
2575 +//      avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
2576 +//#endif
2577 +
2578 +    if(p_dev->flags & IFF_PROMISC)
2579 +    {
2580 +        if(p_capability->promiscous)
2581 +        {
2582 +            /* multi mode in the HAL, check this */
2583 +           val = 0;
2584 +           p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2585 +
2586 +           val = 1;
2587 +            /* set the promiscous mode in the HAL */
2588 +            p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2589 +            p_hal_funcs->Control(p_hal_dev, pszRX_PROM_CH, pszSet, &channel);
2590 +
2591 +                   dbgPrint("%s set in the Promisc mode.\n", p_dev->name);
2592 +       }
2593 +        else
2594 +        {
2595 +           errPrint("%s not configured for Promisc mode.\n", p_dev->name);
2596 +        }
2597 +    }
2598 +    else if(p_dev->flags & IFF_ALLMULTI)
2599 +    {
2600 +        if(p_capability->all_multi)
2601 +        {
2602 +           val = 0;
2603 +           /* disable the promiscous mode in the HAL */
2604 +           p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, "Clear", &val);
2605 +
2606 +           val = 1;
2607 +            /* set the all multi mode in the HAL */
2608 +           p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, pszSet, &val);
2609 +           p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel);
2610 +
2611 +            dbgPrint("%s has been set to the ALL_MULTI mode.\n", p_dev->name);
2612 +        }
2613 +        else
2614 +        {
2615 +           errPrint("%s not configured for ALL MULTI mode.\n", p_dev->name);
2616 +        }
2617 +    }
2618 +    else if(p_dev->mc_count)
2619 +    {
2620 +        if(p_capability->multicast)
2621 +        {
2622 +           struct dev_mc_list *p_dmi = p_dev->mc_list;
2623 +            int    count;
2624 +
2625 +            val = 0;
2626 +            /* clear all the previous data, we are going to populate new ones.*/
2627 +           p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2628 +           /* disable the promiscous mode in the HAL */
2629 +           p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2630 +
2631 +           for(count = 0; count < p_dev->mc_count; count++, p_dmi = p_dmi->next)
2632 +           {
2633 +               p_hal_funcs->Control(p_hal_dev, "RX_MULTI_SINGLE", "Set", p_dmi->dmi_addr);
2634 +           }
2635 +
2636 +            dbgPrint("%s configured for %d multicast addresses.\n", p_dev->name, p_dev->mc_count);
2637 +        }
2638 +        else
2639 +        {
2640 +           errPrint("%s has not been configuted for multicast handling.\n", p_dev->name);
2641 +        }
2642 +    }
2643 +    else
2644 +    {
2645 +       val = 0;
2646 +       /* clear all the previous data, we are going to populate new ones.*/
2647 +       p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2648 +       /* disable the promiscous mode in the HAL */
2649 +       p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2650 +       dbgPrint("Dev set to  Unicast mode.\n");
2651 +    }
2652 +}
2653 +
2654 +static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr)
2655 +{
2656 +    CPMAC_PRIVATE_INFO_T    *p_cpmac_priv = p_dev->priv;
2657 +    CPMAC_DRV_HAL_INFO_T    *p_drv_hal    = p_cpmac_priv->drv_hal;
2658 +    HAL_FUNCTIONS           *p_hal_funcs  = p_drv_hal->hal_funcs;
2659 +    HAL_DEVICE              *p_hal_dev    = p_drv_hal->hal_dev;
2660 +    struct sockaddr *sa = addr;
2661 +
2662 +   memcpy(p_cpmac_priv->mac_addr,sa->sa_data,p_dev->addr_len);
2663 +   memcpy(p_dev->dev_addr,sa->sa_data,p_dev->addr_len);
2664 +   p_hal_funcs->Control(p_hal_dev, pszMacAddr, pszSet, p_cpmac_priv->mac_addr);
2665 +
2666 +       return 0;
2667 +
2668 +}
2669 +
2670 +/* VLAN is handled by vlan/vconfig support. Here, we just check for the
2671 + * 802.1q configuration of the device and en-queue the packet accordingly.
2672 + * We do not do any 802.1q processing here.
2673 + */
2674 +static int cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev)
2675 +{
2676 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv  = p_dev->priv;
2677 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal     = p_cpmac_priv->drv_hal;
2678 +    int channel                         = 0;
2679 +    int ret_val                         = 0;
2680 +    FRAGLIST             send_frag_list[1];
2681 +
2682 +#ifdef CPMAC_8021Q_SUPPORT
2683 +    if(skb->len < TCI_END_OFFSET)
2684 +    {
2685 +        /* Whee, frame shorter than 14 bytes !! We need to copy
2686 +        * fragments to understand the frame. Too much work.
2687 +        * Hmm, dump it. */
2688 +
2689 +        /* Free the buffer */
2690 +       goto cpmac_dev_tx_drop_pkt;
2691 +    }
2692 +
2693 +    /* 802.1p/q stuff */
2694 +    if(IS_802_1Q_FRAME(skb->data + TPID_START_OFFSET))
2695 +    {
2696 +        /* IEEE 802.1q, section 8.8 and section 8.11.9 */
2697 +        if(!p_cpmac_priv->enable_802_1q)
2698 +        {
2699 +           /* free the buffer */
2700 +           goto cpmac_dev_tx_drop_pkt;
2701 +        }
2702 +
2703 +        channel = GET_802_1P_CHAN(p_cpmac_priv->tx_chan_info->opened_chan,
2704 +                                 skb->data[TCI_START_OFFSET]);
2705 +
2706 +    }
2707 +    /* sending a non 802.1q frame, when configured for 802.1q: dump it.*/
2708 +    else if(p_cpmac_priv->enable_802_1q)
2709 +    {
2710 +         /* free the buffer */
2711 +        goto cpmac_dev_tx_drop_pkt;
2712 +    }
2713 +    else
2714 +    {
2715 +        ;/* it is the good old non 802.1q */
2716 +    }
2717 +#endif
2718 +
2719 +    send_frag_list->len  = skb->len;
2720 +    send_frag_list->data = skb->data;
2721 +
2722 +#ifdef CPMAC_TEST
2723 +    xdump(skb->data, skb->len, "send");
2724 +#endif
2725 +
2726 +    dma_cache_wback_inv((unsigned long)skb->data, skb->len);
2727 +
2728 +    if(p_drv_hal->hal_funcs->Send(p_drv_hal->hal_dev, send_frag_list, 1,
2729 +                                 skb->len, skb, channel) != 0)
2730 +    {
2731 +       /* code here to stop the queue, when allowing tx timeout, perhaps next release.*/
2732 +        p_cpmac_priv->net_dev_stats.tx_errors++;
2733 +#ifndef TI_SLOW_PATH
2734 +       /* Free the skb in case of Send return error */
2735 +        dev_kfree_skb_any(skb);
2736 +        p_cpmac_priv->net_dev_stats.tx_dropped++;
2737 +        return 0;
2738 +#endif
2739 +        goto cpmac_dev_tx_drop_pkt;
2740 +    }
2741 +
2742 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
2743 +//    avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_TX_ACTIVITY);
2744 +//#endif
2745 +
2746 +    return(ret_val);
2747 +
2748 +cpmac_dev_tx_drop_pkt:
2749 +
2750 +    p_cpmac_priv->net_dev_stats.tx_dropped++;
2751 +    ret_val = -1;
2752 +    return (ret_val);
2753 +
2754 +} /*cpmac_dev_tx */
2755 +
2756 +
2757 +//------------------------------------------------------------------------------
2758 +// Public functions : Called by outsiders to this file.
2759 +//------------------------------------------------------------------------------
2760 +
2761 +
2762 +void *cpmac_hal_malloc_buffer(unsigned int size, void* mem_base, unsigned int mem_range,
2763 +                             OS_SETUP *p_os_setup, HAL_RECEIVEINFO *HalReceiveInfo,
2764 +                             OS_RECEIVEINFO **osReceiveInfo, OS_DEVICE *p_dev)
2765 +{
2766 +    CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = (CPMAC_RX_CHAN_INFO_T *)p_os_setup;
2767 +    int                  tot_buf_size    = p_rx_chan_info->chan->tot_buf_size;
2768 +    int             tot_reserve_bytes    = p_rx_chan_info->chan->tot_reserve_bytes;
2769 +    struct sk_buff  *p_skb;
2770 +    void             *ret_ptr;
2771 +
2772 +    /* use TI SKB private pool */
2773 +    p_skb = dev_alloc_skb(tot_buf_size);
2774 +
2775 +    if(p_skb == NULL)
2776 +    {
2777 +        errPrint("Failed to allocate skb for %s.\n", ((struct net_device*)p_dev)->name);
2778 +        return (NULL);
2779 +    }
2780 +
2781 +    p_skb->dev = p_dev;
2782 +    skb_reserve(p_skb, tot_reserve_bytes);
2783 +
2784 +    *osReceiveInfo = p_skb;
2785 +
2786 +    ret_ptr = skb_put(p_skb, p_rx_chan_info->chan->buffer_size);
2787 +
2788 +    return(ret_ptr);
2789 +}
2790 +
2791 +void cpmac_hal_isr(int irq, void *p_param, struct pt_regs *regs)
2792 +{
2793 +    CPMAC_ISR_INFO_T      *p_cb_param    = (CPMAC_ISR_INFO_T*) p_param;
2794 +    CPMAC_DRV_HAL_INFO_T  *p_drv_hal     = p_cb_param->owner;
2795 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_drv_hal->owner;
2796 +    int                   pkts_to_handle = 0;
2797 +
2798 +    if(p_cpmac_priv->non_data_irq_expected)
2799 +    {
2800 +        p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
2801 +        p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
2802 +    }
2803 +    else if(!p_cpmac_priv->set_to_close)
2804 +        tasklet_schedule(&((CPMAC_ISR_INFO_T*) p_param)->tasklet);
2805 +    else
2806 +        ; // back off from doing anything more. We are closing down.
2807 +}
2808 +
2809 +void cpmac_handle_tasklet(unsigned long data)
2810 +{
2811 +    CPMAC_ISR_INFO_T     *p_cb_param   = (CPMAC_ISR_INFO_T*) data;
2812 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal    = p_cb_param->owner;
2813 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_drv_hal->owner;
2814 +    int                  pkts_to_handle;
2815 +
2816 +    p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
2817 +
2818 +    if(test_bit(0, &p_cpmac_priv->non_data_irq_expected) || !pkts_to_handle)
2819 +        p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
2820 +    else if(!test_bit(0, &p_cpmac_priv->set_to_close))
2821 +        tasklet_schedule(&p_cb_param->tasklet);
2822 +    else
2823 +        ; // Back off from processing packets we are closing down.
2824 +}
2825 +
2826 +int cpmac_hal_control(OS_DEVICE *p_dev, const char *key,
2827 +                     const char *action, void *value)
2828 +{
2829 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2830 +    int ret_val = -1;
2831 +
2832 +    if(key == NULL)
2833 +    {
2834 +        dbgPrint("Encountered NULL key.\n");
2835 +       return (-1);
2836 +    }
2837 +
2838 +    if(cpmac_ci_strcmp(key, "Sleep") == 0 && value != NULL)
2839 +    {
2840 +        unsigned int clocks_per_tick  = cpmac_cpu_freq/HZ;
2841 +       unsigned int requested_clocks = *(unsigned int*)value;
2842 +       unsigned int requested_ticks  = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
2843 +        mdelay(requested_ticks);
2844 +       ret_val = 0;
2845 +    }
2846 +    else if(cpmac_ci_strcmp(key, "StateChange") == 0)
2847 +    {
2848 +        ret_val = cpmac_p_process_status_ind(p_cpmac_priv);
2849 +    }
2850 +    else if(cpmac_ci_strcmp(key, "Tick") == 0 && action != NULL)
2851 +    {
2852 +       if(cpmac_ci_strcmp(action, "Set") == 0 && value != NULL)
2853 +       {
2854 +            if(*(unsigned int*)value == 0)
2855 +            {
2856 +                cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
2857 +                ret_val = 0;
2858 +            }
2859 +            else
2860 +            {
2861 +                unsigned int clocks_per_tick  = cpmac_cpu_freq/HZ;
2862 +               unsigned int requested_clocks = *(unsigned int*)value;
2863 +               unsigned int requested_ticks  = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
2864 +
2865 +                p_cpmac_priv->delay_ticks =  requested_ticks; /* save it for re-triggering */
2866 +               ret_val = cpmac_p_start_timer(p_cpmac_priv->timer + TICK_TIMER,
2867 +                                             p_cpmac_priv->delay_ticks);
2868 +            }
2869 +       }
2870 +        else if(cpmac_ci_strcmp(action, "Clear") == 0)
2871 +        {
2872 +            ret_val = cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
2873 +        }
2874 +        else
2875 +            ;
2876 +    }
2877 +    else if(cpmac_ci_strcmp(key, "MacAddr") == 0 && action != NULL)
2878 +    {
2879 +        if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2880 +       {
2881 +            *(char **)value = p_cpmac_priv->mac_addr;
2882 +           ret_val = 0;
2883 +       }
2884 +    }
2885 +    else if(cpmac_ci_strcmp(key, "CpuFreq") == 0)
2886 +    {
2887 +       if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2888 +       {
2889 +           *(unsigned int *)value = cpmac_cpu_freq;
2890 +           dbgPrint("Cpu frequency for cpmacs is %u\n",cpmac_cpu_freq);
2891 +           ret_val = 0;
2892 +       }
2893 +    }
2894 +    else if(cpmac_ci_strcmp(key, "SioFlush") == 0)
2895 +    {
2896 +       ret_val = 0;
2897 +       dbgPrint("\n");
2898 +    }
2899 +    else if(cpmac_ci_strcmp(key, "CpmacFrequency") == 0)
2900 +    {
2901 +        /* For Sangam cpmac clock is off the PBUS */
2902 +        /* OS Needs to supply CORRECT frequency */
2903 +        if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2904 +        {
2905 +            *(unsigned int *)value = CONFIG_AR7_SYS_FREQUENCY * 1000 * 1000;
2906 +            ret_val = 0;
2907 +        }
2908 +    }
2909 +    /* For now, providing back the default values. */
2910 +    else if(cpmac_ci_strcmp(key, "MdioClockFrequency") == 0)
2911 +    {
2912 +        if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2913 +        {
2914 +            *(unsigned int *)value = 2200000;  /*DEFAULT */
2915 +            ret_val = 0;
2916 +        }
2917 +    }
2918 +    /* For now, providing back the default values. */
2919 +    else if(cpmac_ci_strcmp(key, "MdioBusFrequency") == 0)
2920 +    {
2921 +        /* For Sangam MdioBusFreq is off the PBUS */
2922 +        if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2923 +        {
2924 +            *(unsigned int *)value = CONFIG_AR7_SYS_FREQUENCY * 1000 * 1000;
2925 +            ret_val = 0;
2926 +        }
2927 +    }
2928 +
2929 +#if 0
2930 +#if defined(CONFIG_AVALANCHE_AUTO_MDIX)
2931 +    /* supporting Mdio Mdix switching */
2932 +    else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
2933 +    {
2934 +        /* For Sangam Mdio-switching  action should be always "set"*/
2935 +        if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
2936 +        {
2937 +           unsigned  int mdix =  *((unsigned int *) value) ;
2938 +
2939 +           if(mdix)
2940 +              avalanche_set_phy_into_mdix_mode();
2941 +
2942 +           else
2943 +              avalanche_set_phy_into_mdi_mode();
2944 +
2945 +           ret_val = 0;
2946 +        }
2947 +
2948 +    }
2949 +#endif
2950 +#endif
2951 +    else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
2952 +    {
2953 +        /* For Sangam Mdio-switching  action should be always "set"*/
2954 +        if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
2955 +        {
2956 +           unsigned  int mdix =  *((unsigned int *) value) ;
2957 +
2958 +#ifdef CONFIG_AR7_MDIX
2959 +          avalanche_set_mdix_on_chip(0xa8610000 , mdix ? 1: 0);
2960 +#endif
2961 +
2962 +           ret_val = 0;
2963 +        }
2964 +
2965 +    }
2966 +
2967 +    return(ret_val);
2968 +}
2969 +
2970 +
2971 +int cpmac_hal_receive(OS_DEVICE *p_dev, FRAGLIST *fragList,
2972 +                             unsigned int fragCount,
2973 +                             unsigned int packet_size,
2974 +                             HAL_RECEIVEINFO *hal_receive_info,
2975 +                             unsigned int mode)
2976 +{
2977 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv  = p_dev->priv;
2978 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal     = p_cpmac_priv->drv_hal;
2979 +    struct sk_buff       *p_skb         = fragList[0].OsInfo;
2980 +    p_skb->len                          = fragList[0].len;
2981 +
2982 +    /* invalidate the cache. */
2983 +    dma_cache_inv((unsigned long)p_skb->data, fragList[0].len);
2984 +#ifdef CPMAC_TEST
2985 +    xdump(p_skb->data, p_skb->len, "recv");
2986 +#endif
2987 +#ifdef CPMAC_8021Q_SUPPORT
2988 +    /* 802.1q stuff, just does the basic checking here. */
2989 +    if(!p_cpmac_priv->enable_802_1q      &&
2990 +       p_skb->len > TCI_END_OFFSET       &&
2991 +       IS_802_1Q_FRAME(p_skb->data + TPID_START_OFFSET))
2992 +    {
2993 +         goto cpmac_hal_recv_frame_mismatch;
2994 +    }
2995 +#endif
2996 +    if(fragCount > 1)
2997 +    {
2998 +       int     len;
2999 +       struct sk_buff *p_temp_skb;
3000 +       CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
3001 +       int     count;
3002 +
3003 +       dbgPrint("Recv: It is multifragment for %s.\n", p_dev->name);
3004 +
3005 +       p_skb = dev_alloc_skb(packet_size +
3006 +          p_rx_chan_info->chan->tot_reserve_bytes);
3007 +       if(p_skb == NULL)
3008 +       {
3009 +          p_cpmac_priv->net_dev_stats.rx_errors++;
3010 +          goto cpmac_hal_recv_alloc_failed;
3011 +       }
3012 +
3013 +       p_skb->dev = p_dev;
3014 +       skb_reserve(p_skb, p_rx_chan_info->chan->tot_reserve_bytes);
3015 +
3016 +       for(count = 0; count < fragCount; count++)
3017 +       {
3018 +          p_temp_skb = fragList[count].OsInfo;
3019 +          len        = fragList[count].len;
3020 +
3021 +          dma_cache_inv((unsigned long)p_temp_skb->data, len);
3022 +
3023 +          memcpy(skb_put(p_skb, len), p_temp_skb->data, len);
3024 +          dev_kfree_skb_any(p_temp_skb);
3025 +       }
3026 +    }
3027 +
3028 +
3029 +#if defined(CONFIG_MIPS_AVALANCHE_MARVELL)
3030 + /* Fetch the receiving port information from EGRESS TRAILOR Bytes*/
3031 +     p_dev->if_port = (unsigned char)p_skb->data[packet_size -(EGRESS_TRAILOR_LEN-1)] + AVALANCHE_MARVELL_BASE_PORT_ID;
3032 +    skb_trim(p_skb, packet_size - EGRESS_TRAILOR_LEN);
3033 +#else
3034 +    /* set length & tail */
3035 +    skb_trim(p_skb, packet_size);
3036 +#endif
3037 +
3038 +#ifndef TI_SLOW_PATH
3039 +    /* TI Optimization: This is NOT required if the ethernet resides below the bridge. But is
3040 +    * required only if the ethernet is directly connected to the IP stack. */
3041 +    if (p_dev->br_port == NULL)
3042 +#endif
3043 +       p_skb->protocol = eth_type_trans(p_skb, p_dev);
3044 +
3045 +    netif_rx(p_skb);
3046 +
3047 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
3048 +//    avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_RX_ACTIVITY);
3049 +//#endif
3050 +
3051 +    p_cpmac_priv->net_dev_stats.rx_packets++;
3052 +    p_cpmac_priv->net_dev_stats.rx_bytes += packet_size;
3053 +
3054 +    p_drv_hal->hal_funcs->RxReturn(hal_receive_info,1);
3055 +
3056 +    return(0);
3057 +
3058 +cpmac_hal_recv_alloc_failed:
3059 +
3060 +#ifdef CPMAC_8021Q_SUPPORT
3061 +cpmac_hal_recv_frame_mismatch:
3062 +#endif
3063 +
3064 +    fragCount--;
3065 +
3066 +    do
3067 +    {
3068 +        dev_kfree_skb_any(fragList[fragCount].OsInfo);
3069 +    }
3070 +    while(fragCount--);
3071 +
3072 +    p_cpmac_priv->net_dev_stats.rx_dropped++;
3073 +
3074 +    return(-1);
3075 +} /*cpmac_receive*/
3076 +
3077 +
3078 +void cpmac_hal_tear_down_complete(OS_DEVICE*a, int b, int ch)
3079 +{
3080 +    dbgPrint("what to do with this.\n");
3081 +}
3082 +
3083 +
3084 +int  cpmac_hal_send_complete(OS_SENDINFO *p_skb)
3085 +{
3086 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_skb->dev->priv;
3087 +
3088 +    p_cpmac_priv->net_dev_stats.tx_packets++;
3089 +    p_cpmac_priv->net_dev_stats.tx_bytes += p_skb->len;
3090 +
3091 +    dev_kfree_skb_any(p_skb);
3092 +
3093 +    return(0);
3094 +}
3095 +
3096 +
3097 +int cpmac_reset(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
3098 +{
3099 +    // code here to reset the device/hal. Not now.
3100 +
3101 +   netif_wake_queue(p_cpmac_priv->owner);
3102 +   return(0);
3103 +}
3104 +
3105 +#ifdef CPMAC_TEST
3106 +
3107 +#define isprint(a) ((a >=' ')&&(a<= '~'))
3108 +void xdump( u_char*  cp, int  length, char*  prefix )
3109 +{
3110 +    int col, count;
3111 +    u_char prntBuf[120];
3112 +    u_char*  pBuf = prntBuf;
3113 +    count = 0;
3114 +    while(count < length){
3115 +        pBuf += sprintf( pBuf, "%s", prefix );
3116 +        for(col = 0;count + col < length && col < 16; col++){
3117 +            if (col != 0 && (col % 4) == 0)
3118 +                pBuf += sprintf( pBuf, " " );
3119 +            pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
3120 +        }
3121 +        while(col++ < 16){      /* pad end of buffer with blanks */
3122 +            if ((col % 4) == 0)
3123 +                sprintf( pBuf, " " );
3124 +            pBuf += sprintf( pBuf, "   " );
3125 +        }
3126 +        pBuf += sprintf( pBuf, "  " );
3127 +        for(col = 0;count + col < length && col < 16; col++){
3128 +            if (isprint((int)cp[count + col]))
3129 +                pBuf += sprintf( pBuf, "%c", cp[count + col] );
3130 +            else
3131 +                pBuf += sprintf( pBuf, "." );
3132 +                }
3133 +        sprintf( pBuf, "\n" );
3134 +        // SPrint(prntBuf);
3135 +        printk(prntBuf);
3136 +        count += col;
3137 +        pBuf = prntBuf;
3138 +    }
3139 +
3140 +}  /* close xdump(... */
3141 +#endif
3142 +
3143 +
3144 +static int __init cpmac_dev_probe(void)
3145 +{
3146 +    int     retVal         = 0;
3147 +    int     unit;
3148 +    int     instance_count = CONFIG_MIPS_CPMAC_PORTS;
3149 +
3150 +    //cpmac_cpu_freq = avalanche_clkc_get_freq(CLKC_MIPS);
3151 +    cpmac_cpu_freq = CONFIG_AR7_CPU_FREQUENCY * 1000 * 1000;
3152 +
3153 +    build_psp_config();
3154 +
3155 +    for(unit = 0; unit < instance_count; unit++)
3156 +    {
3157 +        struct net_device              *p_dev;
3158 +        CPMAC_PRIVATE_INFO_T            *p_cpmac_priv;
3159 +        size_t                         dev_size;
3160 +       int                             failed;
3161 +
3162 +        dev_size =    sizeof(struct net_device)
3163 +                   + sizeof(CPMAC_PRIVATE_INFO_T);
3164 +
3165 +
3166 +        if((p_dev = (struct net_device *) kmalloc(dev_size, GFP_KERNEL)) == NULL)
3167 +        {
3168 +            dbgPrint( "Could not allocate memory for device.\n" );
3169 +            retVal = -ENOMEM;
3170 +            break;
3171 +        }
3172 +
3173 +        memset(p_dev, 0, dev_size );
3174 +
3175 +        p_dev->priv                 = p_cpmac_priv
3176 +                                    = (CPMAC_PRIVATE_INFO_T*)(((char *) p_dev) + sizeof(struct net_device));
3177 +        p_cpmac_priv->owner         = p_dev;
3178 +
3179 +        ether_setup(p_dev);
3180 +
3181 +       p_cpmac_priv->instance_num  = unit;
3182 +        p_dev->init                 = cpmac_dev_init;
3183 +
3184 +        g_dev_array[p_cpmac_priv->instance_num] = p_dev;
3185 +
3186 +#if defined CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC
3187 +        g_init_enable_flag = 1;
3188 +        printk("Cpmac driver is allocating buffer memory at init time.\n");
3189 +#endif
3190 +
3191 +       /* This section gives a default value by the number of PHY in order to
3192 +        * replace the default MACRO. */
3193 +       {
3194 +           char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
3195 +           if(!mac_port || (0 != strcmp(mac_port, "0"))) {
3196 +               printk("Using the MAC with external PHY\n");
3197 +               cfg_start_link_speed = _CPMDIO_NOPHY;
3198 +               cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE + 4;
3199 +           }
3200 +           else {
3201 +               printk("Using the MAC with internal PHY\n");
3202 +               cfg_start_link_speed = CFG_START_LINK_SPEED;
3203 +               cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE;
3204 +           }
3205 +           g_cfg_start_link_params = cfg_start_link_speed;
3206 +       }
3207 +
3208 +        cpmac_p_detect_manual_cfg(cfg_link_speed, cfg_link_mode, cpmac_debug_mode);
3209 +
3210 +       failed = register_netdev(p_dev);
3211 +        if (failed)
3212 +        {
3213 +            dbgPrint("Could not register device for inst %d because of reason \
3214 +                      code %d.\n", unit, failed);
3215 +            retVal = -1;
3216 +            kfree(p_dev);
3217 +            break;
3218 +        }
3219 +        else
3220 +        {
3221 +
3222 +            char proc_name[100];
3223 +            int  proc_category_name_len = 0;
3224 +
3225 +           p_cpmac_priv->next_device = last_cpmac_device;
3226 +            last_cpmac_device         = p_dev;
3227 +
3228 +           dbgPrint(" %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq,
3229 +                      (int) p_dev->base_addr);
3230 +
3231 +           strcpy(proc_name, "avalanche/");
3232 +            strcat(proc_name, p_dev->name);
3233 +            proc_category_name_len = strlen(proc_name);
3234 +
3235 +            strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
3236 +            create_proc_read_entry(proc_name,0,NULL,cpmac_p_read_rfc2665_stats, p_dev);
3237 +
3238 +       }
3239 +    }
3240 +
3241 +    if(retVal == 0)
3242 +    {
3243 +       /* To maintain backward compatibility with NSP. */
3244 +        gp_stats_file = create_proc_entry("avalanche/cpmac_stats", 0644, NULL);
3245 +        if(gp_stats_file)
3246 +        {
3247 +            gp_stats_file->read_proc  = cpmac_p_read_stats;
3248 +            gp_stats_file->write_proc = cpmac_p_write_stats;
3249 +        }
3250 +       create_proc_read_entry("avalanche/cpmac_link", 0, NULL, cpmac_p_read_link, NULL);
3251 +       create_proc_read_entry("avalanche/cpmac_ver", 0, NULL, cpmac_p_get_version, NULL);
3252 +
3253 +    }
3254 +
3255 +    cpmac_devices_installed  = unit;
3256 +    dbgPrint("Installed %d cpmac instances.\n", unit);
3257 +    return ( (unit >= 0 ) ? 0 : -ENODEV );
3258 +
3259 +} /* init_module */
3260 +
3261 +
3262 +/***************************************************************
3263 + *     cleanup_module
3264 + *
3265 + *     Returns:
3266 + *             Nothing
3267 + *     Parms:
3268 + *             None
3269 + *
3270 + *     Goes through the CpmacDevices list and frees the device
3271 + *     structs and memory associated with each device (lists
3272 + *     and buffers).  It also ureserves the IO port regions
3273 + *     associated with this device.
3274 + *
3275 + **************************************************************/
3276 +
3277 +void cpmac_exit(void)
3278 +{
3279 +    struct net_device       *p_dev;
3280 +    CPMAC_PRIVATE_INFO_T    *p_cpmac_priv;
3281 +
3282 +    while (cpmac_devices_installed)
3283 +    {
3284 +        char proc_name[100];
3285 +        int  proc_category_name_len = 0;
3286 +
3287 +        p_dev = last_cpmac_device;
3288 +        p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
3289 +
3290 +       dbgPrint("Unloading %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq, (int) p_dev->base_addr);
3291 +
3292 +        if(g_init_enable_flag)
3293 +            cpmac_p_dev_disable(p_dev);
3294 +
3295 +        cpmac_drv_cleanup(p_cpmac_priv->drv_hal);
3296 +
3297 +//#if defined (CONFIG_MIPS_AVALANCHE_LED)
3298 +//        avalanche_led_unregister(p_cpmac_priv->led_handle);
3299 +//#endif
3300 +       strcpy(proc_name, "avalanche/");
3301 +        strcat(proc_name, p_dev->name);
3302 +        proc_category_name_len = strlen(proc_name);
3303 +
3304 +        strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
3305 +        remove_proc_entry(proc_name, NULL);
3306 +
3307 +        release_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size);
3308 +        unregister_netdev(p_dev);
3309 +       last_cpmac_device = p_cpmac_priv->next_device;
3310 +
3311 +        kfree(p_cpmac_priv->drv_hal);
3312 +        kfree(p_dev);
3313 +
3314 +       cpmac_devices_installed--;
3315 +    }
3316 +
3317 +    if(gp_stats_file)
3318 +        remove_proc_entry("avalanche/cpmac_stats", NULL);
3319 +
3320 +    remove_proc_entry("avalanche/cpmac_link",  NULL);
3321 +    remove_proc_entry("avalanche/cpmac_ver",   NULL);
3322 +
3323 +    psp_config_cleanup();
3324 +}
3325 +
3326 +
3327 +module_init(cpmac_dev_probe);
3328 +module_exit(cpmac_exit);
3329 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpmac.h
3330 --- linux.old/drivers/net/avalanche_cpmac/cpmac.h       1970-01-01 01:00:00.000000000 +0100
3331 +++ linux.dev/drivers/net/avalanche_cpmac/cpmac.h       2005-07-12 02:48:42.043594000 +0200
3332 @@ -0,0 +1,379 @@
3333 +/******************************************************************************
3334 + * FILE PURPOSE:    CPMAC Linux Network Device Driver Header
3335 + ******************************************************************************
3336 + * FILE NAME:       cpmac.h
3337 + *
3338 + * DESCRIPTION:     CPMAC Network Device Driver Header
3339 + *
3340 + * REVISION HISTORY:
3341 + * Date            Name                   Details
3342 + *-----------------------------------------------------------------------------
3343 + * 27 Nov 2002     Suraj S Iyer           Initial Create.
3344 + * 09 Jun 2003     Suraj S Iyer           Preparing for GA.
3345 + *
3346 + * (C) Copyright 2003, Texas Instruments, Inc
3347 + *******************************************************************************/
3348 +
3349 +#ifndef CPMAC_H
3350 +#define CPMAC_H
3351 +
3352 +#include <linux/timer.h>
3353 +#include <linux/netdevice.h>
3354 +#include <asm/semaphore.h>
3355 +#include <linux/ctype.h>
3356 +#include <linux/interrupt.h>
3357 +
3358 +#include "cpmacHalLx.h"
3359 +/*-----------------------------------------------------------------------------
3360 + * Config macros. Use these to config the driver.
3361 + *---------------------------------------------------------------------------*/
3362 +#define CPMAC_MAX_FRAME_SIZE         1518
3363 +
3364 +#if defined(CONFIG_AR7WRD) || defined(CONFIG_AR7WI) || defined(CONFIG_AR7VWI)|| defined(CONFIG_AR7VW)
3365 +#define CFG_RX_NUM_BUF_DESC            64
3366 +#define CFG_RX_NUM_BUF_SERVICE         32
3367 +#else
3368 +#define CFG_RX_NUM_BUF_DESC            16
3369 +#define CFG_RX_NUM_BUF_SERVICE         8
3370 +#endif
3371 +
3372 +#define CFG_RX_BUF_OFFSET              0
3373 +
3374 +#define CFG_TX_NUM_BUF_DESC            128
3375 +#define CFG_TX_NUM_BUF_SERVICE         20
3376 +#define CFG_TX_BUF_OFFSET              0  /* Lets not change this. */
3377 +#define CFG_TX_TIMEOUT                 2000 /* ticks*/
3378 +#define CFG_TX_INT_DISABLE             1  /* Disable the Tx Complete interrupt */
3379 +
3380 +#define CFG_JUMBO_FRAMES               1
3381 +#define CFG_SHORT_FRAMES               1
3382 +#define CFG_PROMISCOUS                 1
3383 +#define CFG_BROADCAST                  1
3384 +#define CFG_MULTICAST                  1
3385 +#define CFG_ALL_MULTI                  (1*(CFG_MULTICAST))
3386 +#define CFG_AUTO_NEGOTIATION           1
3387 +
3388 +#if defined (CONFIG_MIPS_AVALANCHE_MARVELL)
3389 +#define EGRESS_TRAILOR_LEN             4
3390 +#define CFG_START_LINK_SPEED           (_CPMDIO_NOPHY)
3391 +#undef  CPMAC_MAX_FRAME_SIZE
3392 +#define CPMAC_MAX_FRAME_SIZE          (1518 + EGRESS_TRAILOR_LEN)
3393 +#else
3394 +#define CFG_START_LINK_SPEED          (_CPMDIO_10 | _CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD) /* auto nego */
3395 +#endif
3396 +
3397 +#define CFG_LOOP_BACK                  1
3398 +#define CFG_TX_FLOW_CNTL               0
3399 +#define CFG_RX_FLOW_CNTL               0
3400 +#define CFG_TX_PACING                  0
3401 +#define CFG_RX_PASS_CRC                0
3402 +#define CFG_QOS_802_1Q                 0
3403 +#define CFG_TX_NUM_CHAN                1
3404 +
3405 +
3406 +/*-----------------------------------------------------------------------------
3407 + * Private macros.
3408 + *---------------------------------------------------------------------------*/
3409 +#define MAX_TIMER               2
3410 +#define TX_TIMER                0
3411 +#define TICK_TIMER              0
3412 +#define MAX_TX_CHAN             8
3413 +
3414 +#define CPMAC_LINK_OFF          0
3415 +#define CPMAC_LINK_ON           1
3416 +/*#define CPMAC_SPEED_100         2
3417 +#define CPMAC_SPEED_10          3
3418 +#define CPMAC_FULL_DPLX         4
3419 +#define CPMAC_HALF_DPLX         5*/
3420 +#define CPMAC_RX_ACTIVITY       2
3421 +#define CPMAC_TX_ACTIVITY       3
3422 +
3423 +struct cpmac_timer_info;
3424 +
3425 +typedef int  (*CPMAC_HAL_ISR_FUNC_T)(HAL_DEVICE*, int*);
3426 +typedef int  (*CPMAC_TIMEOUT_CB_T)(struct cpmac_timer_info*);
3427 +
3428 +typedef struct cpmac_ability_info
3429 +{
3430 +    int promiscous;
3431 +    int broadcast;
3432 +    int multicast;
3433 +    int all_multi;
3434 +    int loop_back;
3435 +    int jumbo_frames;
3436 +    int short_frames;
3437 +    int auto_negotiation;
3438 +    int tx_flow_control;
3439 +    int rx_flow_control;
3440 +    int tx_pacing;
3441 +    int link_speed;
3442 +    int rx_pass_crc;
3443 +    int qos_802_1q;
3444 +    int tx_num_chan;
3445 +}
3446 +CPMAC_ABILITY_INFO_T;
3447 +
3448 +#ifdef DEBUG
3449 +typedef struct cpmac_timer_info
3450 +{
3451 +    void               *owner;
3452 +    UINT32             delay_ticks;
3453 +    WDOG_ID            timer_id;
3454 +    UINT32             is_running;
3455 +    UINT32             timer_set_at;
3456 +    CPMAC_TIMEOUT_CB_T timeout_CB;
3457 +} CPMAC_TIMER_INFO_T;
3458 +
3459 +typedef struct
3460 +{
3461 +    void               *owner;
3462 +    unsigned int       num_cl_desc;
3463 +    CL_DESC            *cl_desc_tbl;
3464 +    M_CL_CONFIG        *m_cl_blk_config;
3465 +    NET_POOL           *net_pool;
3466 +    CL_POOL_ID         clPoolId;
3467 +
3468 +} CPMAC_NET_MEM_INFO_T;
3469 +
3470 +#endif
3471 +
3472 +typedef struct
3473 +{
3474 +    void                  *owner;
3475 +    CPMAC_HAL_ISR_FUNC_T  hal_isr;
3476 +    struct tasklet_struct tasklet;
3477 +    int                   intr;
3478 +
3479 +} CPMAC_ISR_INFO_T;
3480 +
3481 +typedef struct cpmac_chan
3482 +{
3483 +   int num_BD;
3484 +   int buffer_size;
3485 +   int buffer_offset;
3486 +   int service_max;
3487 +   int state;
3488 +   int tot_buf_size;
3489 +   int tot_reserve_bytes;
3490 +
3491 +} CPMAC_CHAN_T;
3492 +
3493 +#define CHAN_CLOSE  0
3494 +#define CHAN_OPENED 1
3495 +
3496 +typedef struct
3497 +{
3498 +    int          cfg_chan;
3499 +    int          dev_chan;
3500 +    int          opened_chan;
3501 +    CPMAC_CHAN_T chan[1];
3502 +    int          enable_802_1q;
3503 +
3504 +} CPMAC_RX_CHAN_INFO_T;
3505 +
3506 +typedef struct
3507 +{
3508 +    int          cfg_chan;
3509 +    int          dev_chan;
3510 +    int          opened_chan;
3511 +    int          tx_int_disable;
3512 +    CPMAC_CHAN_T chan[MAX_TX_CHAN];
3513 +
3514 +} CPMAC_TX_CHAN_INFO_T;
3515 +
3516 +
3517 +
3518 +typedef struct
3519 +{
3520 +   void                        *owner;
3521 +   HAL_FUNCTIONS               *hal_funcs;
3522 +   HAL_DEVICE                  *hal_dev;
3523 +   OS_FUNCTIONS                *os_funcs;
3524 +//   SEM_ID                      chan_teardown_sem;
3525 +   int                         non_data_irq_expected;
3526 +} CPMAC_DRV_HAL_INFO_T;
3527 +
3528 +
3529 +typedef struct
3530 +{
3531 +    unsigned long tx_discards;
3532 +    unsigned long rx_discards;
3533 +    unsigned long start_tick;
3534 +
3535 +} CPMAC_DRV_STATS_T;
3536 +
3537 +typedef struct
3538 +{
3539 +    unsigned long   ifInGoodFrames;
3540 +    unsigned long   ifInBroadcasts;
3541 +    unsigned long   ifInMulticasts;
3542 +    unsigned long   ifInPauseFrames;
3543 +    unsigned long   ifInCRCErrors;
3544 +    unsigned long   ifInAlignCodeErrors;
3545 +    unsigned long   ifInOversizedFrames;
3546 +    unsigned long   ifInJabberFrames;
3547 +    unsigned long   ifInUndersizedFrames;
3548 +    unsigned long   ifInFragments;
3549 +    unsigned long   ifInFilteredFrames;
3550 +    unsigned long   ifInQosFilteredFrames;
3551 +    unsigned long   ifInOctets;
3552 +    unsigned long   ifOutGoodFrames;
3553 +    unsigned long   ifOutBroadcasts;
3554 +    unsigned long   ifOutMulticasts;
3555 +    unsigned long   ifOutPauseFrames;
3556 +    unsigned long   ifDeferredTransmissions;
3557 +    unsigned long   ifCollisionFrames;
3558 +    unsigned long   ifSingleCollisionFrames;
3559 +    unsigned long   ifMultipleCollisionFrames;
3560 +    unsigned long   ifExcessiveCollisionFrames;
3561 +    unsigned long   ifLateCollisions;
3562 +    unsigned long   ifOutUnderrun;
3563 +    unsigned long   ifCarrierSenseErrors;
3564 +    unsigned long   ifOutOctets;
3565 +    unsigned long   if64OctetFrames;
3566 +    unsigned long   if65To127OctetFrames;
3567 +    unsigned long   if128To255OctetFrames;
3568 +    unsigned long   if256To511OctetFrames;
3569 +    unsigned long   if512To1023OctetFrames;
3570 +    unsigned long   if1024ToUPOctetFrames;
3571 +    unsigned long   ifNetOctets;
3572 +    unsigned long   ifRxSofOverruns;
3573 +    unsigned long   ifRxMofOverruns;
3574 +    unsigned long   ifRxDMAOverruns;
3575 +
3576 +} CPMAC_DEVICE_MIB_T;
3577 +
3578 +
3579 +typedef struct
3580 +{
3581 +    void                         *owner;
3582 +    int                          timer_count;
3583 +    int                          timer_created;
3584 +    struct timer_list            timer[1];
3585 +    CPMAC_DRV_HAL_INFO_T         *drv_hal;
3586 +    unsigned int                 num_of_intr;
3587 +    CPMAC_ISR_INFO_T             cpmac_isr;
3588 +    unsigned int                 link_speed;
3589 +    unsigned int                 link_mode;
3590 +    unsigned int                 enable_802_1q;
3591 +    unsigned int                 timer_access_hal;
3592 +    unsigned int                 loop_back;
3593 +    CPMAC_RX_CHAN_INFO_T         *rx_chan_info;
3594 +    CPMAC_TX_CHAN_INFO_T         *tx_chan_info;
3595 +    CPMAC_ABILITY_INFO_T         *ability_info;
3596 +    CPMAC_DEVICE_MIB_T           *device_mib;
3597 +    CPMAC_DRV_STATS_T            *stats;
3598 +    unsigned int                 flags;
3599 +    unsigned int                 delay_ticks;
3600 +    char                         mac_addr[6];
3601 +    struct net_device_stats      net_dev_stats;
3602 +//    rwlock_t                     rw_lock;
3603 +    int                          set_to_close;
3604 +    struct net_device            *next_device;
3605 +    unsigned int                 instance_num;
3606 +    unsigned int                 non_data_irq_expected;
3607 +    unsigned long                dev_size;
3608 +    void*                        led_handle;
3609 +} CPMAC_PRIVATE_INFO_T;
3610 +
3611 +
3612 +/* Private flags */
3613 +
3614 +/* bit 0 to 31, bit 32 is used to indicate set or reset */
3615 +
3616 +#define IFF_PRIV_SHORT_FRAMES   0x00010000
3617 +#define IFF_PRIV_JUMBO_FRAMES   0x00020000
3618 +#define IFF_PRIV_AUTOSPEED      0x00080000
3619 +#define IFF_PRIV_LINK10_HD      0x00100000
3620 +#define IFF_PRIV_LINK10_FD      0x00200000
3621 +#define IFF_PRIV_LINK100_HD     0x00400000
3622 +#define IFF_PRIV_LINK100_FD     0x00800000
3623 +#define IFF_PRIV_8021Q_EN       0x01000000
3624 +#define IFF_PRIV_NUM_TX_CHAN    0x02000000
3625 +#define IFF_PRIV_TX_FLOW_CNTL   0x04000000
3626 +#define IFF_PRIV_RX_FLOW_CNTL   0x08000000
3627 +#define IFF_PRIV_TX_PACING      0x10000000
3628 +#define IFF_PRIV_RX_PASS_CRC    0x20000000
3629 +
3630 +#define PRIVCSFLAGS             0x200
3631 +#define PRIVCGFLAGS             0x201
3632 +
3633 +
3634 +#define BLOCKING      1
3635 +#define CHAN_TEARDOWN 2
3636 +#define CHAN_SETUP    4
3637 +#define COMPLETE      8
3638 +#define FREE_BUFFER   16
3639 +
3640 +
3641 +static const char pszStats0[]            = "Stats0";
3642 +static const char pszStats1[]            = "Stats1";
3643 +static const char pszStats2[]            = "Stats2";
3644 +static const char pszStats3[]            = "Stats3";
3645 +static const char pszStats4[]            = "Stats4";
3646 +static const char pszStatsDump[]         = "StatsDump";
3647 +static const char pszStatsClear[]        = "StatsClear";
3648 +static const char pszRX_PASS_CRC[]       = "RX_PASS_CRC";
3649 +static const char pszRX_QOS_EN[]         = "RX_QOS_EN";
3650 +static const char pszRX_NO_CHAIN[]       = "RX_NO_CHAIN";
3651 +static const char pszRX_CMF_EN[]         = "RX_CMF_EN";
3652 +static const char pszRX_CSF_EN[]         = "RX_CSF_EN";
3653 +static const char pszRX_CEF_EN[]         = "RX_CEF_EN";
3654 +static const char pszRX_CAF_EN[]         = "RX_CAF_EN";
3655 +static const char pszRX_PROM_CH[]        = "RX_PROM_CH";
3656 +static const char pszRX_BROAD_EN[]       = "RX_BROAD_EN";
3657 +static const char pszRX_BROAD_CH[]       = "RX_BROAD_CH";
3658 +static const char pszRX_MULT_EN[]        = "RX_MULT_EN";
3659 +static const char pszRX_MULT_CH[]        = "RX_MULT_CH";
3660 +static const char pszTX_PTYPE[]          = "TX_PTYPE";
3661 +static const char pszTX_PACE[]           = "TX_PACE";
3662 +static const char pszMII_EN[]            = "MII_EN";
3663 +static const char pszTX_FLOW_EN[]        = "TX_FLOW_EN";
3664 +static const char pszRX_FLOW_EN[]        = "RX_FLOW_EN";
3665 +static const char pszRX_MAXLEN[]         = "RX_MAXLEN";
3666 +static const char pszRX_FILTERLOWTHRESH[]   = "RX_FILTERLOWTHRESH";
3667 +static const char pszRX0_FLOWTHRESH[]   = "RX0_FLOWTHRESH";
3668 +static const char pszRX_UNICAST_SET[]    = "RX_UNICAST_SET";
3669 +static const char pszRX_UNICAST_CLEAR[]  = "RX_UNICAST_CLEAR";
3670 +static const char pszMdioConnect[]       = "MdioConnect";
3671 +static const char pszMacAddr[]           = "MacAddr";
3672 +static const char pszTick[]              = "Tick";
3673 +static const char pszRX_MULTICAST[]      = "RX_MULTICAST";
3674 +static const char pszRX_MULTI_ALL[]      = "RX_MULTI_ALL";
3675 +static const char pszRX_MULTI_SINGLE[]   = "RX_MULTI_SINGLE";
3676 +
3677 +static const char pszSet[]               = "Set";
3678 +static const char pszGet[]               = "Get";
3679 +static const char pszClear[]             = "Clear";
3680 +
3681 +
3682 +void *cpmac_hal_malloc_buffer(unsigned int size, void *MemBase, unsigned int MemRange,
3683 +                              HAL_DEVICE *HalDev, HAL_RECEIVEINFO *HalReceiveInfo,
3684 +                              OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
3685 +
3686 +void cpmac_hal_tear_down_complete(OS_DEVICE*, int, int);
3687 +int  cpmac_hal_control(OS_DEVICE *p_END_obj, const char *key,
3688 +                   const char *action, void *value);
3689 +int  cpmac_hal_receive(OS_DEVICE *p_END_obj, FRAGLIST *fragList,
3690 +               unsigned int FragCount, unsigned int pkt_len,
3691 +               HAL_RECEIVEINFO *halReceiveInfo,
3692 +               unsigned int mode);
3693 +int  cpmac_hal_send_complete(OS_SENDINFO*);
3694 +
3695 +void  cpmac_hal_isr(int irq, void *p_param, struct pt_regs *p_cb_param);
3696 +void  cpmac_handle_tasklet(unsigned long data);
3697 +
3698 +inline static int cpmac_ci_strcmp(const char *s1, const char *s2)
3699 +{
3700 +    while(*s1 && *s2)
3701 +    {
3702 +        if(tolower(*s1) != tolower(*s2))
3703 +            break;
3704 +        s1++;
3705 +        s2++;
3706 +    }
3707 +
3708 +    return(tolower(*s1) - tolower(*s2));
3709 +}
3710 +
3711 +#endif
3712 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.c linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.c
3713 --- linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.c  1970-01-01 01:00:00.000000000 +0100
3714 +++ linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.c  2005-07-12 02:48:42.044593000 +0200
3715 @@ -0,0 +1,492 @@
3716 +/******************************************************************************
3717 + * FILE PURPOSE:    CPMAC Net Driver HAL support Source
3718 + ******************************************************************************
3719 + * FILE NAME:       cpmacHalLx.c
3720 + *
3721 + * DESCRIPTION:     CPMAC Network Device Driver Source
3722 + *
3723 + * REVISION HISTORY:
3724 + *
3725 + * Date           Description                               Author
3726 + *-----------------------------------------------------------------------------
3727 + * 27 Nov 2002    Initial Creation                          Suraj S Iyer
3728 + * 09 Jun 2003    Updates for GA                            Suraj S Iyer
3729 + * 18 Dec 2003    Updated for 5.7                           Suraj S Iyer
3730 + *
3731 + * (C) Copyright 2003, Texas Instruments, Inc
3732 + *******************************************************************************/
3733 +#include <linux/kernel.h>
3734 +#include <linux/module.h>
3735 +#include <linux/init.h>
3736 +#include <linux/netdevice.h>
3737 +#include <linux/etherdevice.h>
3738 +#include <linux/delay.h>
3739 +#include <linux/spinlock.h>
3740 +#include <linux/proc_fs.h>
3741 +#include <asm/io.h>
3742 +#include <linux/string.h>
3743 +
3744 +#include "cpmacHalLx.h"
3745 +#include "cpmac.h"
3746 +
3747 +/* PSP config headers */
3748 +#include "psp_config_parse.h"
3749 +#include "psp_config_mgr.h"
3750 +
3751 +/* Probe Debug Section*/
3752 +
3753 +/* debug */
3754 +extern int cpmac_debug_mode;
3755 +#define dbgPrint if (cpmac_debug_mode) printk
3756 +#define errPrint printk
3757 +
3758 +char CpmacSignature[] = "Cpmac driver";
3759 +static unsigned long irq_flags = 0;
3760 +OS_SETUP *p_os_setup = NULL;
3761 +
3762 +extern int avalanche_request_intr_pacing(int, unsigned int, unsigned int);
3763 +extern int avalanche_free_intr_pacing(unsigned int blk_num);
3764 +
3765 +/*----------------------------------------------------------------------------
3766 + * Parameter extracting functionalities.
3767 + *--------------------------------------------------------------------------*/
3768 +static int os_find_parm_u_int(void *info_ptr, const char *param, unsigned int *val)
3769 +{
3770 +    int ret_val = 0;
3771 +
3772 +    if((ret_val = psp_config_get_param_uint(info_ptr, param, val)) == -1)
3773 +    {
3774 +        dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
3775 +        ret_val = -1;
3776 +    }
3777 +
3778 +    return(ret_val);
3779 +}
3780 +
3781 +static int os_find_parm_val(void *info_ptr, const char *param, void *val)
3782 +{
3783 +    int ret_val = 0;
3784 +
3785 +    if(psp_config_get_param_string(info_ptr, param, val) == -1)
3786 +    {
3787 +        dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
3788 +        ret_val = -1;
3789 +    }
3790 +
3791 +    return(ret_val);
3792 +}
3793 +
3794 +static int os_find_device(int unit, const char *find_name, void *device_info)
3795 +{
3796 +    int ret_val = 0;
3797 +
3798 +    if(psp_config_get((char *)find_name, unit, device_info) == -1)
3799 +    {
3800 +        dbgPrint("Error: could not locate the requested \"%s\" param.\n", find_name);
3801 +        ret_val = -1;
3802 +    }
3803 +
3804 +    return(ret_val);
3805 +}
3806 +
3807 +/*---------------------------------------------------------------------------
3808 + * Memory related OS abstraction.
3809 + *--------------------------------------------------------------------------*/
3810 +void os_free(void *mem_ptr)
3811 +{
3812 +    kfree(mem_ptr);
3813 +}
3814 +
3815 +void  os_free_buffer(OS_RECEIVEINFO *osReceiveInfo, void *mem_ptr)
3816 +{
3817 +    dev_kfree_skb_any(osReceiveInfo);
3818 +}
3819 +
3820 +void  os_free_dev(void *mem_ptr)
3821 +{
3822 +    kfree(mem_ptr);
3823 +}
3824 +
3825 +void os_free_dma_xfer(void *mem_ptr)
3826 +{
3827 +    kfree(mem_ptr);
3828 +}
3829 +
3830 +static void *os_malloc(unsigned int size)
3831 +{
3832 +    return(kmalloc(size, GFP_KERNEL));
3833 +}
3834 +
3835 +static void *os_malloc_dma_xfer(unsigned int size,
3836 +                                void         *mem_base,
3837 +                                unsigned int mem_range)
3838 +{
3839 +    return(kmalloc(size, GFP_KERNEL));
3840 +}
3841 +
3842 +static void *os_malloc_dev(unsigned int size)
3843 +{
3844 +    return(kmalloc(size, GFP_KERNEL));
3845 +}
3846 +
3847 +
3848 +/*----------------------------------------------------------------------------
3849 + * CRITICAL SECTION ENABLING/DISABLING.
3850 + *--------------------------------------------------------------------------*/
3851 +static void os_critical_on(void)
3852 +{
3853 +    save_and_cli(irq_flags);
3854 +}
3855 +
3856 +static void os_critical_off(void)
3857 +{
3858 +    restore_flags(irq_flags);
3859 +}
3860 +
3861 +/*----------------------------------------------------------------------------
3862 + * Cache related abstraction
3863 + *--------------------------------------------------------------------------*/
3864 +static void os_cache_invalidate(void *mem_ptr, int size)
3865 +{
3866 +    dma_cache_inv((unsigned long)mem_ptr, size);
3867 +}
3868 +
3869 +static void os_cache_writeback(void *mem_ptr, int size)
3870 +{
3871 +    dma_cache_wback_inv((unsigned long)mem_ptr, size);
3872 +}
3873 +
3874 +/*-----------------------------------------------------------------------------
3875 + * Support functions.
3876 + *---------------------------------------------------------------------------*/
3877 +
3878 +static void  hal_drv_unregister_isr(OS_DEVICE *p_dev, int intr)
3879 +{
3880 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_dev->priv;
3881 +    CPMAC_ISR_INFO_T     *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
3882 +    intr                                 = LNXINTNUM(intr);
3883 +
3884 +    free_irq(p_isr_cb_param->intr, p_isr_cb_param);
3885 +
3886 +    dbgPrint("cpmac_hal_unregister called for the intr %d for unit %x and isr_cb_param %x.\n",
3887 +             intr, p_cpmac_priv->instance_num, (unsigned int )&p_cpmac_priv->cpmac_isr);
3888 +}
3889 +
3890 +
3891 +static void hal_drv_register_isr(OS_DEVICE *p_dev,
3892 +                                 CPMAC_HAL_ISR_FUNC_T hal_isr, int intr)
3893 +{
3894 +    CPMAC_PRIVATE_INFO_T *p_cpmac_priv   = p_dev->priv;
3895 +    CPMAC_DRV_HAL_INFO_T *p_drv_hal      = p_cpmac_priv->drv_hal;
3896 +    CPMAC_ISR_INFO_T     *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
3897 +    intr                                 = LNXINTNUM(intr);
3898 +
3899 +    dbgPrint("osRegister called for the intr %d for device %x and p_isr_cb_param %x.\n",
3900 +             intr, (bit32u)p_dev, (bit32u)p_isr_cb_param);
3901 +
3902 +    p_isr_cb_param->owner       = p_drv_hal;
3903 +    p_isr_cb_param->hal_isr     = hal_isr;
3904 +    p_isr_cb_param->intr        = intr;
3905 +
3906 +    tasklet_init(&p_isr_cb_param->tasklet, cpmac_handle_tasklet, (unsigned long)p_isr_cb_param);
3907 +    dbgPrint("Success in registering irq %d for Cpmac unit# %d.\n", intr, p_cpmac_priv->instance_num);
3908 +}
3909 +
3910 +/*---------------------------------------------------------------------------
3911 + * FUNCTIONS called by the CPMAC Net Device.
3912 + *-------------------------------------------------------------------------*/
3913 +static int load_os_funcs(OS_FUNCTIONS *os_func)
3914 +{
3915 +    dbgPrint("os_init_module: Start\n");
3916 +    if( os_func == 0 )
3917 +    {
3918 +        return(sizeof(OS_FUNCTIONS));
3919 +    }
3920 +
3921 +    os_func->Control                    = cpmac_hal_control;
3922 +    os_func->CriticalOn                 = os_critical_on;
3923 +    os_func->CriticalOff                = os_critical_off;
3924 +    os_func->DataCacheHitInvalidate     = os_cache_invalidate;
3925 +    os_func->DataCacheHitWriteback      = os_cache_writeback;
3926 +    os_func->DeviceFindInfo     = os_find_device;
3927 +    os_func->DeviceFindParmUint = os_find_parm_u_int;
3928 +    os_func->DeviceFindParmValue= os_find_parm_val;
3929 +    os_func->Free               = os_free;
3930 +    os_func->FreeRxBuffer       = os_free_buffer;
3931 +    os_func->FreeDev            = os_free_dev;
3932 +    os_func->FreeDmaXfer        = os_free_dma_xfer;
3933 +    os_func->IsrRegister        = hal_drv_register_isr;
3934 +    os_func->IsrUnRegister      = hal_drv_unregister_isr;
3935 +    os_func->Malloc             = os_malloc;
3936 +    os_func->MallocDev          = os_malloc_dev;
3937 +    os_func->MallocDmaXfer      = os_malloc_dma_xfer;
3938 +    os_func->MallocRxBuffer     = cpmac_hal_malloc_buffer;
3939 +    os_func->Memset             = memset;
3940 +    os_func->Printf             = printk;
3941 +    os_func->Receive            = cpmac_hal_receive;
3942 +    os_func->SendComplete       = cpmac_hal_send_complete;
3943 +    os_func->Strcmpi            = cpmac_ci_strcmp;
3944 +    os_func->TeardownComplete   = cpmac_hal_tear_down_complete;
3945 +    os_func->Strstr             = strstr;
3946 +    os_func->Strtoul            = simple_strtol;
3947 +    os_func->Sprintf            = sprintf;
3948 +    os_func->Strlen             = strlen;
3949 +
3950 +    dbgPrint("os_init_module: Leave\n");
3951 +
3952 +    return(0);
3953 +}
3954 +
3955 +
3956 +int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
3957 +{
3958 +    HAL_DEVICE       *p_hal_dev    = p_drv_hal->hal_dev;
3959 +    HAL_FUNCTIONS    *p_hal_funcs  = p_drv_hal->hal_funcs;
3960 +
3961 +    return(p_hal_funcs->Init(p_hal_dev));
3962 +}
3963 +
3964 +int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
3965 +{
3966 +    HAL_DEVICE       *p_hal_dev    = p_drv_hal->hal_dev;
3967 +    HAL_FUNCTIONS    *p_hal_funcs  = p_drv_hal->hal_funcs;
3968 +
3969 +    int              ret_val       = p_hal_funcs->Shutdown(p_hal_dev);
3970 +
3971 +#if 0
3972 +    if(ret_val == 0)
3973 +        kfree(p_hal_funcs);
3974 +    else
3975 +        ret_val = -1;
3976 +#endif
3977 +
3978 +    kfree(p_drv_hal->os_funcs);
3979 +
3980 +    return (ret_val);
3981 +}
3982 +
3983 +int cpmac_drv_tx_setup(HAL_FUNCTIONS        *p_hal_funcs,
3984 +                       HAL_DEVICE           *p_hal_dev,
3985 +                       CPMAC_TX_CHAN_INFO_T *p_tx_chan_info)
3986 +{
3987 +    int ret_val = 0;
3988 +    int count   = 0;
3989 +    CHANNEL_INFO chan_info;
3990 +
3991 +    /* Let's setup the TX Channels. */
3992 +    for(count=0; count < p_tx_chan_info->cfg_chan; count++)
3993 +    {
3994 +        chan_info.Channel        = count;
3995 +        chan_info.Direction      = DIRECTION_TX;
3996 +        chan_info.TxNumBuffers   = p_tx_chan_info->chan[count].num_BD;
3997 +        chan_info.TxServiceMax   = p_tx_chan_info->chan[count].service_max;
3998 +        chan_info.TxNumQueues    = 0;
3999 +
4000 +        if((ret_val = p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info,
4001 +                                                NULL)) != 0)
4002 +        {
4003 +            errPrint("Error in opening channel %d for TX.\n", count);
4004 +            ret_val = -1;
4005 +            break;
4006 +        }
4007 +
4008 +        p_tx_chan_info->opened_chan++;
4009 +    }
4010 +
4011 +    return(ret_val);
4012 +}
4013 +
4014 +int cpmac_drv_rx_setup(HAL_FUNCTIONS         *p_hal_funcs,
4015 +                       HAL_DEVICE            *p_hal_dev,
4016 +                       CPMAC_RX_CHAN_INFO_T  *p_rx_chan_info)
4017 +{
4018 +    int ret_val = 0;
4019 +    CHANNEL_INFO chan_info;
4020 +
4021 +    chan_info.Channel       = 0;
4022 +    chan_info.Direction     = DIRECTION_RX;
4023 +    chan_info.RxBufSize     = p_rx_chan_info->chan[0].buffer_size;
4024 +    chan_info.RxBufferOffset= p_rx_chan_info->chan[0].buffer_offset;
4025 +    chan_info.RxNumBuffers  = p_rx_chan_info->chan[0].num_BD;
4026 +    chan_info.RxServiceMax  = p_rx_chan_info->chan[0].service_max;
4027 +
4028 +    if(p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info, p_rx_chan_info) != 0)
4029 +    {
4030 +        errPrint("Error in opening channel %d for RX.\n", 0);
4031 +        ret_val = -1;
4032 +    }
4033 +
4034 +    return(ret_val);
4035 +}
4036 +
4037 +int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *p_drv_hal,
4038 +                    CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4039 +                    CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,
4040 +                    unsigned int         flags)
4041 +{
4042 +    int ret_val = 0;
4043 +    HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
4044 +    HAL_DEVICE    *p_hal_dev   = p_drv_hal->hal_dev;
4045 +
4046 +    dbgPrint("It is in cpmac_drv_start for %x.\n", (unsigned int)p_drv_hal);
4047 +
4048 +    if(flags & CHAN_SETUP)
4049 +    {
4050 +        if(cpmac_drv_tx_setup(p_hal_funcs, p_hal_dev,
4051 +                  p_tx_chan_info)!=0)
4052 +        {
4053 +            errPrint("Failed to set up tx channel(s).\n");
4054 +            ret_val = -1;
4055 +        }
4056 +        else if(cpmac_drv_rx_setup(p_hal_funcs, p_hal_dev,
4057 +                                   p_rx_chan_info)!=0)
4058 +        {
4059 +            errPrint("Failed to set up rx channel.\n");
4060 +            ret_val = -1;
4061 +        }
4062 +        else
4063 +        {
4064 +            ret_val = 0;
4065 +        }
4066 +    }
4067 +
4068 +    /* Error in setting up the Channels, quit. */
4069 +    if((ret_val == 0) && (ret_val = p_hal_funcs->Open(p_hal_dev)) != 0)
4070 +    {
4071 +        errPrint("failed to open the HAL!!!.\n");
4072 +        ret_val = -1;
4073 +    }
4074 +
4075 +    return (ret_val);
4076 +} /* cpmac_drv_start */
4077 +
4078 +
4079 +
4080 +int cpmac_drv_tx_teardown(HAL_FUNCTIONS        *p_hal_funcs,
4081 +                          HAL_DEVICE           *p_hal_dev,
4082 +                          CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4083 +                          unsigned int         flags)
4084 +{
4085 +    int ret_val = 0;
4086 +    int count   = 0;
4087 +
4088 +    /* Let's setup the TX Channels. */
4089 +    for(;  p_tx_chan_info->opened_chan > 0;
4090 +        p_tx_chan_info->opened_chan--, count++)
4091 +    {
4092 +        if(p_hal_funcs->ChannelTeardown(p_hal_dev, count, flags) != 0)
4093 +        {
4094 +            errPrint("Error in tearing down channel %d for TX.\n", count);
4095 +            ret_val = -1;
4096 +            break;
4097 +        }
4098 +    }
4099 +
4100 +    return(ret_val);
4101 +}
4102 +
4103 +
4104 +int cpmac_drv_rx_teardown(HAL_FUNCTIONS *p_hal_funcs,
4105 +                  HAL_DEVICE    *p_hal_dev,
4106 +              unsigned int  flags)
4107 +{
4108 +    int ret_val = 0;
4109 +
4110 +    if(p_hal_funcs->ChannelTeardown(p_hal_dev, 0, flags) != 0)
4111 +    {
4112 +        errPrint("Error in tearing down channel %d for RX.\n", 0);
4113 +        ret_val = -1;
4114 +    }
4115 +
4116 +    return(ret_val);
4117 +}
4118 +
4119 +int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T    *p_drv_hal,
4120 +                   CPMAC_TX_CHAN_INFO_T    *p_tx_chan_info,
4121 +                   CPMAC_RX_CHAN_INFO_T    *p_rx_chan_info,
4122 +                   unsigned int flags)
4123 +{
4124 +    HAL_DEVICE       *p_hal_dev    = p_drv_hal->hal_dev;
4125 +    HAL_FUNCTIONS    *p_hal_funcs  = p_drv_hal->hal_funcs;
4126 +    int ret_val                    = 0;
4127 +
4128 +    if(flags & CHAN_TEARDOWN)
4129 +    {
4130 +        unsigned int chan_flags = 0;
4131 +
4132 +        if(flags & FREE_BUFFER) chan_flags |= 0x4; /* full tear down */
4133 +        if(flags & BLOCKING)    chan_flags |= 0x8; /* blocking call  */
4134 +
4135 +        dbgPrint("The teardown flags are %d.\n", flags);
4136 +        dbgPrint("The teardown chan flags are %d.\n", chan_flags);
4137 +
4138 +        if(cpmac_drv_tx_teardown(p_hal_funcs, p_hal_dev,
4139 +                                 p_tx_chan_info, chan_flags | 0x1) != 0)
4140 +        {
4141 +            ret_val = -1;
4142 +            errPrint("The tx channel teardown failed.\n");
4143 +        }
4144 +        else if(cpmac_drv_rx_teardown(p_hal_funcs, p_hal_dev, chan_flags | 0x2) != 0)
4145 +        {
4146 +            ret_val = -1;
4147 +            errPrint("The rx channel teardown failed.\n");
4148 +        }
4149 +        else
4150 +        {
4151 +            ;
4152 +        }
4153 +    }
4154 +
4155 +    if(ret_val == 0)
4156 +    {
4157 +        int close_flags = 1;
4158 +
4159 +        if(flags & FREE_BUFFER)  close_flags = 2;
4160 +//        if(flags & COMPLETE)     close_flags = 3;
4161 +
4162 +        if(p_hal_funcs->Close(p_hal_dev, close_flags) != 0)
4163 +        {
4164 +            ret_val = -1;
4165 +        }
4166 +    }
4167 +
4168 +    return(ret_val);
4169 +}
4170 +
4171 +int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T *p_drv_hal, OS_DEVICE *p_os_dev, int inst)
4172 +{
4173 +    int ret_val = -1;
4174 +    int hal_func_size;
4175 +
4176 +    dbgPrint("Entering the CpmacInitModule for the inst %d \n", inst);
4177 +
4178 +    if((p_drv_hal->os_funcs = kmalloc(sizeof(OS_FUNCTIONS), GFP_KERNEL)) == NULL)
4179 +    {
4180 +        errPrint("Failed to allocate memory for OS_FUNCTIONS.\n");
4181 +    }
4182 +    else if(load_os_funcs(p_drv_hal->os_funcs) != 0)
4183 +    {
4184 +        errPrint("Failed to load OS funcs.\n");
4185 +        os_free(p_drv_hal->os_funcs);
4186 +    }
4187 +    else if(halCpmacInitModule(&p_drv_hal->hal_dev, p_os_dev,
4188 +                               &p_drv_hal->hal_funcs, p_drv_hal->os_funcs,
4189 +                               sizeof(*p_drv_hal->os_funcs),
4190 +                               &hal_func_size, inst) != 0)
4191 +    {
4192 +        errPrint("halCpmacInitModule failed for inst %d \n", inst);
4193 +        os_free(p_drv_hal->os_funcs);
4194 +    }
4195 +    else if(p_drv_hal->hal_funcs->Probe(p_drv_hal->hal_dev) != 0)
4196 +    {
4197 +        errPrint("halCpmacProbe failed for inst %d \n", inst);
4198 +        os_free(p_drv_hal->os_funcs);
4199 +    }
4200 +    else
4201 +    {
4202 +        /* every thing went well. */
4203 +        ret_val = 0;
4204 +    }
4205 +
4206 +    return (ret_val);
4207 +}
4208 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.h linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.h
4209 --- linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.h  1970-01-01 01:00:00.000000000 +0100
4210 +++ linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.h  2005-07-12 02:48:42.044593000 +0200
4211 @@ -0,0 +1,51 @@
4212 +/******************************************************************************
4213 + * FILE PURPOSE:    CPMAC Linux Device Driver HAL support Header
4214 + ******************************************************************************
4215 + * FILE NAME:       cpmacHalVx.h
4216 + *
4217 + * DESCRIPTION:     CPMAC Linux Device Driver Header
4218 + *
4219 + * REVISION HISTORY:
4220 + *
4221 + * Date           Description                               Author
4222 + *-----------------------------------------------------------------------------
4223 + * 27 Nov 2002    Initial Creation                          Suraj S Iyer
4224 + * 09 Jun 2003    Updates for GA                            Suraj S Iyer
4225 + *
4226 + * (C) Copyright 2002, Texas Instruments, Inc
4227 + *******************************************************************************/
4228 +
4229 +#ifndef __CPMAC_HAL_LX_H
4230 +#define __CPMAC_HAL_LX_H
4231 +
4232 +
4233 +typedef struct net_device         OS_DEVICE;
4234 +typedef struct sk_buff            OS_RECEIVEINFO;
4235 +typedef struct sk_buff            OS_SENDINFO;
4236 +
4237 +#ifdef DEBUG
4238 +typedef void                      HAL_RECEIVEINFO;
4239 +typedef void                      HAL_DEVICE;
4240 +typedef void                      OS_SETUP;
4241 +#endif
4242 +
4243 +#define OS_SETUP   void
4244 +#define HAL_DEVICE void
4245 +#define HAL_RECEIVEINFO void
4246 +
4247 +#define _CPHAL_CPMAC
4248 +
4249 +#include "cpswhal_cpmac.h"
4250 +#include "cpmac.h"
4251 +
4252 +int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *, CPMAC_TX_CHAN_INFO_T*,
4253 +                    CPMAC_RX_CHAN_INFO_T *, unsigned int);
4254 +int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *);
4255 +int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T*);
4256 +int cpmac_drv_close(CPMAC_DRV_HAL_INFO_T*);
4257 +int cpmac_drv_open(CPMAC_DRV_HAL_INFO_T*);
4258 +int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T*, OS_DEVICE*, int);
4259 +int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T *p_drv_hal,CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4260 +                   CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,unsigned int flags);
4261 +
4262 +#endif
4263 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac_reg.h linux.dev/drivers/net/avalanche_cpmac/cpmac_reg.h
4264 --- linux.old/drivers/net/avalanche_cpmac/cpmac_reg.h   1970-01-01 01:00:00.000000000 +0100
4265 +++ linux.dev/drivers/net/avalanche_cpmac/cpmac_reg.h   2005-07-12 02:48:42.045593000 +0200
4266 @@ -0,0 +1,406 @@
4267 +/****************************************************************************
4268 +        TNETD73xx Software Support
4269 +        Copyright(c) 2000, Texas Instruments Incorporated. All Rights Reserved.
4270 +
4271 +        FILE: cpmac_reg.h   Register definitions for the CPMAC module
4272 +
4273 +         DESCRIPTION:
4274 +                This include file contains register definitions for the
4275 +                CPMAC module.
4276 +
4277 +         HISTORY:
4278 +              15Nov00 BEGR Original version written
4279 +              30May02 MICK Added bits for Int Vector
4280 +              19Sep02 MICK Added INT_ACK per Channel
4281 +              08Nov02 GDUN Updated to use base
4282 +              12Nov02 MICK Incorporated into CPHAL
4283 +*****************************************************************************/
4284 +#ifndef _INC_CPMAC_REG
4285 +#define _INC_CPMAC_REG
4286 +
4287 +#ifndef MEM_PTR
4288 +#define MEM_PTR volatile bit32u *
4289 +#endif
4290 +
4291 +/***************************************************************************
4292 + *
4293 + *         C P M A C  M E M O R Y  M A P
4294 + *
4295 + **************************************************************************/
4296 +
4297 +#define pCPMAC_TX_IDVER(base)                 ((MEM_PTR)(base+0x000))
4298 +#define  CPMAC_TX_IDVER(base)                 (*pCPMAC_TX_IDVER(base))
4299 +#define pCPMAC_TX_CONTROL(base)               ((MEM_PTR)(base+0x004))
4300 +#define  CPMAC_TX_CONTROL(base)               (*pCPMAC_TX_CONTROL(base))
4301 +#define pCPMAC_TX_TEARDOWN(base)              ((MEM_PTR)(base+0x008))
4302 +#define  CPMAC_TX_TEARDOWN(base)              (*pCPMAC_TX_TEARDOWN(base))
4303 +#define pCPMAC_RX_IDVER(base)                 ((MEM_PTR)(base+0x010))
4304 +#define  CPMAC_RX_IDVER(base)                 (*pCPMAC_RX_IDVER(base))
4305 +#define pCPMAC_RX_CONTROL(base)               ((MEM_PTR)(base+0x014))
4306 +#define  CPMAC_RX_CONTROL(base)               (*pCPMAC_RX_CONTROL(base))
4307 +#define pCPMAC_RX_TEARDOWN(base)              ((MEM_PTR)(base+0x018))
4308 +#define  CPMAC_RX_TEARDOWN(base)              (*pCPMAC_RX_TEARDOWN(base))
4309 +#define pCPMAC_RX_MBP_ENABLE(base)            ((MEM_PTR)(base+0x100))
4310 +#define  CPMAC_RX_MBP_ENABLE(base)            (*pCPMAC_RX_MBP_ENABLE(base))
4311 +#define pCPMAC_RX_UNICAST_SET(base)           ((MEM_PTR)(base+0x104))
4312 +#define  CPMAC_RX_UNICAST_SET(base)           (*pCPMAC_RX_UNICAST_SET(base))
4313 +#define pCPMAC_RX_UNICAST_CLEAR(base)         ((MEM_PTR)(base+0x108))
4314 +#define  CPMAC_RX_UNICAST_CLEAR(base)         (*pCPMAC_RX_UNICAST_CLEAR(base))
4315 +#define pCPMAC_RX_MAXLEN(base)                ((MEM_PTR)(base+0x10C))
4316 +#define  CPMAC_RX_MAXLEN(base)                (*pCPMAC_RX_MAXLEN(base))
4317 +#define pCPMAC_RX_BUFFER_OFFSET(base)         ((MEM_PTR)(base+0x110))
4318 +#define  CPMAC_RX_BUFFER_OFFSET(base)         (*pCPMAC_RX_BUFFER_OFFSET(base))
4319 +#define pCPMAC_RX_FILTERLOWTHRESH(base)       ((MEM_PTR)(base+0x114))
4320 +#define  CPMAC_RX_FILTERLOWTHRESH(base)       (*pCPMAC_RX_FILTERLOWTHRESH(base))
4321 +#define pCPMAC_RX0_FLOWTHRESH(base)           ((MEM_PTR)(base+0x120))
4322 +#define  CPMAC_RX0_FLOWTHRESH(base)           (*pCPMAC_RX0_FLOWTHRESH(base))
4323 +#define pCPMAC_RX1_FLOWTHRESH(base)           ((MEM_PTR)(base+0x124))
4324 +#define  CPMAC_RX1_FLOWTHRESH(base)           (*pCPMAC_RX1_FLOWTHRESH(base))
4325 +#define pCPMAC_RX2_FLOWTHRESH(base)           ((MEM_PTR)(base+0x128))
4326 +#define  CPMAC_RX2_FLOWTHRESH(base)           (*pCPMAC_RX2_FLOWTHRESH(base))
4327 +#define pCPMAC_RX3_FLOWTHRESH(base)           ((MEM_PTR)(base+0x12C))
4328 +#define  CPMAC_RX3_FLOWTHRESH(base)           (*pCPMAC_RX3_FLOWTHRESH(base))
4329 +#define pCPMAC_RX4_FLOWTHRESH(base)           ((MEM_PTR)(base+0x130))
4330 +#define  CPMAC_RX4_FLOWTHRESH(base)           (*pCPMAC_RX4_FLOWTHRESH(base))
4331 +#define pCPMAC_RX5_FLOWTHRESH(base)           ((MEM_PTR)(base+0x134))
4332 +#define  CPMAC_RX5_FLOWTHRESH(base)           (*pCPMAC_RX5_FLOWTHRESH(base))
4333 +#define pCPMAC_RX6_FLOWTHRESH(base)           ((MEM_PTR)(base+0x138))
4334 +#define  CPMAC_RX6_FLOWTHRESH(base)           (*pCPMAC_RX6_FLOWTHRESH(base))
4335 +#define pCPMAC_RX7_FLOWTHRESH(base)           ((MEM_PTR)(base+0x13C))
4336 +#define  CPMAC_RX7_FLOWTHRESH(base)           (*pCPMAC_RX7_FLOWTHRESH(base))
4337 +#define pCPMAC_RX0_FREEBUFFER(base)           ((MEM_PTR)(base+0x140))
4338 +#define  CPMAC_RX0_FREEBUFFER(base)           (*pCPMAC_RX0_FREEBUFFER(base))
4339 +#define pCPMAC_RX1_FREEBUFFER(base)           ((MEM_PTR)(base+0x144))
4340 +#define  CPMAC_RX1_FREEBUFFER(base)           (*pCPMAC_RX1_FREEBUFFER(base))
4341 +#define pCPMAC_RX2_FREEBUFFER(base)           ((MEM_PTR)(base+0x148))
4342 +#define  CPMAC_RX2_FREEBUFFER(base)           (*pCPMAC_RX2_FREEBUFFER(base))
4343 +#define pCPMAC_RX3_FREEBUFFER(base)           ((MEM_PTR)(base+0x14C))
4344 +#define  CPMAC_RX3_FREEBUFFER(base)           (*pCPMAC_RX3_FREEBUFFER(base))
4345 +#define pCPMAC_RX4_FREEBUFFER(base)           ((MEM_PTR)(base+0x150))
4346 +#define  CPMAC_RX4_FREEBUFFER(base)           (*pCPMAC_RX4_FREEBUFFER(base))
4347 +#define pCPMAC_RX5_FREEBUFFER(base)           ((MEM_PTR)(base+0x154))
4348 +#define  CPMAC_RX5_FREEBUFFER(base)           (*pCPMAC_RX5_FREEBUFFER(base))
4349 +#define pCPMAC_RX6_FREEBUFFER(base)           ((MEM_PTR)(base+0x158))
4350 +#define  CPMAC_RX6_FREEBUFFER(base)           (*pCPMAC_RX6_FREEBUFFER(base))
4351 +#define pCPMAC_RX7_FREEBUFFER(base)           ((MEM_PTR)(base+0x15C))
4352 +#define  CPMAC_RX7_FREEBUFFER(base)           (*pCPMAC_RX7_FREEBUFFER(base))
4353 +#define pCPMAC_MACCONTROL(base)               ((MEM_PTR)(base+0x160))
4354 +#define  CPMAC_MACCONTROL(base)               (*pCPMAC_MACCONTROL(base))
4355 +#define pCPMAC_MACSTATUS(base)                ((MEM_PTR)(base+0x164))
4356 +#define  CPMAC_MACSTATUS(base)                (*pCPMAC_MACSTATUS(base))
4357 +#define pCPMAC_EMCONTROL(base)                ((MEM_PTR)(base+0x168))
4358 +#define  CPMAC_EMCONTROL(base)                (*pCPMAC_EMCONTROL(base))
4359 +#define pCPMAC_TX_INTSTAT_RAW(base)           ((MEM_PTR)(base+0x170))
4360 +#define  CPMAC_TX_INTSTAT_RAW(base)           (*pCPMAC_TX_INTSTAT_RAW(base))
4361 +#define pCPMAC_TX_INTSTAT_MASKED(base)        ((MEM_PTR)(base+0x174))
4362 +#define  CPMAC_TX_INTSTAT_MASKED(base)        (*pCPMAC_TX_INTSTAT_MASKED(base))
4363 +#define pCPMAC_TX_INTMASK_SET(base)           ((MEM_PTR)(base+0x178))
4364 +#define  CPMAC_TX_INTMASK_SET(base)           (*pCPMAC_TX_INTMASK_SET(base))
4365 +#define pCPMAC_TX_INTMASK_CLEAR(base)         ((MEM_PTR)(base+0x17C))
4366 +#define  CPMAC_TX_INTMASK_CLEAR(base)         (*pCPMAC_TX_INTMASK_CLEAR(base))
4367 +#define pCPMAC_MAC_IN_VECTOR(base)            ((MEM_PTR)(base+0x180))
4368 +#define  CPMAC_MAC_IN_VECTOR(base)            (*pCPMAC_MAC_IN_VECTOR(base))
4369 +#define pCPMAC_MAC_EOI_VECTOR(base)           ((MEM_PTR)(base+0x184))
4370 +#define  CPMAC_MAC_EOI_VECTOR(base)           (*pCPMAC_MAC_EOI_VECTOR(base))
4371 +#define pCPMAC_RX_INTSTAT_RAW(base)           ((MEM_PTR)(base+0x190))
4372 +#define  CPMAC_RX_INTSTAT_RAW(base)           (*pCPMAC_RX_INTSTAT_RAW(base))
4373 +#define pCPMAC_RX_INTSTAT_MASKED(base)        ((MEM_PTR)(base+0x194))
4374 +#define  CPMAC_RX_INTSTAT_MASKED(base)        (*pCPMAC_RX_INTSTAT_MASKED(base))
4375 +#define pCPMAC_RX_INTMASK_SET(base)           ((MEM_PTR)(base+0x198))
4376 +#define  CPMAC_RX_INTMASK_SET(base)           (*pCPMAC_RX_INTMASK_SET(base))
4377 +#define pCPMAC_RX_INTMASK_CLEAR(base)         ((MEM_PTR)(base+0x19C))
4378 +#define  CPMAC_RX_INTMASK_CLEAR(base)         (*pCPMAC_RX_INTMASK_CLEAR(base))
4379 +#define pCPMAC_MAC_INTSTAT_RAW(base)          ((MEM_PTR)(base+0x1A0))
4380 +#define  CPMAC_MAC_INTSTAT_RAW(base)          (*pCPMAC_MAC_INTSTAT_RAW(base))
4381 +#define pCPMAC_MAC_INTSTAT_MASKED(base)       ((MEM_PTR)(base+0x1A4))
4382 +#define  CPMAC_MAC_INTSTAT_MASKED(base)       (*pCPMAC_MAC_INTSTAT_MASKED(base))
4383 +#define pCPMAC_MAC_INTMASK_SET(base)          ((MEM_PTR)(base+0x1A8))
4384 +#define  CPMAC_MAC_INTMASK_SET(base)          (*pCPMAC_MAC_INTMASK_SET(base))
4385 +#define pCPMAC_MAC_INTMASK_CLEAR(base)        ((MEM_PTR)(base+0x1AC))
4386 +#define  CPMAC_MAC_INTMASK_CLEAR(base)        (*pCPMAC_MAC_INTMASK_CLEAR(base))
4387 +#define pCPMAC_MACADDRLO_0(base)              ((MEM_PTR)(base+0x1B0))
4388 +#define  CPMAC_MACADDRLO_0(base)              (*pCPMAC_MACADDRLO_0(base))
4389 +#define pCPMAC_MACADDRLO_1(base)              ((MEM_PTR)(base+0x1B4))
4390 +#define  CPMAC_MACADDRLO_1(base)              (*pCPMAC_MACADDRLO_1(base))
4391 +#define pCPMAC_MACADDRLO_2(base)              ((MEM_PTR)(base+0x1B8))
4392 +#define  CPMAC_MACADDRLO_2(base)              (*pCPMAC_MACADDRLO_2(base))
4393 +#define pCPMAC_MACADDRLO_3(base)              ((MEM_PTR)(base+0x1BC))
4394 +#define  CPMAC_MACADDRLO_3(base)              (*pCPMAC_MACADDRLO_3(base))
4395 +#define pCPMAC_MACADDRLO_4(base)              ((MEM_PTR)(base+0x1C0))
4396 +#define  CPMAC_MACADDRLO_4(base)              (*pCPMAC_MACADDRLO_4(base))
4397 +#define pCPMAC_MACADDRLO_5(base)              ((MEM_PTR)(base+0x1C4))
4398 +#define  CPMAC_MACADDRLO_5(base)              (*pCPMAC_MACADDRLO_5(base))
4399 +#define pCPMAC_MACADDRLO_6(base)              ((MEM_PTR)(base+0x1C8))
4400 +#define  CPMAC_MACADDRLO_6(base)              (*pCPMAC_MACADDRLO_6(base))
4401 +#define pCPMAC_MACADDRLO_7(base)              ((MEM_PTR)(base+0x1CC))
4402 +#define  CPMAC_MACADDRLO_7(base)              (*pCPMAC_MACADDRLO_7(base))
4403 +#define pCPMAC_MACADDRMID(base)               ((MEM_PTR)(base+0x1D0))
4404 +#define  CPMAC_MACADDRMID(base)               (*pCPMAC_MACADDRMID(base))
4405 +#define pCPMAC_MACADDRHI(base)                ((MEM_PTR)(base+0x1D4))
4406 +#define  CPMAC_MACADDRHI(base)                (*pCPMAC_MACADDRHI(base))
4407 +#define pCPMAC_MACHASH1(base)                 ((MEM_PTR)(base+0x1D8))
4408 +#define  CPMAC_MACHASH1(base)                 (*pCPMAC_MACHASH1(base))
4409 +#define pCPMAC_MACHASH2(base)                 ((MEM_PTR)(base+0x1DC))
4410 +#define  CPMAC_MACHASH2(base)                 (*pCPMAC_MACHASH2(base))
4411 +#define pCPMAC_BOFFTEST(base)                 ((MEM_PTR)(base+0x1E0))
4412 +#define  CPMAC_BOFFTEST(base)                 (*pCPMAC_BOFFTEST(base))
4413 +#define pCPMAC_PACTEST(base)                  ((MEM_PTR)(base+0x1E4))
4414 +#define  CPMAC_PACTEST(base)                  (*pCPMAC_PACTEST(base))
4415 +#define pCPMAC_RXPAUSE(base)                  ((MEM_PTR)(base+0x1E8))
4416 +#define  CPMAC_RXPAUSE(base)                  (*pCPMAC_RXPAUSE(base))
4417 +#define pCPMAC_TXPAUSE(base)                  ((MEM_PTR)(base+0x1EC))
4418 +#define  CPMAC_TXPAUSE(base)                  (*pCPMAC_TXPAUSE(base))
4419 +/* STATISTICS */
4420 +#define pCPMAC_RXGOODFRAMES(base)             ((MEM_PTR)(base+0x200))
4421 +#define  CPMAC_RXGOODFRAMES(base)             (*pCPMAC_RXGOODFRAMES(base))
4422 +#define pCPMAC_RXBROADCASTFRAMES(base)        ((MEM_PTR)(base+0x204))
4423 +#define  CPMAC_RXBROADCASTFRAMES(base)        (*pCPMAC_RXBROADCASTFRAMES(base))
4424 +#define pCPMAC_RXMULTICASTFRAMES(base)        ((MEM_PTR)(base+0x208))
4425 +#define  CPMAC_RXMULTICASTFRAMES(base)        (*pCPMAC_RXMULTICASTFRAMES(base))
4426 +#define pCPMAC_RXPAUSEFRAMES(base)            ((MEM_PTR)(base+0x20C))
4427 +#define   CPMAC_RXPAUSEFRAMES(base)           (*pCPMAC_RXPAUSEFRAMES(base))
4428 +#define pCPMAC_RXCRCERRORS(base)              ((MEM_PTR)(base+0x210))
4429 +#define   CPMAC_RXCRCERRORS(base)             (*pCPMAC_RXCRCERRORS(base))
4430 +#define pCPMAC_RXALIGNCODEERRORS(base)        ((MEM_PTR)(base+0x214))
4431 +#define   CPMAC_RXALIGNCODEERRORS(base)       (*pCPMAC_RXALIGNCODEERRORS(base))
4432 +#define pCPMAC_RXOVERSIZEDFRAMES(base)        ((MEM_PTR)(base+0x218))
4433 +#define   CPMAC_RXOVERSIZEDFRAMES(base)       (*pCPMAC_RXOVERSIZEDFRAMES(base))
4434 +#define pCPMAC_RXJABBERFRAMES(base)           ((MEM_PTR)(base+0x21C))
4435 +#define  CPMAC_RXJABBERFRAMES(base)           (*pCPMAC_RXJABBERFRAMES(base))
4436 +#define pCPMAC_RXUNDERSIZEDFRAMES(base)       ((MEM_PTR)(base+0x220))
4437 +#define  CPMAC_RXUNDERSIZEDFRAMES(base)       (*pCPMAC_RXUNDERSIZEDFRAMES(base))
4438 +#define pCPMAC_RXFRAGMENTS(base)              ((MEM_PTR)(base+0x224))
4439 +#define  CPMAC_RXFRAGMENTS(base)              (*pCPMAC_RXFRAGMENTS(base))
4440 +#define pCPMAC_RXFILTEREDFRAMES(base)         ((MEM_PTR)(base+0x228))
4441 +#define  CPMAC_RXFILTEREDFRAMES(base)         (*pCPMAC_RXFILTEREDFRAMES(base))
4442 +#define pCPMAC_RXQOSFILTEREDFRAMES(base)      ((MEM_PTR)(base+0x22C))
4443 +#define  CPMAC_RXQOSFILTEREDFRAMES(base)      (*pCPMAC_RXQOSFILTEREDFRAMES(base))
4444 +#define pCPMAC_RXOCTETS(base)                 ((MEM_PTR)(base+0x230))
4445 +#define  CPMAC_RXOCTETS(base)                 (*pCPMAC_RXOCTETS(base))
4446 +#define pCPMAC_TXGOODFRAMES(base)             ((MEM_PTR)(base+0x234))
4447 +#define  CPMAC_TXGOODFRAMES(base)             (*pCPMAC_TXGOODFRAMES(base))
4448 +#define pCPMAC_TXBROADCASTFRAMES(base)        ((MEM_PTR)(base+0x238))
4449 +#define  CPMAC_TXBROADCASTFRAMES(base)        (*pCPMAC_TXBROADCASTFRAMES(base))
4450 +#define pCPMAC_TXMULTICASTFRAMES(base)        ((MEM_PTR)(base+0x23C))
4451 +#define  CPMAC_TXMULTICASTFRAMES(base)        (*pCPMAC_TXMULTICASTFRAMES(base))
4452 +#define pCPMAC_TXPAUSEFRAMES(base)            ((MEM_PTR)(base+0x240))
4453 +#define  CPMAC_TXPAUSEFRAMES(base)            (*pCPMAC_TXPAUSEFRAMES(base))
4454 +#define pCPMAC_TXDEFERREDFRAMES(base)         ((MEM_PTR)(base+0x244))
4455 +#define  CPMAC_TXDEFERREDFRAMES(base)         (*pCPMAC_TXDEFERREDFRAMES(base))
4456 +#define pCPMAC_TXCOLLISIONFRAMES(base)        ((MEM_PTR)(base+0x248))
4457 +#define  CPMAC_TXCOLLISIONFRAMES(base)        (*pCPMAC_TXCOLLISIONFRAMES(base))
4458 +#define pCPMAC_TXSINGLECOLLFRAMES(base)       ((MEM_PTR)(base+0x24C))
4459 +#define  CPMAC_TXSINGLECOLLFRAMES(base)       (*pCPMAC_TXSINGLECOLLFRAMES(base))
4460 +#define pCPMAC_TXMULTCOLLFRAMES(base)         ((MEM_PTR)(base+0x250))
4461 +#define  CPMAC_TXMULTCOLLFRAMES(base)         (*pCPMAC_TXMULTCOLLFRAMES(base))
4462 +#define pCPMAC_TXEXCESSIVECOLLISIONS(base)    ((MEM_PTR)(base+0x254))
4463 +#define  CPMAC_TXEXCESSIVECOLLISIONS(base)    (*pCPMAC_TXEXCESSIVECOLLISIONS(base))
4464 +#define pCPMAC_TXLATECOLLISIONS(base)         ((MEM_PTR)(base+0x258))
4465 +#define  CPMAC_TXLATECOLLISIONS(base)         (*pCPMAC_TXLATECOLLISIONS(base))
4466 +#define pCPMAC_TXUNDERRUN(base)               ((MEM_PTR)(base+0x25C))
4467 +#define  CPMAC_TXUNDERRUN(base)               (*pCPMAC_TXUNDERRUN(base))
4468 +#define pCPMAC_TXCARRIERSENSEERRORS(base)     ((MEM_PTR)(base+0x260))
4469 +#define  CPMAC_TXCARRIERSENSEERRORS(base)     (*pCPMAC_TXCARRIERSENSEERRORS(base))
4470 +#define pCPMAC_TXOCTETS(base)                 ((MEM_PTR)(base+0x264))
4471 +#define  CPMAC_TXOCTETS(base)                 (*pCPMAC_TXOCTETS(base))
4472 +#define pCPMAC_64OCTETFRAMES(base)            ((MEM_PTR)(base+0x268))
4473 +#define  CPMAC_64OCTETFRAMES(base)            (*pCPMAC_64OCTETFRAMES(base))
4474 +#define pCPMAC_65T127OCTETFRAMES(base)        ((MEM_PTR)(base+0x26C))
4475 +#define  CPMAC_65T127OCTETFRAMES(base)        (*pCPMAC_65T127OCTETFRAMES(base))
4476 +#define pCPMAC_128T255OCTETFRAMES(base)       ((MEM_PTR)(base+0x270))
4477 +#define  CPMAC_128T255OCTETFRAMES(base)       (*pCPMAC_128T255OCTETFRAMES(base))
4478 +#define pCPMAC_256T511OCTETFRAMES(base)       ((MEM_PTR)(base+0x274))
4479 +#define  CPMAC_256T511OCTETFRAMES(base)       (*pCPMAC_256T511OCTETFRAMES(base))
4480 +#define pCPMAC_512T1023OCTETFRAMES(base)      ((MEM_PTR)(base+0x278))
4481 +#define  CPMAC_512T1023OCTETFRAMES(base)      (*pCPMAC_512T1023OCTETFRAMES(base))
4482 +#define pCPMAC_1024TUPOCTETFRAMES(base)       ((MEM_PTR)(base+0x27C))
4483 +#define  CPMAC_1024TUPOCTETFRAMES(base)       (*pCPMAC_1024TUPOCTETFRAMES(base))
4484 +#define pCPMAC_NETOCTETS(base)                ((MEM_PTR)(base+0x280))
4485 +#define  CPMAC_NETOCTETS(base)                (*pCPMAC_NETOCTETS(base))
4486 +#define pCPMAC_RXSOFOVERRUNS(base)            ((MEM_PTR)(base+0x284))
4487 +#define  CPMAC_RXSOFOVERRUNS(base)            (*pCPMAC_RXSOFOVERRUNS(base))
4488 +#define pCPMAC_RXMOFOVERRUNS(base)            ((MEM_PTR)(base+0x288))
4489 +#define  CPMAC_RXMOFOVERRUNS(base)            (*pCPMAC_RXMOFOVERRUNS(base))
4490 +#define pCPMAC_RXDMAOVERRUNS(base)            ((MEM_PTR)(base+0x28C))
4491 +#define  CPMAC_RXDMAOVERRUNS(base)            (*pCPMAC_RXDMAOVERRUNS(base))
4492 +
4493 +#define  CPMAC_TX_HDP(base,ch)                (*(MEM_PTR)(base+0x600+(4*ch)))
4494 +#define pCPMAC_TX0_HDP(base)                  ((MEM_PTR)(base+0x600))
4495 +#define  CPMAC_TX0_HDP(base)                  (*pCPMAC_TX0_HDP(base))
4496 +#define pCPMAC_TX1_HDP(base)                  ((MEM_PTR)(base+0x604))
4497 +#define  CPMAC_TX1_HDP(base)                  (*pCPMAC_TX1_HDP(base))
4498 +#define pCPMAC_TX2_HDP(base)                  ((MEM_PTR)(base+0x608))
4499 +#define  CPMAC_TX2_HDP(base)                  (*pCPMAC_TX2_HDP(base))
4500 +#define pCPMAC_TX3_HDP(base)                  ((MEM_PTR)(base+0x60C))
4501 +#define  CPMAC_TX3_HDP(base)                  (*pCPMAC_TX3_HDP(base))
4502 +#define pCPMAC_TX4_HDP(base)                  ((MEM_PTR)(base+0x610))
4503 +#define  CPMAC_TX4_HDP(base)                  (*pCPMAC_TX4_HDP(base))
4504 +#define pCPMAC_TX5_HDP(base)                  ((MEM_PTR)(base+0x614))
4505 +#define  CPMAC_TX5_HDP(base)                  (*pCPMAC_TX5_HDP(base))
4506 +#define pCPMAC_TX6_HDP(base)                  ((MEM_PTR)(base+0x618))
4507 +#define  CPMAC_TX6_HDP(base)                  (*pCPMAC_TX6_HDP(base))
4508 +#define pCPMAC_TX7_HDP(base)                  ((MEM_PTR)(base+0x61C))
4509 +#define  CPMAC_TX7_HDP(base)                  (*pCPMAC_TX7_HDP(base))
4510 +#define  CPMAC_RX_HDP(base,ch)                (*(MEM_PTR)(base+0x620+(4*ch)))
4511 +#define pCPMAC_RX0_HDP(base)                  ((MEM_PTR)(base+0x620))
4512 +#define  CPMAC_RX0_HDP(base)                  (*pCPMAC_RX0_HDP(base))
4513 +#define pCPMAC_RX1_HDP(base)                  ((MEM_PTR)(base+0x624))
4514 +#define  CPMAC_RX1_HDP(base)                  (*pCPMAC_RX1_HDP(base))
4515 +#define pCPMAC_RX2_HDP(base)                  ((MEM_PTR)(base+0x628))
4516 +#define  CPMAC_RX2_HDP(base)                  (*pCPMAC_RX2_HDP(base))
4517 +#define pCPMAC_RX3_HDP(base)                  ((MEM_PTR)(base+0x62C))
4518 +#define  CPMAC_RX3_HDP(base)                  (*pCPMAC_RX3_HDP(base))
4519 +#define pCPMAC_RX4_HDP(base)                  ((MEM_PTR)(base+0x630))
4520 +#define  CPMAC_RX4_HDP(base)                  (*pCPMAC_RX4_HDP(base))
4521 +#define pCPMAC_RX5_HDP(base)                  ((MEM_PTR)(base+0x634))
4522 +#define  CPMAC_RX5_HDP(base)                  (*pCPMAC_RX5_HDP(base))
4523 +#define pCPMAC_RX6_HDP(base)                  ((MEM_PTR)(base+0x638))
4524 +#define  CPMAC_RX6_HDP(base)                  (*pCPMAC_RX6_HDP(base))
4525 +#define pCPMAC_RX7_HDP(base)                  ((MEM_PTR)(base+0x63C))
4526 +#define  CPMAC_RX7_HDP(base)                  (*pCPMAC_RX7_HDP(base))
4527 +
4528 +
4529 +#define CPMAC_TX_INT_ACK(base,ch)             (*(MEM_PTR)(base+0x640+(4*ch)))
4530 +
4531 +#define pCPMAC_TX0_INT_ACK(base)              ((MEM_PTR)(base+0x640))
4532 +#define  CPMAC_TX0_INT_ACK(base)              (*pCPMAC_TX0_INT_ACK(base))
4533 +#define pCPMAC_TX1_INT_ACK(base)              ((MEM_PTR)(base+0x644))
4534 +#define  CPMAC_TX1_INT_ACK(base)              (*pCPMAC_TX1_INT_ACK(base))
4535 +#define pCPMAC_TX2_INT_ACK(base)              ((MEM_PTR)(base+0x648))
4536 +#define  CPMAC_TX2_INT_ACK(base)              (*pCPMAC_TX2_INT_ACK(base))
4537 +#define pCPMAC_TX3_INT_ACK(base)              ((MEM_PTR)(base+0x64C))
4538 +#define  CPMAC_TX3_INT_ACK(base)              (*pCPMAC_TX3_INT_ACK(base))
4539 +#define pCPMAC_TX4_INT_ACK(base)              ((MEM_PTR)(base+0x650))
4540 +#define  CPMAC_TX4_INT_ACK(base)              (*pCPMAC_TX4_INT_ACK(base))
4541 +#define pCPMAC_TX5_INT_ACK(base)              ((MEM_PTR)(base+0x654))
4542 +#define  CPMAC_TX5_INT_ACK(base)              (*pCPMAC_TX5_INT_ACK(base))
4543 +#define pCPMAC_TX6_INT_ACK(base)              ((MEM_PTR)(base+0x658))
4544 +#define  CPMAC_TX6_INT_ACK(base)              (*pCPMAC_TX6_INT_ACK(base))
4545 +#define pCPMAC_TX7_INT_ACK(base)              ((MEM_PTR)(base+0x65C))
4546 +#define  CPMAC_TX7_INT_ACK(base)              (*pCPMAC_TX7_INT_ACK(base))
4547 +#define CPMAC_RX_INT_ACK(base,ch)             (*(MEM_PTR)(base+0x660+(4*ch)))
4548 +
4549 +#define pCPMAC_RX0_INT_ACK(base)              ((MEM_PTR)(base+0x660))
4550 +#define  CPMAC_RX0_INT_ACK(base)              (*pCPMAC_RX0_INT_ACK(base))
4551 +#define pCPMAC_RX1_INT_ACK(base)              ((MEM_PTR)(base+0x664))
4552 +#define  CPMAC_RX1_INT_ACK(base)              (*pCPMAC_RX1_INT_ACK(base))
4553 +#define pCPMAC_RX2_INT_ACK(base)              ((MEM_PTR)(base+0x668))
4554 +#define  CPMAC_RX2_INT_ACK(base)              (*pCPMAC_RX2_INT_ACK(base))
4555 +#define pCPMAC_RX3_INT_ACK(base)              ((MEM_PTR)(base+0x66C))
4556 +#define  CPMAC_RX3_INT_ACK(base)              (*pCPMAC_RX3_INT_ACK(base))
4557 +#define pCPMAC_RX4_INT_ACK(base)              ((MEM_PTR)(base+0x670))
4558 +#define  CPMAC_RX4_INT_ACK(base)              (*pCPMAC_RX4_INT_ACK(base))
4559 +#define pCPMAC_RX5_INT_ACK(base)              ((MEM_PTR)(base+0x674))
4560 +#define  CPMAC_RX5_INT_ACK(base)              (*pCPMAC_RX5_INT_ACK(base))
4561 +#define pCPMAC_RX6_INT_ACK(base)              ((MEM_PTR)(base+0x678))
4562 +#define  CPMAC_RX6_INT_ACK(base)              (*pCPMAC_RX6_INT_ACK(base))
4563 +#define pCPMAC_RX7_INT_ACK(base)              ((MEM_PTR)(base+0x67C))
4564 +#define  CPMAC_RX7_INT_ACK(base)              (*pCPMAC_RX7_INT_ACK(base))
4565 +
4566 +/****************************************************************************/
4567 +/*                                                                          */
4568 +/*         R E G I S T E R  B I T  D E F I N I T I O N S                    */
4569 +/*                                                                          */
4570 +/****************************************************************************/
4571 +
4572 +/* TX_CONTROL */
4573 +
4574 +#define TX_EN               (1 << 0)
4575 +
4576 +/* RX_CONTROL */
4577 +
4578 +#define RX_EN               (1 << 0)
4579 +
4580 +/* RX_MBP_ENABLE */
4581 +
4582 +#define RX_PASS_CRC         (1 << 30)
4583 +#define RX_QOS_EN           (1 << 29)
4584 +#define RX_NO_CHAIN         (1 << 28)
4585 +
4586 +#define RX_CMF_EN           (1 << 24)
4587 +#define RX_CSF_EN           (1 << 23)
4588 +#define RX_CEF_EN           (1 << 22)
4589 +#define RX_CAF_EN           (1 << 21)
4590 +
4591 +#define RX_PROM_CH(n)       (n << 16)
4592 +#define RX_PROM_CH_MASK     RX_PROM_CH(7)
4593 +#define RX_PROM_CH_7        RX_PROM_CH(7)
4594 +#define RX_PROM_CH_6        RX_PROM_CH(6)
4595 +#define RX_PROM_CH_5        RX_PROM_CH(5)
4596 +#define RX_PROM_CH_4        RX_PROM_CH(4)
4597 +#define RX_PROM_CH_3        RX_PROM_CH(3)
4598 +#define RX_PROM_CH_2        RX_PROM_CH(2)
4599 +#define RX_PROM_CH_1        RX_PROM_CH(1)
4600 +#define RX_PROM_CH_0        RX_PROM_CH(0)
4601 +
4602 +#define RX_BROAD_EN         (1 << 13)
4603 +
4604 +#define RX_BROAD_CH(n)       (n <<  8)
4605 +#define RX_BROAD_CH_MASK     RX_BROAD_CH(7)
4606 +#define RX_BROAD_CH_7        RX_BROAD_CH(7)
4607 +#define RX_BROAD_CH_6        RX_BROAD_CH(6)
4608 +#define RX_BROAD_CH_5        RX_BROAD_CH(5)
4609 +#define RX_BROAD_CH_4        RX_BROAD_CH(4)
4610 +#define RX_BROAD_CH_3        RX_BROAD_CH(3)
4611 +#define RX_BROAD_CH_2        RX_BROAD_CH(2)
4612 +#define RX_BROAD_CH_1        RX_BROAD_CH(1)
4613 +#define RX_BROAD_CH_0        RX_BROAD_CH(0)
4614 +
4615 +#define RX_MULT_EN          (1 <<  5)
4616 +
4617 +#define RX_MULT_CH(n)       (n << 0)
4618 +#define RX_MULT_CH_MASK     RX_MULT_CH(7)
4619 +#define RX_MULT_CH_7        RX_MULT_CH(7)
4620 +#define RX_MULT_CH_6        RX_MULT_CH(6)
4621 +#define RX_MULT_CH_5        RX_MULT_CH(5)
4622 +#define RX_MULT_CH_4        RX_MULT_CH(4)
4623 +#define RX_MULT_CH_3        RX_MULT_CH(3)
4624 +#define RX_MULT_CH_2        RX_MULT_CH(2)
4625 +#define RX_MULT_CH_1        RX_MULT_CH(1)
4626 +#define RX_MULT_CH_0        RX_MULT_CH(0)
4627 +
4628 +
4629 +
4630 +/* RX_UNICAST_SET */
4631 +
4632 +#define RX_CH7_EN        (1 <<  7)
4633 +#define RX_CH6_EN        (1 <<  6)
4634 +#define RX_CH5_EN        (1 <<  5)
4635 +#define RX_CH4_EN        (1 <<  4)
4636 +#define RX_CH3_EN        (1 <<  3)
4637 +#define RX_CH2_EN        (1 <<  2)
4638 +#define RX_CH1_EN        (1 <<  1)
4639 +#define RX_CH0_EN        (1 <<  0)
4640 +
4641 +
4642 +
4643 +/*  MAC control */
4644 +#define TX_PTYPE         (1 << 9)
4645 +#define TX_PACE          (1 << 6)
4646 +#define MII_EN           (1 << 5)
4647 +#define TX_FLOW_EN       (1 << 4)
4648 +#define RX_FLOW_EN       (1 << 3)
4649 +#define MTEST            (1 << 2)
4650 +#define CTRL_LOOPBACK    (1 << 1)
4651 +#define FULLDUPLEX       (1 << 0)
4652 +
4653 +
4654 +/* IntVec definitions  */
4655 +#define MAC_IN_VECTOR_STATUS_INT   (1 << 19)
4656 +#define MAC_IN_VECTOR_HOST_INT     (1 << 18)
4657 +#define MAC_IN_VECTOR_RX_INT_OR    (1 << 17)
4658 +#define MAC_IN_VECTOR_TX_INT_OR    (1 << 16)
4659 +#define MAC_IN_VECTOR_RX_INT_VEC   (7 << 8)
4660 +#define MAC_IN_VECTOR_TX_INT_VEC   (7)
4661 +
4662 +
4663 +/*  MacStatus */
4664 +
4665 +#define TX_HOST_ERR_CODE         (0xF << 20)
4666 +#define TX_ERR_CH                (0x7 << 16)
4667 +#define RX_HOST_ERR_CODE         (0xF << 12)
4668 +#define RX_ERR_CH                (0x7 <<  8)
4669 +#define RX_QOS_ACT               (1 << 2)
4670 +#define RX_FLOW_ACT              (1 << 1)
4671 +#define TX_FLOW_ACT              (1 << 0)
4672 +#endif _INC_CPMAC_REG
4673 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmdio.c linux.dev/drivers/net/avalanche_cpmac/cpmdio.c
4674 --- linux.old/drivers/net/avalanche_cpmac/cpmdio.c      1970-01-01 01:00:00.000000000 +0100
4675 +++ linux.dev/drivers/net/avalanche_cpmac/cpmdio.c      2005-07-12 02:48:42.046593000 +0200
4676 @@ -0,0 +1,960 @@
4677 +/***************************************************************************
4678 +**  TNETD53xx Software Support
4679 +**  Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
4680 +**
4681 +**  FILE: cpmdio.c
4682 +**
4683 +**  DESCRIPTION:
4684 +**   MDIO Polling State Machine API. Functions will enable mii-Phy
4685 +**   negotiation.
4686 +**
4687 +**  HISTORY:
4688 +**    01Jan01 Denis, Bill      Original
4689 +**      27Mar02 Michael Hanrahan (modified from emacmdio.c)
4690 +**      07May02 Michael Hanrahan replaced clockwait for code delay
4691 +**      10Jul02 Michael Hanrahan more debug, if fallback link is selected
4692 +*****************************************************************************/
4693 +#define __CPHAL_CPMDIO
4694 +
4695 +#include "mdio_reg.h"
4696 +
4697 +#ifdef _CPHAL_CPMAC
4698 +#define mdioPrintf PhyDev->HalDev->OsFunc->Printf
4699 +#else
4700 +#define mdioPrintf printf
4701 +#endif
4702 +
4703 +typedef struct _phy_device
4704 +{
4705 +   bit32u miibase;
4706 +   bit32u inst;
4707 +   bit32u PhyState;
4708 +   bit32u MdixMask;
4709 +   bit32u PhyMask;
4710 +   bit32u MLinkMask;
4711 +   bit32u PhyMode;
4712 +#ifdef _CPHAL_CPMAC
4713 +   HAL_DEVICE *HalDev;
4714 +#endif
4715 +} _PHY_DEVICE;
4716 +
4717 +static void   _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait);
4718 +static void   _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev);
4719 +static void   _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data);
4720 +static bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr);
4721 +static void   _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data);
4722 +
4723 +static void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
4724 +static void _mdioPhyTimeOut(PHY_DEVICE *PhyDev);
4725 +static void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
4726 +
4727 +static void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p);
4728 +static void _mdioDumpState(PHY_DEVICE *PhyDev);
4729 +
4730 +/* Auto Mdix */
4731 +static void _mdioMdixDelay(PHY_DEVICE *PhyDev);
4732 +static int  _mdioMdixSupported(PHY_DEVICE *PhyDev);
4733 +
4734 +static void _MdioDefaultState  (PHY_DEVICE *PhyDev);
4735 +static void _MdioFindingState  (PHY_DEVICE *PhyDev);
4736 +static void _MdioFoundState    (PHY_DEVICE *PhyDev);
4737 +static void _MdioInitState     (PHY_DEVICE *PhyDev);
4738 +static void _MdioLinkedState   (PHY_DEVICE *PhyDev);
4739 +static void _MdioLinkWaitState (PHY_DEVICE *PhyDev);
4740 +static void _MdioLoopbackState (PHY_DEVICE *PhyDev);
4741 +static void _MdioNwayStartState(PHY_DEVICE *PhyDev);
4742 +static void _MdioNwayWaitState (PHY_DEVICE *PhyDev);
4743 +
4744 +
4745 +
4746 +#ifndef TRUE
4747 +#define TRUE (1==1)
4748 +#endif
4749 +
4750 +#ifndef FALSE
4751 +#define FALSE (1==2)
4752 +#endif
4753 +
4754 +#define PHY_NOT_FOUND  0xFFFF    /*  Used in Phy Detection */
4755 +
4756 +/*PhyState breakout                                                          */
4757 +
4758 +#define PHY_DEV_OFFSET      (0)
4759 +#define PHY_DEV_SIZE        (5)        /*  5 Bits used */
4760 +#define PHY_DEV_MASK        (0x1f<<PHY_DEV_OFFSET)
4761 +
4762 +#define PHY_STATE_OFFSET    (PHY_DEV_SIZE+PHY_DEV_OFFSET)
4763 +#define PHY_STATE_SIZE      (5)        /* 10 Bits used */
4764 +#define PHY_STATE_MASK      (0x1f<<PHY_STATE_OFFSET)
4765 +  #define INIT       (1<<PHY_STATE_OFFSET)
4766 +  #define FINDING    (2<<PHY_STATE_OFFSET)
4767 +  #define FOUND      (3<<PHY_STATE_OFFSET)
4768 +  #define NWAY_START (4<<PHY_STATE_OFFSET)
4769 +  #define NWAY_WAIT  (5<<PHY_STATE_OFFSET)
4770 +  #define LINK_WAIT  (6<<PHY_STATE_OFFSET)
4771 +  #define LINKED     (7<<PHY_STATE_OFFSET)
4772 +  #define LOOPBACK   (8<<PHY_STATE_OFFSET)
4773 +
4774 +#define PHY_SPEED_OFFSET    (PHY_STATE_OFFSET+PHY_STATE_SIZE)
4775 +#define PHY_SPEED_SIZE      (1)     /* 11 Bits used */
4776 +#define PHY_SPEED_MASK      (1<<PHY_SPEED_OFFSET)
4777 +
4778 +#define PHY_DUPLEX_OFFSET   (PHY_SPEED_OFFSET+PHY_SPEED_SIZE)
4779 +#define PHY_DUPLEX_SIZE     (1)     /* 12 Bits used */
4780 +#define PHY_DUPLEX_MASK     (1<<PHY_DUPLEX_OFFSET)
4781 +
4782 +#define PHY_TIM_OFFSET      (PHY_DUPLEX_OFFSET+PHY_DUPLEX_SIZE)
4783 +#define PHY_TIM_SIZE        (10)    /* 22 Bits used */
4784 +#define PHY_TIM_MASK        (0x3ff<<PHY_TIM_OFFSET)
4785 +  #define PHY_FIND_TO (  2<<PHY_TIM_OFFSET)
4786 +  #define PHY_RECK_TO (200<<PHY_TIM_OFFSET)
4787 +  #define PHY_LINK_TO (500<<PHY_TIM_OFFSET)
4788 +  #define PHY_NWST_TO (500<<PHY_TIM_OFFSET)
4789 +  #define PHY_NWDN_TO (800<<PHY_TIM_OFFSET)
4790 +  #define PHY_MDIX_TO (274<<PHY_TIM_OFFSET) /* 2.74 Seconds <--Spec and empirical */
4791 +
4792 +#define PHY_SMODE_OFFSET    (PHY_TIM_OFFSET+PHY_TIM_SIZE)
4793 +#define PHY_SMODE_SIZE      (5)     /* 27 Bits used */
4794 +#define PHY_SMODE_MASK      (0x1f<<PHY_SMODE_OFFSET)
4795 +  #define SMODE_AUTO   (0x10<<PHY_SMODE_OFFSET)
4796 +  #define SMODE_FD100  (0x08<<PHY_SMODE_OFFSET)
4797 +  #define SMODE_HD100  (0x04<<PHY_SMODE_OFFSET)
4798 +  #define SMODE_FD10   (0x02<<PHY_SMODE_OFFSET)
4799 +  #define SMODE_HD10   (0x01<<PHY_SMODE_OFFSET)
4800 +  #define SMODE_ALL    (0x1f<<PHY_SMODE_OFFSET)
4801 +
4802 +#define PHY_CHNG_OFFSET    (PHY_SMODE_OFFSET+PHY_SMODE_SIZE)
4803 +#define PHY_CHNG_SIZE      (1)     /* 28 Bits used */
4804 +#define PHY_CHNG_MASK      (1<<PHY_CHNG_OFFSET)
4805 +  #define PHY_CHANGE (1<<PHY_CHNG_OFFSET)
4806 +
4807 +#define PHY_TIMEDOUT_OFFSET    (PHY_CHNG_OFFSET+PHY_CHNG_SIZE)
4808 +#define PHY_TIMEDOUT_SIZE      (1)     /*  29 Bits used */
4809 +#define PHY_TIMEDOUT_MASK      (1<<PHY_TIMEDOUT_OFFSET)
4810 +  #define PHY_MDIX_SWITCH  (1<<PHY_TIMEDOUT_OFFSET)
4811 +
4812 +#define PHY_MDIX_OFFSET    (PHY_TIMEDOUT_OFFSET+PHY_TIMEDOUT_SIZE)
4813 +#define PHY_MDIX_SIZE      (1)     /*  30 Bits used */
4814 +#define PHY_MDIX_MASK      (1<<PHY_MDIX_OFFSET)
4815 +  #define PHY_MDIX     (1<<PHY_MDIX_OFFSET)
4816 +
4817 +static char *lstate[]={"NULL","INIT","FINDING","FOUND","NWAY_START","NWAY_WAIT","LINK_WAIT","LINKED", "LOOPBACK"};
4818 +static int cpMacDebug;
4819 +
4820 +/*  Local MDIO Register Macros    */
4821 +
4822 +#define myMDIO_ALIVE           MDIO_ALIVE     (PhyDev->miibase)
4823 +#define myMDIO_CONTROL         MDIO_CONTROL   (PhyDev->miibase)
4824 +#define myMDIO_LINK            MDIO_LINK      (PhyDev->miibase)
4825 +#define myMDIO_LINKINT         MDIO_LINKINT   (PhyDev->miibase)
4826 +#define myMDIO_USERACCESS      MDIO_USERACCESS(PhyDev->miibase, PhyDev->inst)
4827 +#define myMDIO_USERPHYSEL      MDIO_USERPHYSEL(PhyDev->miibase, PhyDev->inst)
4828 +#define myMDIO_VER             MDIO_VER       (PhyDev->miibase)
4829 +
4830 +#ifndef VOLATILE32
4831 +#define VOLATILE32(addr) (*((volatile bit32u *)(addr)))
4832 +#endif
4833 +
4834 +/************************************
4835 +***
4836 +*** Delays at least ClockWait cylces
4837 +*** before returning
4838 +***
4839 +**************************************/
4840 +void _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait)
4841 +  {
4842 +#ifdef _CPHAL_CPMAC                                                  /*+RC3.02*/
4843 +  HAL_DEVICE *HalDev = PhyDev->HalDev;                               /*+RC3.02*/
4844 +  osfuncSleep((int*)&ClockWait);                                     /*+RC3.02*/
4845 +#else                                                                /*+RC3.02*/
4846 +  volatile bit32u i=0;
4847 +  while(ClockWait--)
4848 +    {
4849 +    i |= myMDIO_LINK; /*  MDIO register access to burn cycles */
4850 +    }
4851 +#endif
4852 +  }
4853 +
4854 +void _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev)
4855 +  {
4856 +  while((myMDIO_USERACCESS & MDIO_USERACCESS_GO)!=0)
4857 +    {
4858 +    }
4859 +  }
4860 +
4861 +void _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data)
4862 +  {
4863 +  bit32u  control;
4864 +
4865 +  control =  MDIO_USERACCESS_GO |
4866 +             (method) |
4867 +             (((regadr) << 21) & MDIO_USERACCESS_REGADR) |
4868 +             (((phyadr) << 16) & MDIO_USERACCESS_PHYADR) |
4869 +             ((data) & MDIO_USERACCESS_DATA);
4870 +
4871 +  myMDIO_USERACCESS = control;
4872 +  }
4873 +
4874 +
4875 +
4876 +/************************************
4877 +***
4878 +*** Waits for MDIO_USERACCESS to be ready and reads data
4879 +*** If 'WaitForData' set, waits for read to complete and returns Data,
4880 +*** otherwise returns 0
4881 +*** Note: 'data' is 16 bits but we use 32 bits
4882 +***        to be consistent with rest of the code.
4883 +***
4884 +**************************************/
4885 +bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr)
4886 +  {
4887 +
4888 +  _mdioWaitForAccessComplete(PhyDev);  /* Wait until UserAccess ready */
4889 +  _mdioUserAccess(PhyDev, MDIO_USERACCESS_READ, regadr, phyadr, 0);
4890 +  _mdioWaitForAccessComplete(PhyDev);  /* Wait for Read to complete */
4891 +
4892 +  return(myMDIO_USERACCESS & MDIO_USERACCESS_DATA);
4893 +  }
4894 +
4895 +
4896 +/************************************
4897 +***
4898 +*** Waits for MDIO_USERACCESS to be ready and writes data
4899 +***
4900 +**************************************/
4901 +void _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data)
4902 +  {
4903 +  _mdioWaitForAccessComplete(PhyDev);  /* Wait until UserAccess ready */
4904 +  _mdioUserAccess(PhyDev, MDIO_USERACCESS_WRITE, regadr, phyadr, data);
4905 +  }
4906 +
4907 +void _mdioDumpPhyDetailed(PHY_DEVICE *PhyDev)
4908 +{
4909 +  bit32u *PhyState = &PhyDev->PhyState;
4910 +  bit32u  PhyNum;
4911 +  int     RegData;
4912 +
4913 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
4914 +
4915 +  RegData = _mdioUserAccessRead(PhyDev, 0, PhyNum);
4916 +  mdioPrintf("PhyControl: %04X, Lookback=%s, Speed=%s, Duplex=%s\n",
4917 +    RegData,
4918 +    RegData&PHY_LOOP?"On":"Off",
4919 +    RegData&PHY_100?"100":"10",
4920 +    RegData&PHY_FD?"Full":"Half");
4921 +  RegData = _mdioUserAccessRead(PhyDev, 1, PhyNum);
4922 +  mdioPrintf("PhyStatus: %04X, AutoNeg=%s, Link=%s\n",
4923 +    RegData,
4924 +    RegData&NWAY_COMPLETE?"Complete":"NotComplete",
4925 +    RegData&PHY_LINKED?"Up":"Down");
4926 +  RegData = _mdioUserAccessRead(PhyDev, 4, PhyNum);
4927 +  mdioPrintf("PhyMyCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
4928 +    RegData,
4929 +    RegData&NWAY_FD100?"Yes":"No",
4930 +    RegData&NWAY_HD100?"Yes":"No",
4931 +    RegData&NWAY_FD10?"Yes":"No",
4932 +    RegData&NWAY_HD10?"Yes":"No");
4933 +
4934 +  RegData = _mdioUserAccessRead(PhyDev, 5, PhyNum);
4935 +  mdioPrintf("PhyPartnerCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
4936 +    RegData,
4937 +    RegData&NWAY_FD100?"Yes":"No",
4938 +    RegData&NWAY_HD100?"Yes":"No",
4939 +    RegData&NWAY_FD10?"Yes":"No",
4940 +    RegData&NWAY_HD10?"Yes":"No");
4941 +}
4942 +void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p)
4943 +  {
4944 +  bit32u j,n,PhyAcks;
4945 +  bit32u PhyRegAddr;
4946 +  bit32u phy_num;
4947 +  bit32u PhyMask  = PhyDev->PhyMask;
4948 +
4949 +  PhyAcks=myMDIO_ALIVE;
4950 +  PhyAcks&=PhyMask;   /* Only interested in 'our' Phys */
4951 +
4952 +  for(phy_num=0,j=1;phy_num<32;phy_num++,j<<=1)
4953 +    {
4954 +    if (PhyAcks&j)
4955 +      {
4956 +      mdioPrintf("%2d%s:",phy_num,(phy_num==p)?">":" ");
4957 +      for(PhyRegAddr=0;PhyRegAddr<6;PhyRegAddr++)
4958 +        {
4959 +        n = _mdioUserAccessRead(PhyDev, PhyRegAddr, phy_num);
4960 +        mdioPrintf(" %04x",n&0x0ffff);
4961 +        }
4962 +      mdioPrintf("\n");
4963 +      }
4964 +    }
4965 +  _mdioDumpPhyDetailed(PhyDev);
4966 +  }
4967 +
4968 +void _mdioDumpState(PHY_DEVICE *PhyDev)
4969 +  {
4970 +  bit32u state    = PhyDev->PhyState;
4971 +
4972 +  if (!cpMacDebug) return;
4973 +
4974 +  mdioPrintf("Phy: %d, ",(state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
4975 +  mdioPrintf("State: %d/%s, ",(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET,lstate[(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET]);
4976 +  mdioPrintf("Speed: %d, ",(state&PHY_SPEED_MASK)>>PHY_SPEED_OFFSET);
4977 +  mdioPrintf("Dup: %d, ",(state&PHY_DUPLEX_MASK)>>PHY_DUPLEX_OFFSET);
4978 +  mdioPrintf("Tim: %d, ",(state&PHY_TIM_MASK)>>PHY_TIM_OFFSET);
4979 +  mdioPrintf("SMode: %d, ",(state&PHY_SMODE_MASK)>>PHY_SMODE_OFFSET);
4980 +  mdioPrintf("Chng: %d",(state&PHY_CHNG_MASK)>>PHY_CHNG_OFFSET);
4981 +  mdioPrintf("\n");
4982 +
4983 +  if (((state&PHY_STATE_MASK)!=FINDING)&&((state&PHY_STATE_MASK)!=INIT))
4984 +    _mdioDumpPhy(PhyDev, (state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
4985 +  }
4986 +
4987 +
4988 +void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
4989 +  {
4990 +  bit16u PhyControlReg;
4991 +
4992 +  _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_RESET);
4993 +  if (cpMacDebug)
4994 +    mdioPrintf("cpMacMdioPhYReset(%d)\n",PhyNum);
4995 +
4996 +  /* Read control register until Phy Reset is complete */
4997 +  do
4998 +   {
4999 +    PhyControlReg = _mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
5000 +   }
5001 +   while (PhyControlReg & PHY_RESET); /* Wait for Reset to clear */
5002 +  }
5003 +
5004 +void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
5005 +  {
5006 +  _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_ISOLATE|PHY_PDOWN);
5007 +
5008 +  if (cpMacDebug)
5009 +    mdioPrintf("cpMacMdioDisablePhy(%d)\n",PhyNum);
5010 +
5011 +  }
5012 +
5013 +void _MdioInitState(PHY_DEVICE *PhyDev)
5014 +  {
5015 +  bit32u *PhyState = &PhyDev->PhyState;
5016 +  bit32u CurrentState;
5017 +
5018 +  CurrentState=*PhyState;
5019 +  CurrentState=(CurrentState&~PHY_TIM_MASK)|(PHY_FIND_TO);
5020 +  CurrentState=(CurrentState&~PHY_STATE_MASK)|(FINDING);
5021 +  CurrentState=(CurrentState&~PHY_SPEED_MASK);
5022 +  CurrentState=(CurrentState&~PHY_DUPLEX_MASK);
5023 +  CurrentState|=PHY_CHANGE;
5024 +
5025 +  *PhyState=CurrentState;
5026 +
5027 +  }
5028 +
5029 +void _MdioFindingState(PHY_DEVICE *PhyDev)
5030 +  {
5031 +  bit32u *PhyState = &PhyDev->PhyState;
5032 +  bit32u  PhyMask  = PhyDev->PhyMask;
5033 +  bit32u  PhyNum,i,j,PhyAcks;
5034 +
5035 +
5036 +  PhyNum=PHY_NOT_FOUND;
5037 +
5038 +  if (*PhyState&PHY_TIM_MASK)
5039 +    {
5040 +    *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5041 +    }
5042 +   else
5043 +    {
5044 +    PhyAcks=myMDIO_ALIVE;
5045 +    PhyAcks&=PhyMask;   /* Only interested in 'our' Phys */
5046 +
5047 +    for(i=0,j=1;(i<32)&&((j&PhyAcks)==0);i++,j<<=1);
5048 +
5049 +    if ((PhyAcks)&&(i<32)) PhyNum=i;
5050 +    if (PhyNum!=PHY_NOT_FOUND)
5051 +      {
5052 +      /*  Phy Found! */
5053 +      *PhyState=(*PhyState&~PHY_DEV_MASK)|((PhyNum&PHY_DEV_MASK)<<PHY_DEV_OFFSET);
5054 +      *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
5055 +      *PhyState|=PHY_CHANGE;
5056 +      if (cpMacDebug)
5057 +        mdioPrintf("cpMacMdioFindingState: PhyNum: %d\n",PhyNum);
5058 +      }
5059 +     else
5060 +      {
5061 +      if (cpMacDebug)
5062 +        mdioPrintf("cpMacMdioFindingState: Timed Out looking for a Phy!\n");
5063 +      *PhyState|=PHY_RECK_TO;  /* This state currently has no support?*/
5064 +      }
5065 +    }
5066 +  }
5067 +
5068 +void _MdioFoundState(PHY_DEVICE *PhyDev)
5069 +  {
5070 +  bit32u *PhyState  = &PhyDev->PhyState;
5071 +  bit32u  PhyMask   = PhyDev->PhyMask;
5072 +  bit32u  MLinkMask = PhyDev->MLinkMask;
5073 +  bit32u  PhyNum,PhyStatus,NWAYadvertise,m,phynum,i,j,PhyAcks;
5074 +  bit32u  PhySel;
5075 +
5076 +  if ((*PhyState&PHY_SMODE_MASK)==0) return;
5077 +
5078 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5079 +
5080 +  PhyAcks=myMDIO_ALIVE;
5081 +  PhyAcks&=PhyMask;   /* Only interested in 'our' Phys */
5082 +
5083 +  /* Will now isolate all our Phys, except the one we have decided to use */
5084 +  for(phynum=0,j=1;phynum<32;phynum++,j<<=1)
5085 +    {
5086 +    if (PhyAcks&j)
5087 +      {
5088 +        if (phynum!=PhyNum)  /* Do not disabled Found Phy */
5089 +          _mdioDisablePhy(PhyDev,phynum);
5090 +      }
5091 +    }
5092 +
5093 +  /*  Reset the Phy and proceed with auto-negotiation */
5094 +  _mdioResetPhy(PhyDev,PhyNum);
5095 +
5096 +  /* Now setup the MDIOUserPhySel register */
5097 +
5098 +  PhySel=PhyNum;  /* Set the phy address */
5099 +
5100 +  /*  Set the way Link will be Monitored */
5101 +  /* Check the Link Selection Method */
5102 +  if ((1 << PhyNum) & MLinkMask)
5103 +    PhySel |= MDIO_USERPHYSEL_LINKSEL;
5104 +
5105 +  myMDIO_USERPHYSEL = PhySel;  /* update PHYSEL */
5106 +
5107 +  /* Get the Phy Status */
5108 +  PhyStatus = _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5109 +
5110 +
5111 +#ifdef _CPHAL_CPMAC
5112 +  /*  For Phy Internal loopback test, need to wait until Phy
5113 +      found, then set Loopback */
5114 +  if (PhyDev->HalDev->MdioConnect & _CPMDIO_LOOPBK)
5115 +    {
5116 +    /* Set Phy in Loopback */
5117 +    _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_LOOP|PHY_FD);
5118 +    /* Do a read to ensure PHY_LOOP has completed */
5119 +    _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5120 +    *PhyState=(*PhyState&~PHY_STATE_MASK)|(LOOPBACK);
5121 +    *PhyState|=PHY_CHANGE;
5122 +    return;
5123 +    }
5124 +#endif
5125 +
5126 +
5127 +  if (cpMacDebug)
5128 +    mdioPrintf("Enable Phy to negotiate external connection\n");
5129 +
5130 +  NWAYadvertise=NWAY_SEL;
5131 +  if (*PhyState&SMODE_FD100) NWAYadvertise|=NWAY_FD100;
5132 +  if (*PhyState&SMODE_HD100) NWAYadvertise|=NWAY_HD100;
5133 +  if (*PhyState&SMODE_FD10)  NWAYadvertise|=NWAY_FD10;
5134 +  if (*PhyState&SMODE_HD10)  NWAYadvertise|=NWAY_HD10;
5135 +
5136 +  *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
5137 +  if ((PhyStatus&NWAY_CAPABLE)&&(*PhyState&SMODE_AUTO))   /*NWAY Phy Detected*/
5138 +    {
5139 +    /*For NWAY compliant Phys                                                */
5140 +
5141 +    _mdioUserAccessWrite(PhyDev, NWAY_ADVERTIZE_REG, PhyNum, NWAYadvertise);
5142 +
5143 +    if (cpMacDebug)
5144 +      {
5145 +      mdioPrintf("NWAY Advertising: ");
5146 +      if (NWAYadvertise&NWAY_FD100) mdioPrintf("FullDuplex-100 ");
5147 +      if (NWAYadvertise&NWAY_HD100) mdioPrintf("HalfDuplex-100 ");
5148 +      if (NWAYadvertise&NWAY_FD10)  mdioPrintf("FullDuplex-10 ");
5149 +      if (NWAYadvertise&NWAY_HD10)  mdioPrintf("HalfDuplex-10 ");
5150 +      mdioPrintf("\n");
5151 +      }
5152 +
5153 +    _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN);
5154 +
5155 +    _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
5156 +
5157 +    *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
5158 +    }
5159 +   else
5160 +    {
5161 +    *PhyState&=~SMODE_AUTO;   /*The Phy is not capable of auto negotiation!  */
5162 +    m=NWAYadvertise;
5163 +    for(j=0x8000,i=0;(i<16)&&((j&m)==0);i++,j>>=1);
5164 +    m=j;
5165 +    j=0;
5166 +    if (m&(NWAY_FD100|NWAY_HD100))
5167 +      {
5168 +      j=PHY_100;
5169 +      m&=(NWAY_FD100|NWAY_HD100);
5170 +      }
5171 +    if (m&(NWAY_FD100|NWAY_FD10))
5172 +      j |= PHY_FD;
5173 +    if (cpMacDebug)
5174 +      mdioPrintf("Requested PHY mode %s Duplex %s Mbps\n",(j&PHY_FD)?"Full":"Half",(j&PHY_100)?"100":"10");
5175 +    _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, j);
5176 +    *PhyState&=~PHY_SPEED_MASK;
5177 +    if (j&PHY_100)
5178 +      *PhyState|=(1<<PHY_SPEED_OFFSET);
5179 +    *PhyState&=~PHY_DUPLEX_MASK;
5180 +    if (j&PHY_FD)
5181 +      *PhyState|=(1<<PHY_DUPLEX_OFFSET);
5182 +    *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5183 +    }
5184 +     _mdioMdixDelay(PhyDev);  /* If AutoMdix add delay */
5185 +  }
5186 +
5187 +void _MdioNwayStartState(PHY_DEVICE *PhyDev)
5188 +  {
5189 +  bit32u *PhyState = &PhyDev->PhyState;
5190 +  bit32u PhyNum,PhyMode;
5191 +
5192 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5193 +
5194 +  /*Wait for Negotiation to start                                            */
5195 +
5196 +  PhyMode=_mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
5197 +
5198 +  if((PhyMode&RENEGOTIATE)==0)
5199 +    {
5200 +    _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum); /*Flush pending latch bits*/
5201 +    *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
5202 +    *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
5203 +    _mdioMdixDelay(PhyDev);  /* If AutoMdix add delay */
5204 +    }
5205 +   else
5206 +    {
5207 +    if (*PhyState&PHY_TIM_MASK)
5208 +      *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5209 +     else
5210 +      _mdioPhyTimeOut(PhyDev);
5211 +    }
5212 +  }
5213 +
5214 +void _MdioNwayWaitState(PHY_DEVICE *PhyDev)
5215 +  {
5216 +  bit32u *PhyState = &PhyDev->PhyState;
5217 +  bit32u  PhyNum,PhyStatus,NWAYadvertise,NWAYREadvertise,NegMode,i,j;
5218 +
5219 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5220 +
5221 +  PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5222 +
5223 +  if (PhyStatus&NWAY_COMPLETE)
5224 +    {
5225 +    *PhyState|=PHY_CHANGE;
5226 +    *PhyState&=~PHY_SPEED_MASK;
5227 +    *PhyState&=~PHY_DUPLEX_MASK;
5228 +
5229 +    NWAYadvertise   =_mdioUserAccessRead(PhyDev, NWAY_ADVERTIZE_REG, PhyNum);
5230 +    NWAYREadvertise =_mdioUserAccessRead(PhyDev, NWAY_REMADVERTISE_REG, PhyNum);
5231 +
5232 +    /* Negotiated mode is we and the remote have in common */
5233 +    NegMode = NWAYadvertise & NWAYREadvertise;
5234 +
5235 +    if (cpMacDebug)
5236 +      {
5237 +       mdioPrintf("Phy: %d, ",(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
5238 +       mdioPrintf("NegMode %04X, NWAYadvertise %04X, NWAYREadvertise %04X\n",
5239 +         NegMode,  NWAYadvertise, NWAYREadvertise);
5240 +      }
5241 +
5242 +    /* Limit negotiation to fields below */
5243 +    NegMode &= (NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10);
5244 +
5245 +    if (NegMode==0)
5246 +      {
5247 +      NegMode=(NWAY_HD100|NWAY_HD10)&NWAYadvertise; /*or 10 ?? who knows, Phy is not MII compliant*/
5248 +      if(cpMacDebug)
5249 +        {
5250 +         mdioPrintf("Mdio:WARNING: Negotiation complete but NO agreement, default is HD\n");
5251 +         _mdioDumpPhyDetailed(PhyDev);
5252 +        }
5253 +      }
5254 +    for(j=0x8000,i=0;(i<16)&&((j&NegMode)==0);i++,j>>=1);
5255 +
5256 +
5257 +    NegMode=j;
5258 +    if (cpMacDebug)
5259 +      {
5260 +      mdioPrintf("Negotiated connection: ");
5261 +      if (NegMode&NWAY_FD100) mdioPrintf("FullDuplex 100 Mbs\n");
5262 +      if (NegMode&NWAY_HD100) mdioPrintf("HalfDuplex 100 Mbs\n");
5263 +      if (NegMode&NWAY_FD10) mdioPrintf("FullDuplex 10 Mbs\n");
5264 +      if (NegMode&NWAY_HD10) mdioPrintf("HalfDuplex 10 Mbs\n");
5265 +      }
5266 +    if (NegMode!=0)
5267 +      {
5268 +      if (PhyStatus&PHY_LINKED)
5269 +        *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
5270 +       else
5271 +        *PhyState=(*PhyState&~PHY_STATE_MASK)|LINK_WAIT;
5272 +      if (NegMode&(NWAY_FD100|NWAY_HD100))
5273 +        *PhyState=(*PhyState&~PHY_SPEED_MASK)|(1<<PHY_SPEED_OFFSET);
5274 +      if (NegMode&(NWAY_FD100|NWAY_FD10))
5275 +        *PhyState=(*PhyState&~PHY_DUPLEX_MASK)|(1<<PHY_DUPLEX_OFFSET);
5276 +      }
5277 +    }
5278 +   else
5279 +    {
5280 +    if (*PhyState&PHY_TIM_MASK)
5281 +      *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5282 +     else
5283 +      _mdioPhyTimeOut(PhyDev);
5284 +    }
5285 +  }
5286 +
5287 +void _MdioLinkWaitState(PHY_DEVICE *PhyDev)
5288 +  {
5289 +  bit32u *PhyState = &PhyDev->PhyState;
5290 +  bit32u  PhyStatus;
5291 +  bit32u  PhyNum;
5292 +
5293 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5294 +
5295 +  PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5296 +
5297 +  if (PhyStatus&PHY_LINKED)
5298 +    {
5299 +    *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
5300 +    *PhyState|=PHY_CHANGE;
5301 +    }
5302 +   else
5303 +    {
5304 +    if (*PhyState&PHY_TIM_MASK)
5305 +      *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5306 +     else
5307 +      _mdioPhyTimeOut(PhyDev);
5308 +    }
5309 +  }
5310 +
5311 +void _mdioPhyTimeOut(PHY_DEVICE *PhyDev)
5312 +  {
5313 +  bit32u *PhyState;
5314 +
5315 +  if(_mdioMdixSupported(PhyDev) == 0)
5316 +    return;  /* AutoMdix not supported */
5317 +
5318 +  PhyState = &PhyDev->PhyState;
5319 +
5320 +  /*  Indicate MDI/MDIX mode switch is needed */
5321 +  *PhyState|=PHY_MDIX_SWITCH;
5322 +
5323 +  /* Toggle the MDIX mode indicatir */
5324 +  if(*PhyState & PHY_MDIX)
5325 +    *PhyState &= ~PHY_MDIX_MASK;       /* Current State is MDIX, set to MDI */
5326 +  else
5327 +    *PhyState |=  PHY_MDIX_MASK;      /* Current State is MDI, set to MDIX */
5328 +
5329 +  /* Reset state machine to FOUND */
5330 +  *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
5331 +  }
5332 +
5333 +void _MdioLoopbackState(PHY_DEVICE *PhyDev)
5334 +  {
5335 +  return;
5336 +  }
5337 +
5338 +void _MdioLinkedState(PHY_DEVICE *PhyDev)
5339 +  {
5340 +  bit32u *PhyState = &PhyDev->PhyState;
5341 +  bit32u  PhyNum   = (*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5342 +
5343 +  if (myMDIO_LINK&(1<<PhyNum)) return;  /* if still Linked, exit*/
5344 +
5345 +  /* Not Linked */
5346 +  *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
5347 +  if (*PhyState&SMODE_AUTO)
5348 +    *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
5349 +   else
5350 +    *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5351 +
5352 +  _mdioMdixDelay(PhyDev);  /* If AutoMdix add delay */
5353 +  }
5354 +
5355 +void _MdioDefaultState(PHY_DEVICE *PhyDev)
5356 +  {
5357 +  bit32u *PhyState = &PhyDev->PhyState;
5358 +  /*Awaiting a cpMacMdioInit call                                             */
5359 +  *PhyState|=PHY_CHANGE;
5360 +  }
5361 +
5362 +
5363 +/*User Calls*********************************************************       */
5364 +
5365 +void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full)
5366 +  {
5367 +  }
5368 +
5369 +
5370 +int cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetReg, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info)
5371 +  {
5372 +  bit32u HighestChannel;
5373 +  bit32u ControlState;
5374 +  bit32u *PhyState = &PhyDev->PhyState;
5375 +  bit32u clkdiv;                                                  /*MJH+030328*/
5376 +
5377 +  cpMacDebug=verbose;
5378 +
5379 +  PhyDev->miibase   = miibase;
5380 +  PhyDev->inst      = inst;
5381 +  PhyDev->PhyMask   = PhyMask;
5382 +  PhyDev->MLinkMask = MLinkMask;
5383 +  PhyDev->MdixMask  = MdixMask;
5384 +#ifdef _CPHAL_CPMAC
5385 +  PhyDev->HalDev    = (HAL_DEVICE*) Info;
5386 +#endif
5387 +
5388 +  *PhyState &= ~PHY_MDIX_MASK;   /* Set initial State to MDI */
5389 +
5390 +  /* Check that the channel supplied is within range */
5391 +  HighestChannel = (myMDIO_CONTROL & MDIO_CONTROL_HIGHEST_USER_CHANNEL) > 8;
5392 +  if(inst > HighestChannel)
5393 +    return(HighestChannel);
5394 +
5395 +  /*Setup MII MDIO access regs                                              */
5396 +
5397 +  /* Calculate the correct value for the mclkdiv */
5398 +  /* See PITS #14 */
5399 +  if (MdioClockFreq)                                              /*MJH+030402*/
5400 +     clkdiv = (MdioBusFreq / MdioClockFreq) - 1;                  /*MJH+030402*/
5401 +  else                                                            /*MJH+030402*/
5402 +     clkdiv = 0xFF;                                               /*MJH+030402*/
5403 +
5404 +  ControlState  = MDIO_CONTROL_ENABLE;
5405 +  ControlState |= (clkdiv & MDIO_CONTROL_CLKDIV);                 /*MJH+030328*/
5406 +
5407 +  /*
5408 +      If mii is not out of reset or if the Control Register is not set correctly
5409 +      then initalize
5410 +  */
5411 +  if( !(VOLATILE32(ResetReg) & (1 << ResetBit)) ||
5412 +     ((myMDIO_CONTROL & (MDIO_CONTROL_CLKDIV | MDIO_CONTROL_ENABLE)) != ControlState) )/*GSG~030404*/
5413 +    {
5414 +    /*  MII not setup, Setup initial condition  */
5415 +    VOLATILE32(ResetReg) &= ~(1 << ResetBit);
5416 +    _mdioDelayEmulate(PhyDev, 64);
5417 +    VOLATILE32(ResetReg) |= (1 << ResetBit);  /* take mii out of reset  */
5418 +    _mdioDelayEmulate(PhyDev, 64);
5419 +    myMDIO_CONTROL = ControlState;  /* Enable MDIO   */
5420 +    }
5421 +
5422 +  *PhyState=INIT;
5423 +
5424 +  if (cpMacDebug)
5425 +    mdioPrintf("cpMacMdioInit\n");
5426 +  _mdioDumpState(PhyDev);
5427 +  return(0);
5428 +  }
5429 +
5430 +void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode)
5431 +  {
5432 +  bit32u *PhyState = &PhyDev->PhyState;
5433 +  bit32u CurrentState;
5434 +
5435 +  PhyDev->PhyMode = PhyMode;   /* used for AUTOMIDX, planned to replace PhyState fields */
5436 +
5437 +  *PhyState&=~PHY_SMODE_MASK;
5438 +
5439 +  if (PhyMode&NWAY_AUTO)  *PhyState|=SMODE_AUTO;
5440 +  if (PhyMode&NWAY_FD100) *PhyState|=SMODE_FD100;
5441 +  if (PhyMode&NWAY_HD100) *PhyState|=SMODE_HD100;
5442 +  if (PhyMode&NWAY_FD10)  *PhyState|=SMODE_FD10;
5443 +  if (PhyMode&NWAY_HD10)  *PhyState|=SMODE_HD10;
5444 +
5445 +  CurrentState=*PhyState&PHY_STATE_MASK;
5446 +  if ((CurrentState==NWAY_START)||
5447 +      (CurrentState==NWAY_WAIT) ||
5448 +      (CurrentState==LINK_WAIT) ||
5449 +      (CurrentState==LINKED)      )
5450 +    *PhyState=(*PhyState&~PHY_STATE_MASK)|FOUND|PHY_CHANGE;
5451 +  if (cpMacDebug)
5452 +    mdioPrintf("cpMacMdioSetPhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
5453 +     PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
5454 +     PhyMode&NWAY_HD100);
5455 +  _mdioDumpState(PhyDev);
5456 +  }
5457 +
5458 +/* cpMacMdioTic is called every 10 mili seconds to process Phy states         */
5459 +
5460 +int cpMacMdioTic(PHY_DEVICE *PhyDev)
5461 +  {
5462 +  bit32u *PhyState = &PhyDev->PhyState;
5463 +  bit32u  CurrentState;
5464 +
5465 +  /*Act on current state of the Phy                                          */
5466 +
5467 +  CurrentState=*PhyState;
5468 +  switch(CurrentState&PHY_STATE_MASK)
5469 +    {
5470 +    case INIT:       _MdioInitState(PhyDev);      break;
5471 +    case FINDING:    _MdioFindingState(PhyDev);   break;
5472 +    case FOUND:      _MdioFoundState(PhyDev);     break;
5473 +    case NWAY_START: _MdioNwayStartState(PhyDev); break;
5474 +    case NWAY_WAIT:  _MdioNwayWaitState(PhyDev);  break;
5475 +    case LINK_WAIT:  _MdioLinkWaitState(PhyDev);  break;
5476 +    case LINKED:     _MdioLinkedState(PhyDev);    break;
5477 +    case LOOPBACK:   _MdioLoopbackState(PhyDev);  break;
5478 +    default:         _MdioDefaultState(PhyDev);   break;
5479 +    }
5480 +
5481 +  /*Dump state info if a change has been detected                            */
5482 +
5483 +  if ((CurrentState&~PHY_TIM_MASK)!=(*PhyState&~PHY_TIM_MASK))
5484 +    _mdioDumpState(PhyDev);
5485 +
5486 +  /*  Check is MDI/MDIX mode switch is needed */
5487 +  if(*PhyState & PHY_MDIX_SWITCH)
5488 +    {
5489 +    bit32u Mdix;
5490 +
5491 +    *PhyState &= ~PHY_MDIX_SWITCH;  /* Clear Mdix Flip indicator */
5492 +
5493 +    if(*PhyState & PHY_MDIX)
5494 +      Mdix = 1;
5495 +    else
5496 +      Mdix = 0;
5497 +    return(_MIIMDIO_MDIXFLIP|Mdix);
5498 +    }
5499 +
5500 +  /*Return state change to user                                              */
5501 +
5502 +  if (*PhyState&PHY_CHNG_MASK)
5503 +    {
5504 +    *PhyState&=~PHY_CHNG_MASK;
5505 +    return(1);
5506 +    }
5507 +   else
5508 +    return(0);
5509 +  }
5510 +
5511 +/* cpMacMdioGetDuplex is called to retrieve the Duplex info                   */
5512 +
5513 +int cpMacMdioGetDuplex(PHY_DEVICE *PhyDev)
5514 +  {
5515 +  bit32u *PhyState = &PhyDev->PhyState;
5516 +  return((*PhyState&PHY_DUPLEX_MASK)?1:0);  /* return 0 or a 1  */
5517 +  }
5518 +
5519 +/* cpMacMdioGetSpeed is called to retreive the Speed info                     */
5520 +
5521 +int cpMacMdioGetSpeed(PHY_DEVICE *PhyDev)
5522 +  {
5523 +  bit32u *PhyState = &PhyDev->PhyState;
5524 +  return(*PhyState&PHY_SPEED_MASK);
5525 +  }
5526 +
5527 +/* cpMacMdioGetPhyNum is called to retreive the Phy Device Adr info           */
5528 +
5529 +int cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev)
5530 +  {
5531 +  bit32u *PhyState = &PhyDev->PhyState;
5532 +  return((*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
5533 +  }
5534 +
5535 +/* cpMacMdioGetLoopback is called to Determine if the LOOPBACK state has been reached*/
5536 +
5537 +int cpMacMdioGetLoopback(PHY_DEVICE *PhyDev)
5538 +  {
5539 +  bit32u *PhyState = &PhyDev->PhyState;
5540 +  return((*PhyState&PHY_STATE_MASK)==LOOPBACK);
5541 +  }
5542 +/* cpMacMdioGetLinked is called to Determine if the LINKED state has been reached*/
5543 +
5544 +int cpMacMdioGetLinked(PHY_DEVICE *PhyDev)
5545 +  {
5546 +  bit32u *PhyState = &PhyDev->PhyState;
5547 +  return((*PhyState&PHY_STATE_MASK)==LINKED);
5548 +  }
5549 +
5550 +void cpMacMdioLinkChange(PHY_DEVICE *PhyDev)
5551 +  {
5552 +  bit32u *PhyState = &PhyDev->PhyState;
5553 +  bit32u  PhyNum,PhyStatus;
5554 +
5555 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5556 +
5557 +  if (cpMacMdioGetLinked(PhyDev))
5558 +    {
5559 +    PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5560 +
5561 +    if ((PhyStatus&PHY_LINKED)==0)
5562 +      {
5563 +      *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
5564 +      if (*PhyState&SMODE_AUTO)
5565 +        {
5566 +        _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
5567 +        *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
5568 +        }
5569 +       else
5570 +        {
5571 +        *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5572 +        }
5573 +      }
5574 +    }
5575 +  }
5576 +
5577 +void cpMacMdioGetVer(bit32u miibase, bit32u *ModID,  bit32u *RevMaj,  bit32u *RevMin)
5578 +  {
5579 +  bit32u  Ver;
5580 +
5581 +  Ver = MDIO_VER(miibase);
5582 +
5583 +  *ModID  = (Ver & MDIO_VER_MODID) >> 16;
5584 +  *RevMaj = (Ver & MDIO_VER_REVMAJ) >> 8;
5585 +  *RevMin = (Ver & MDIO_VER_REVMIN);
5586 +  }
5587 +
5588 +int cpMacMdioGetPhyDevSize(void)
5589 +  {
5590 +  return(sizeof(PHY_DEVICE));
5591 +  }
5592 +
5593 +  /* returns 0 if current Phy has AutoMdix support, otherwise 0 */
5594 +int _mdioMdixSupported(PHY_DEVICE *PhyDev)
5595 +  {
5596 +  bit32u *PhyState = &PhyDev->PhyState;
5597 +  bit32u PhyNum;
5598 +
5599 +  if((PhyDev->PhyMode & NWAY_AUTOMDIX) == 0)
5600 +    return(0);  /* AutoMdix not turned on */
5601 +
5602 +  PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5603 +  if( ((1<<PhyNum) & PhyDev->MdixMask) == 0)
5604 +    return(0);  /*  Phy does not support AutoMdix*/
5605 +
5606 +  return(1);
5607 +  }
5608 +
5609 +/* If current Phy has AutoMdix support add Mdix Delay to the Timer State Value */
5610 +void _mdioMdixDelay(PHY_DEVICE *PhyDev)
5611 +  {
5612 +  int Delay;
5613 +  bit32u *PhyState = &PhyDev->PhyState;
5614 +#ifdef _CPHAL_CPMAC
5615 +  HAL_DEVICE *HalDev = PhyDev->HalDev;
5616 +#endif
5617 +
5618 +  if(_mdioMdixSupported(PhyDev) == 0)
5619 +    return;  /* AutoMdix not supported */
5620 +/* Currently only supported when used with the CPMAC */
5621 +#ifdef _CPHAL_CPMAC
5622 +  /* Get the Delay value in milli-seconds and convert to ten-milli second value */
5623 +  Delay = cpmacRandomRange(HalDev, _AUTOMDIX_DELAY_MIN, _AUTOMDIX_DELAY_MAX);
5624 +  Delay /= 10;
5625 +
5626 +  /*  Add AutoMidx Random Switch Delay to AutoMdix Link Delay */
5627 +
5628 +  Delay += (PHY_MDIX_TO>>PHY_TIM_OFFSET);
5629 +
5630 +  /* Change Timeout value to AutoMdix standard */
5631 +  *PhyState &= ~(PHY_TIM_MASK);  /* Clear current Time out value */
5632 +  *PhyState |=  (Delay<<PHY_TIM_OFFSET);     /* Set new value */
5633 +#endif
5634 +  }
5635 +
5636 +
5637 diff -urN linux.old/drivers/net/avalanche_cpmac/cpmdio.h linux.dev/drivers/net/avalanche_cpmac/cpmdio.h
5638 --- linux.old/drivers/net/avalanche_cpmac/cpmdio.h      1970-01-01 01:00:00.000000000 +0100
5639 +++ linux.dev/drivers/net/avalanche_cpmac/cpmdio.h      2005-07-12 02:48:42.047593000 +0200
5640 @@ -0,0 +1,73 @@
5641 +/*****************************************************************************
5642 +**      TNETD53xx Software Support
5643 +**      Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
5644 +**
5645 +**      FILE: cpmdio.h   User Include for MDIO API Access
5646 +**
5647 +**      DESCRIPTION:
5648 +**              This include file contains definitions for the the MDIO API
5649 +**
5650 +**      HISTORY:
5651 +**              27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
5652 +**              04Apr02 Michael Hanrahan Added Interrupt Support
5653 +*****************************************************************************/
5654 +#ifndef _INC_CPMDIO
5655 +#define _INC_CPMDIO
5656 +
5657 +
5658 +#ifndef __CPHAL_CPMDIO
5659 +typedef void PHY_DEVICE;
5660 +#endif
5661 +
5662 +
5663 +/*Version Information */
5664 +
5665 +void cpMacMdioGetVer(bit32u miiBase, bit32u *ModID,  bit32u *RevMaj,  bit32u *RevMin);
5666 +
5667 +/*Called once at the begining of time                                        */
5668 +
5669 +int  cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetBase, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info);
5670 +int  cpMacMdioGetPhyDevSize(void);
5671 +
5672 +
5673 +/*Called every 10 mili Seconds, returns TRUE if there has been a mode change */
5674 +
5675 +int cpMacMdioTic(PHY_DEVICE *PhyDev);
5676 +
5677 +/*Called to set Phy mode                                                     */
5678 +
5679 +void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode);
5680 +
5681 +/*Calls to retreive info after a mode change!                                */
5682 +
5683 +int  cpMacMdioGetDuplex(PHY_DEVICE *PhyDev);
5684 +int  cpMacMdioGetSpeed(PHY_DEVICE *PhyDev);
5685 +int  cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev);
5686 +int  cpMacMdioGetLinked(PHY_DEVICE *PhyDev);
5687 +void cpMacMdioLinkChange(PHY_DEVICE *PhyDev);
5688 +
5689 +/*  Shot Down  */
5690 +
5691 +void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full);
5692 +
5693 +
5694 +/* Phy Mode Values  */
5695 +#define NWAY_AUTOMDIX       (1<<16)
5696 +#define NWAY_FD100          (1<<8)
5697 +#define NWAY_HD100          (1<<7)
5698 +#define NWAY_FD10           (1<<6)
5699 +#define NWAY_HD10           (1<<5)
5700 +#define NWAY_AUTO           (1<<0)
5701 +
5702 +/*
5703 + *
5704 + *    Tic() return values
5705 + *
5706 + */
5707 +
5708 +#define _MIIMDIO_MDIXFLIP (1<<28)
5709 +
5710 +#define _AUTOMDIX_DELAY_MIN  80  /* milli-seconds*/
5711 +#define _AUTOMDIX_DELAY_MAX 200  /* milli-seconds*/
5712 +
5713 +#endif  /*  _INC_CPMDIO */
5714 diff -urN linux.old/drivers/net/avalanche_cpmac/cppi_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cppi_cpmac.c
5715 --- linux.old/drivers/net/avalanche_cpmac/cppi_cpmac.c  1970-01-01 01:00:00.000000000 +0100
5716 +++ linux.dev/drivers/net/avalanche_cpmac/cppi_cpmac.c  2005-07-12 02:48:42.048593000 +0200
5717 @@ -0,0 +1,1345 @@
5718 +/*************************************************************************
5719 + *  TNETDxxxx Software Support
5720 + *  Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
5721 + *
5722 + *  FILE: cppi.c
5723 + *
5724 + *  DESCRIPTION:
5725 + *      This file contains shared code for all CPPI modules.
5726 + *
5727 + *  HISTORY:
5728 + *   7Aug02 Greg RC1.00  Original Version created.
5729 + *  27Sep02 Mick RC1.01  Merged for use by CPMAC/CPSAR
5730 + *  16Oct02 Mick RC1.02  Performance Tweaks (see cppihist.txt)
5731 + *  12Nov02 Mick RC1.02  Updated to use cpmac_reg.h
5732 + *  09Jan03 Mick RC3.01  Removed modification to RxBuffer ptr
5733 + *  28Mar03 Mick 1.03    RxReturn now returns error if Malloc Fails
5734 + *  10Apr03 Mick 1.03.02 Added Needs Buffer Support
5735 + *  11Jun03 Mick 1.06.02 halSend() errors corrected
5736 + *  23Aug04 Mick 1.07.08 cpmac only - Send: bypass threshold check if TxInts re-enabled
5737 + *
5738 + *  @author  Greg Guyotte
5739 + *  @version 1.00
5740 + *  @date    7-Aug-2002
5741 + *****************************************************************************/
5742 +/* each CPPI module must modify this file, the rest of the
5743 +                     code in cppi.c should be totally shared *//* Each CPPI module MUST properly define all constants shown below */
5744 +
5745 +/* CPPI registers */
5746 +
5747 +/* the following defines are not CPPI specific */
5748 +
5749 +static int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork);
5750 +
5751 +static void FreeRx(HAL_DEVICE *HalDev, int Ch)
5752 +  {
5753 +   HAL_RCB *rcb_ptr;                                                /*+GSG 030303*/
5754 +   int rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf;                        /*+GSG 030303*/
5755 +   int Num = HalDev->ChData[Ch].RxNumBuffers, i;                    /*+GSG 030303*/
5756 +
5757 +   /* Free Rx data buffers attached to descriptors, if necessary */
5758 +   if (HalDev->RcbStart[Ch] != 0)                                   /*+GSG 030303*/
5759 +     {                                                              /*+GSG 030303*/
5760 +      for(i=0;i<Num;i++)                                            /*+GSG 030303*/
5761 +        {                                                           /*+GSG 030303*/
5762 +         rcb_ptr = (HAL_RCB *)(HalDev->RcbStart[Ch] + (i*rcbSize)); /*+GSG 030303*/
5763 +
5764 +         /* free the data buffer */
5765 +         if (rcb_ptr->DatPtr != 0)
5766 +       {
5767 +
5768 +        HalDev->OsFunc->FreeRxBuffer((void *)rcb_ptr->OsInfo, (void *)rcb_ptr->DatPtr);
5769 +        rcb_ptr->OsInfo=0;                                        /*MJH+030522*/
5770 +        rcb_ptr->DatPtr=0;                                        /*MJH+030522*/
5771 +       }
5772 +    }                                                           /*+GSG 030303*/
5773 +     }                                                              /*+GSG 030303*/
5774 +
5775 +   /* free up all desciptors at once */
5776 +   HalDev->OsFunc->FreeDmaXfer(HalDev->RcbStart[Ch]);
5777 +
5778 +   /* mark buffers as freed */
5779 +   HalDev->RcbStart[Ch] = 0;
5780 +  }
5781 +
5782 +static void FreeTx(HAL_DEVICE *HalDev, int Ch, int Queue)
5783 +  {
5784 +
5785 +/*+GSG 030303*/
5786 +
5787 +   /* free all descriptors at once */
5788 +   HalDev->OsFunc->FreeDmaXfer(HalDev->TcbStart[Ch][Queue]);
5789 +
5790 +   HalDev->TcbStart[Ch][Queue] = 0;
5791 +  }
5792 +
5793 +/* return of 0 means that this code executed, -1 means the interrupt was not
5794 +   a teardown interrupt */
5795 +static int RxTeardownInt(HAL_DEVICE *HalDev, int Ch)
5796 +  {
5797 +   bit32u base = HalDev->dev_base;
5798 +
5799 +   /* check to see if the interrupt is a teardown interrupt */
5800 +   if (((CPMAC_RX_INT_ACK( base , Ch ))  & TEARDOWN_VAL) == TEARDOWN_VAL)
5801 +     {
5802 +      /* finish channel teardown */
5803 +
5804 +      /* Free channel resources on a FULL teardown */
5805 +      if (HalDev->RxTeardownPending[Ch] & FULL_TEARDOWN)
5806 +        {
5807 +         FreeRx(HalDev, Ch);
5808 +        }
5809 +
5810 +      /* bug fix - clear Rx channel pointers on teardown */
5811 +      HalDev->RcbPool[Ch] = 0;
5812 +      HalDev->RxActQueueHead[Ch]  = 0;
5813 +      HalDev->RxActQueueCount[Ch] = 0;
5814 +      HalDev->RxActive[Ch] = FALSE;
5815 +
5816 +      /* write completion pointer */
5817 +      (CPMAC_RX_INT_ACK( base , Ch ))  = TEARDOWN_VAL;
5818 +
5819 +      /* use direction bit as a teardown pending bit! May be able to
5820 +         use only one teardown pending integer in HalDev */
5821 +
5822 +      HalDev->RxTeardownPending[Ch] &= ~RX_TEARDOWN;
5823 +
5824 +      HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
5825 +
5826 +      HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
5827 +      CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
5828 +      if ((HalDev->RxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
5829 +    {
5830 +
5831 +     HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_RX);
5832 +    }
5833 +      HalDev->RxTeardownPending[Ch] = 0;
5834 +
5835 +      return (EC_NO_ERRORS);
5836 +     }
5837 +   return (-1);
5838 +  }
5839 +
5840 +/* return of 0 means that this code executed, -1 means the interrupt was not
5841 +   a teardown interrupt.  Note: this code is always called with Queue == 0 (hi priority). */
5842 +static int TxTeardownInt(HAL_DEVICE *HalDev, int Ch, int Queue)
5843 +  {
5844 +   bit32u base = HalDev->dev_base;
5845 +   HAL_TCB *Last, *Curr, *First;                                    /*+GSG 030303*/
5846 +   int i;
5847 +
5848 +   if (((CPMAC_TX_INT_ACK( base , Ch ))  & TEARDOWN_VAL) == TEARDOWN_VAL)
5849 +     {
5850 +      /* perform all actions for both queues (+GSG 040212) */
5851 +      for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
5852 +        {
5853 +         /* return outstanding buffers to OS                             +RC3.02*/
5854 +         Curr = HalDev->TxActQueueHead[Ch][i];                     /*+GSG 030303*/
5855 +         First = Curr;                                                 /*+GSG 030303*/
5856 +         while (Curr)                                                  /*+GSG 030303*/
5857 +           {                                                           /*+GSG 030303*/
5858 +            /* Pop TCB(s) for packet from the stack */                 /*+GSG 030303*/
5859 +            Last = Curr->Eop;                                          /*+GSG 030303*/
5860 +            HalDev->TxActQueueHead[Ch][i] = Last->Next;            /*+GSG 030303*/
5861 +                                                                    /*+GSG 030303*/
5862 +            /* return to OS */                                         /*+GSG 030303*/
5863 +            HalDev->OsFunc->SendComplete(Curr->OsInfo);                /*+GSG 030303*/
5864 +                                                                    /*+GSG 030303*/
5865 +            /* Push Tcb(s) back onto the stack */                      /*+GSG 030303*/
5866 +            Curr = Last->Next;                                         /*+GSG 030303*/
5867 +            Last->Next = HalDev->TcbPool[Ch][i];                   /*+GSG 030303*/
5868 +            HalDev->TcbPool[Ch][i] = First;                        /*+GSG 030303*/
5869 +                                                                    /*+GSG 030303*/
5870 +            /* set the first(SOP) pointer for the next packet */       /*+GSG 030303*/
5871 +            First = Curr;                                              /*+GSG 030303*/
5872 +           }                                                           /*+GSG 030303*/
5873 +        }
5874 +
5875 +      /* finish channel teardown */
5876 +
5877 +      if (HalDev->TxTeardownPending[Ch] & FULL_TEARDOWN)
5878 +        {
5879 +         FreeTx(HalDev, Ch, 0);
5880 +
5881 +         if (HalDev->ChData[Ch].TxNumQueues == 2)
5882 +           FreeTx(HalDev, Ch, 1);
5883 +        } /* if FULL teardown */
5884 +
5885 +      /* perform all actions for both queues (+GSG 040212) */
5886 +      for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
5887 +        {
5888 +         /* bug fix - clear Tx channel pointers on teardown */
5889 +         HalDev->TcbPool[Ch][i] = 0;
5890 +         HalDev->TxActQueueHead[Ch][i]  = 0;
5891 +         HalDev->TxActQueueCount[Ch][i] = 0;
5892 +         HalDev->TxActive[Ch][i]        = FALSE;
5893 +        }
5894 +
5895 +      /* write completion pointer, only needed for the high priority queue */
5896 +      (CPMAC_TX_INT_ACK( base , Ch ))  = TEARDOWN_VAL;
5897 +
5898 +      /* no longer pending teardown */
5899 +      HalDev->TxTeardownPending[Ch] &= ~TX_TEARDOWN;
5900 +
5901 +      HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
5902 +
5903 +      HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
5904 +      CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
5905 +      if ((HalDev->TxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
5906 +        {
5907 +
5908 +         HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_TX);
5909 +        }
5910 +      HalDev->TxTeardownPending[Ch] = 0;
5911 +
5912 +      return (EC_NO_ERRORS);
5913 +     }
5914 +   return (-1);
5915 +  }
5916 +
5917 +/* +GSG 030421 */
5918 +static void AddToRxQueue(HAL_DEVICE *HalDev, HAL_RCB *FirstRcb, HAL_RCB *LastRcb, int FragCount, int Ch)
5919 +  {
5920 +   if (HalDev->RxActQueueHead[Ch]==0)
5921 +     {
5922 +
5923 +      HalDev->RxActQueueHead[Ch]=FirstRcb;
5924 +      HalDev->RxActQueueTail[Ch]=LastRcb;
5925 +      if (!HalDev->RxActive[Ch])
5926 +        {
5927 +         /* write Rx Queue Head Descriptor Pointer */
5928 +         ((CPMAC_RX_HDP(  HalDev->dev_base  ,  Ch  )) )  = VirtToPhys(FirstRcb) - HalDev->offset;
5929 +         HalDev->RxActive[Ch]=TRUE;
5930 +        }
5931 +     }
5932 +    else
5933 +     {
5934 +      register HAL_RCB *OldTailRcb;
5935 +      register bit32u rmode;
5936 +
5937 +      HalDev->OsFunc->CriticalOn();
5938 +      OldTailRcb=HalDev->RxActQueueTail[Ch];
5939 +      OldTailRcb->Next=(void *)FirstRcb;
5940 +      OldTailRcb=VirtToVirtNoCache(OldTailRcb);
5941 +      OldTailRcb->HNext=VirtToPhys(FirstRcb) - HalDev->offset;
5942 +      HalDev->RxActQueueTail[Ch]=LastRcb;
5943 +      rmode=OldTailRcb->mode;
5944 +      if (rmode&CB_EOQ_BIT)
5945 +        {
5946 +        rmode&=~CB_EOQ_BIT;
5947 +        ((CPMAC_RX_HDP(  HalDev->dev_base  ,  Ch  )) )  = VirtToPhys(FirstRcb) - HalDev->offset;
5948 +        OldTailRcb->mode=rmode;
5949 +        }
5950 +      HalDev->OsFunc->CriticalOff();
5951 +     }
5952 +  }
5953 +
5954 +/**
5955 + *  @ingroup CPHAL_Functions
5956 + *  This function is called to indicate to the CPHAL that the upper layer
5957 + *  software has finished processing the receive data (given to it by
5958 + *  osReceive()).  The CPHAL will then return the appropriate receive buffers
5959 + *  and buffer descriptors to the available pool.
5960 + *
5961 + *  @param   HalReceiveInfo   Start of receive buffer descriptor chain returned to
5962 + *                      CPHAL.
5963 + *  @param   StripFlag  Flag indicating whether the upper layer software has
5964 + *                      retained ownership of the receive data buffers.
5965 + *<BR>
5966 + * 'FALSE' means  that the CPHAL can reuse the receive data buffers.
5967 + *<BR>
5968 + * 'TRUE' : indicates the data buffers were retained by the OS
5969 + *<BR>
5970 + * NOTE:  If StripFlag is TRUE, it is the responsibility of the upper layer software to free the buffers when they are no longer needed.
5971 + *
5972 + *  @return EC_NO_ERRORS (ok). <BR>
5973 + *          Possible Error Codes:<BR>
5974 + *          @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
5975 + *          @ref EC_VAL_RCB_NEEDS_BUFFER "EC_VAL_RCB_NEEDS_BUFFER"<BR>
5976 + *          @ref EC_VAL_RCB_DROPPED "EC_VAL_RCB_DROPPED"<BR>
5977 + */
5978 +static int halRxReturn(HAL_RECEIVEINFO *HalReceiveInfo,
5979 +            int StripFlag)
5980 +  {
5981 +   int Ch, i;
5982 +   HAL_RCB *LastRcb;
5983 +   HAL_DEVICE *HalDev;
5984 +   int RcbSize;
5985 +   int FragCount;
5986 +
5987 +   Ch = HalReceiveInfo->mode&0x0ff;
5988 +   HalDev = (HAL_DEVICE *)HalReceiveInfo->Off_BLen;
5989 +   FragCount = HalReceiveInfo->mode>>8;
5990 +
5991 +   if (HalDev->State != enOpened)
5992 +     return(EC_CPMAC |EC_FUNC_RXRETURN|EC_VAL_INVALID_STATE);
5993 +
5994 +   LastRcb=(HAL_RCB *)HalReceiveInfo->Eop;
5995 +   LastRcb->HNext=0;
5996 +   LastRcb->Next=0;
5997 +   RcbSize = HalDev->ChData[Ch].RxBufSize;
5998 +
5999 +   if (FragCount>1)
6000 +     {
6001 +      LastRcb->Off_BLen=RcbSize;
6002 +      LastRcb->mode=CB_OWNERSHIP_BIT;
6003 +     }
6004 +
6005 +   HalReceiveInfo->Off_BLen=RcbSize;
6006 +   HalReceiveInfo->mode=CB_OWNERSHIP_BIT;
6007 +
6008 +   /* If OS has kept the buffers for this packet, attempt to alloc new buffers */
6009 +   if (StripFlag)
6010 +     {
6011 +      int rc=0;                                                      /*MJH+030417*/
6012 +      int GoodCount=0;                                               /*GSG+030421*/
6013 +      HAL_RCB *TempRcb;
6014 +      char *pBuf;
6015 +      HAL_RCB *CurrHeadRcb = HalReceiveInfo, *LastGoodRcb=0;         /* +GSG 030421 */
6016 +
6017 +      TempRcb = HalReceiveInfo;
6018 +      for (i=0; i<FragCount; i++)
6019 +        {
6020 +         if (TempRcb == 0)
6021 +           {
6022 +            dbgPrintf("Rx Return error while allocating new buffers\n");
6023 +            dbgPrintf("Rcb = %08x, Rcb->Eop = %08x, FragCount = %d:%d\n",
6024 +              (bit32u)HalReceiveInfo, (bit32u)HalReceiveInfo->Eop, FragCount,i);
6025 +            osfuncSioFlush();
6026 +
6027 +            return(EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_CORRUPT_RCB_CHAIN);
6028 +           }
6029 +
6030 +         pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(RcbSize,0,
6031 +                             0xF,HalDev->ChData[Ch].OsSetup,
6032 +                             (void *)TempRcb,
6033 +                             (void *)&TempRcb->OsInfo,
6034 +                             (void *) HalDev->OsDev);
6035 +         if (!pBuf)
6036 +           {
6037 +            /* malloc failed, add this RCB to Needs Buffer List */
6038 +            (HAL_RCB *)TempRcb->Eop = TempRcb;                                  /* GSG +030430 */
6039 +            TempRcb->mode=1<<8|Ch;
6040 +            TempRcb->Off_BLen=(bit32u)HalDev;
6041 +
6042 +            if(HalDev->NeedsCount < MAX_NEEDS)                                  /* +MJH 030410 */
6043 +              {                                                                 /* +MJH 030410 */
6044 +               HalDev->Needs[HalDev->NeedsCount] = (HAL_RECEIVEINFO *) TempRcb; /* +MJH 030410 */
6045 +               HalDev->NeedsCount++;                                            /* +MJH 030410 */
6046 +               rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_NEEDS_BUFFER);         /* ~MJH 030417 */
6047 +              }                                                                 /* +MJH 030410 */
6048 +             else                                                               /* +MJH 030410 */
6049 +               rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_DROPPED);              /* ~MJH 030417 */
6050 +
6051 +            /* requeue any previous RCB's that were ready to go before this one */
6052 +            if (GoodCount > 0)                                                  /* +GSG 030421 */
6053 +              {                                                                 /* +GSG 030421 */
6054 +               LastGoodRcb->HNext=0;                                            /* +GSG 030430 */
6055 +               LastGoodRcb->Next=0;                                             /* +GSG 030430 */
6056 +               osfuncDataCacheHitWritebackAndInvalidate((void *)LastGoodRcb, 16);            /* +GSG 030430 */
6057 +
6058 +               AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch);   /* +GSG 030421 */
6059 +               GoodCount = 0;                                                   /* +GSG 030421 */
6060 +              }                                                                 /* +GSG 030421 */
6061 +
6062 +            CurrHeadRcb = TempRcb->Next;                                        /* +GSG 030421 */
6063 +           }
6064 +          else                                                                  /* +GSG 030421 */
6065 +           {                                                                    /* +GSG 030421 */
6066 +            /* malloc succeeded, requeue the RCB to the hardware */
6067 +            TempRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
6068 +            TempRcb->DatPtr=pBuf;
6069 +            /* Emerald fix 10/29 */
6070 +            osfuncDataCacheHitWritebackAndInvalidate((void *)TempRcb, 16);
6071 +
6072 +            /* i store the last good RCB in case the malloc fails for the
6073 +               next fragment.  This ensures that I can go ahead and return
6074 +               a partial chain of RCB's to the hardware */
6075 +            LastGoodRcb = TempRcb;                                              /* +GSG 030421 */
6076 +            GoodCount++;                                                        /* +GSG 030421 */
6077 +           }                                                                    /* +GSG 030421 */
6078 +         TempRcb = TempRcb->Next;
6079 +        } /*  end of Frag loop */
6080 +      /* if there any good RCB's to requeue, do so here */
6081 +      if (GoodCount > 0)                                                        /* +GSG 030421 */
6082 +        {
6083 +         AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch);          /* +GSG 030421 */
6084 +        }
6085 +      return(rc);                                                               /* ~GSG 030421 */
6086 +     }
6087 +   else
6088 +     {
6089 +      /*  Not Stripping */
6090 +      /* Emerald */
6091 +      /* Write Back SOP and last RCB */
6092 +      osfuncDataCacheHitWritebackAndInvalidate((void *)HalReceiveInfo, 16);
6093 +
6094 +      if (FragCount > 1)
6095 +        {
6096 +         osfuncDataCacheHitWritebackAndInvalidate((void *)LastRcb, 16);
6097 +        }
6098 +      /* if not stripping buffers, always add to queue */
6099 +      AddToRxQueue(HalDev, HalReceiveInfo, LastRcb, FragCount, Ch); /*MJH~030520*/
6100 +     }
6101 +
6102 +   return(EC_NO_ERRORS);
6103 +  }
6104 +
6105 +/* +MJH 030410
6106 +   Trys to liberate an RCB until liberation fails.
6107 +   Note: If liberation fails then RxReturn will re-add the RCB to the
6108 +         Needs list.
6109 +*/
6110 +static void NeedsCheck(HAL_DEVICE *HalDev)
6111 +{
6112 +    HAL_RECEIVEINFO* HalRcb;
6113 +    int rc;
6114 +    HalDev->OsFunc->CriticalOn();
6115 +    while(HalDev->NeedsCount)
6116 +      {
6117 +      HalDev->NeedsCount--;
6118 +      HalRcb = HalDev->Needs[HalDev->NeedsCount];
6119 +      rc =  halRxReturn(HalRcb, 1);
6120 +      /* short circuit if RxReturn starts to fail */
6121 +      if (rc != 0)
6122 +        break;
6123 +      }
6124 +    HalDev->OsFunc->CriticalOff();
6125 +}
6126 +
6127 +/*
6128 + *  This function allocates transmit buffer descriptors (internal CPHAL function).
6129 + *  It creates a high priority transmit queue by default for a single Tx
6130 + *  channel.  If QoS is enabled for the given CPHAL device, this function
6131 + *  will also allocate a low priority transmit queue.
6132 + *
6133 + *  @param   HalDev   CPHAL module instance. (set by cphalInitModule())
6134 + *  @param   Ch       Channel number.
6135 + *
6136 + *  @return  0 OK, Non-Zero Not OK
6137 + */
6138 +static int InitTcb(HAL_DEVICE *HalDev, int Ch)
6139 +  {
6140 +   int i, Num = HalDev->ChData[Ch].TxNumBuffers;
6141 +   HAL_TCB *pTcb=0;
6142 +   char *AllTcb;
6143 +   int  tcbSize, Queue;
6144 +   int SizeMalloc;
6145 +
6146 +   tcbSize = (sizeof(HAL_TCB)+0xf)&~0xf;
6147 +   SizeMalloc = (tcbSize*Num)+0xf;
6148 +
6149 +   for (Queue=0; Queue < HalDev->ChData[Ch].TxNumQueues; Queue++)
6150 +     {
6151 +      if (HalDev->TcbStart[Ch][Queue] == 0)
6152 +        {
6153 +
6154 +         /* malloc all TCBs at once */
6155 +         AllTcb = (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
6156 +         if (!AllTcb)
6157 +           {
6158 +            return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_TCB_MALLOC_FAILED);
6159 +           }
6160 +
6161 +         HalDev->OsFunc->Memset(AllTcb, 0, SizeMalloc);
6162 +
6163 +         /* keep this address for freeing later */
6164 +         HalDev->TcbStart[Ch][Queue] = AllTcb;
6165 +        }
6166 +       else
6167 +        {
6168 +         /* if the memory has already been allocated, simply reuse it! */
6169 +         AllTcb = HalDev->TcbStart[Ch][Queue];
6170 +        }
6171 +
6172 +      /* align to cache line */
6173 +      AllTcb = (char *)(((bit32u)AllTcb + 0xf) &~ 0xf); /*PITS #143  MJH~030522*/
6174 +
6175 +      /* default High priority transmit queue */
6176 +      HalDev->TcbPool[Ch][Queue]=0;
6177 +      for(i=0;i<Num;i++)
6178 +        {
6179 +         /*pTcb=(HAL_TCB *) OsFunc->MallocDmaXfer(sizeof(HAL_TCB),0,0xffffffff); */
6180 +         pTcb= (HAL_TCB *)(AllTcb + (i*tcbSize));
6181 +         pTcb->mode=0;
6182 +         pTcb->BufPtr=0;
6183 +         pTcb->Next=HalDev->TcbPool[Ch][Queue];
6184 +         pTcb->Off_BLen=0;
6185 +         HalDev->TcbPool[Ch][Queue]=pTcb;
6186 +        }
6187 +      /*HalDev->TcbEnd = pTcb;*/
6188 +     }
6189 +
6190 +   return(EC_NO_ERRORS);
6191 +  }
6192 +
6193 +/*
6194 + *  This function allocates receive buffer descriptors (internal CPHAL function).
6195 + *  After allocation, the function 'queues' (gives to the hardware) the newly
6196 + *  created receive buffers to enable packet reception.
6197 + *
6198 + *  @param   HalDev   CPHAL module instance. (set by cphalInitModule())
6199 + *  @param   Ch    Channel number.
6200 + *
6201 + *  @return  0 OK, Non-Zero Not OK
6202 + */
6203 +static int InitRcb(HAL_DEVICE *HalDev, int Ch)
6204 +  {
6205 +   int i, Num = HalDev->ChData[Ch].RxNumBuffers;
6206 +   int Size = HalDev->ChData[Ch].RxBufSize;
6207 +   HAL_RCB *pRcb;
6208 +   char *pBuf;
6209 +   char *AllRcb;
6210 +   int  rcbSize;
6211 +   int  DoMalloc = 0;
6212 +   int SizeMalloc;
6213 +   int MallocSize;
6214 +
6215 +   rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf;
6216 +   SizeMalloc = (rcbSize*Num)+0xf;
6217 +
6218 +   if (HalDev->RcbStart[Ch] == 0)
6219 +     {
6220 +      DoMalloc = 1;
6221 +
6222 +      /* malloc all RCBs at once */
6223 +      AllRcb= (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
6224 +      if (!AllRcb)
6225 +        {
6226 +         return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RCB_MALLOC_FAILED);
6227 +        }
6228 +
6229 +      HalDev->OsFunc->Memset(AllRcb, 0, SizeMalloc);
6230 +
6231 +      /* keep this address for freeing later */
6232 +      HalDev->RcbStart[Ch] = AllRcb;
6233 +     }
6234 +    else
6235 +     {
6236 +      /* if the memory has already been allocated, simply reuse it! */
6237 +      AllRcb = HalDev->RcbStart[Ch];
6238 +     }
6239 +
6240 +   /* align to cache line */
6241 +   AllRcb = (char *)(((bit32u)AllRcb + 0xf)&~0xf);  /*PITS #143  MJH~030522*/
6242 +
6243 +   HalDev->RcbPool[Ch]=0;
6244 +   for(i=0;i<Num;i++)
6245 +     {
6246 +      pRcb = (HAL_RCB *)(AllRcb + (i*rcbSize));
6247 +
6248 +      if (DoMalloc == 1)
6249 +        {
6250 +
6251 +         MallocSize = Size;                                       /*~3.01 */
6252 +         pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(MallocSize,0,0xF,HalDev->ChData[Ch].OsSetup, (void *)pRcb, (void *)&pRcb->OsInfo, (void *) HalDev->OsDev);
6253 +         if(!pBuf)
6254 +             {
6255 +            return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RX_BUFFER_MALLOC_FAILED);
6256 +             }
6257 +           /* -RC3.01 pBuf = (char *)(((bit32u)pBuf+0xF) & ~0xF); */
6258 +         pRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
6259 +         pRcb->DatPtr=pBuf;
6260 +        }
6261 +      pRcb->mode=(1<<8)|Ch; /* One Frag for Ch */
6262 +      pRcb->Next=(void *)HalDev->RcbPool[Ch];
6263 +      pRcb->Off_BLen=(bit32u)HalDev;
6264 +      HalDev->RcbPool[Ch]=pRcb;
6265 +     }
6266 +
6267 +   /* Give all of the Rx buffers to hardware */
6268 +
6269 +   while(HalDev->RcbPool[Ch])
6270 +     {
6271 +      pRcb=HalDev->RcbPool[Ch];
6272 +      HalDev->RcbPool[Ch]=pRcb->Next;
6273 +      pRcb->Eop=(void*)pRcb;
6274 +      pRcb->mode=(1<<8)|Ch;
6275 +      halRxReturn((HAL_RECEIVEINFO *)pRcb, 0);
6276 +     }
6277 +
6278 +   return(EC_NO_ERRORS);
6279 +  }
6280 +
6281 +/**
6282 + *  @ingroup CPHAL_Functions
6283 + *  This function transmits the data in FragList using available transmit
6284 + *  buffer descriptors.  More information on the use of the Mode parameter
6285 + *  is available in the module-specific appendices.  Note:  The OS should
6286 + *  not call Send() for a channel that has been requested to be torndown.
6287 + *
6288 + *  @param   HalDev      CPHAL module instance. (set by cphalInitModule())
6289 + *  @param   FragList    Fragment List structure.
6290 + *  @param   FragCount   Number of fragments in FragList.
6291 + *  @param   PacketSize  Number of bytes to transmit.
6292 + *  @param   OsSendInfo  OS Send Information structure. <BR>
6293 + *  @param   Mode        32-bit value with the following bit fields: <BR>
6294 + *                       31-16: Mode  (used for module specific data). <BR>
6295 + *                       15-08: Queue (transmit queue to send on). <BR>
6296 + *                       07-00: Channel (channel number to send on).
6297 + *
6298 + *  @return  EC_NO_ERRORS (ok). <BR>
6299 + *           Possible Error Codes:<BR>
6300 + *           @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6301 + *           @ref EC_VAL_NOT_LINKED "EC_VAL_NOT_LINKED"<BR>
6302 + *           @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
6303 + *           @ref EC_VAL_OUT_OF_TCBS "EC_VAL_OUT_OF_TCBS"<BR>
6304 + *           @ref EC_VAL_NO_TCBS "EC_VAL_NO_TCBS"<BR>
6305 + */
6306 +static int halSend(HAL_DEVICE *HalDev,FRAGLIST *FragList,
6307 +                      int FragCount,int PacketSize, OS_SENDINFO *OsSendInfo,
6308 +                      bit32u Mode)
6309 +  {
6310 +  HAL_TCB *tcb_ptr, *head;
6311 +  int i;
6312 +  int rc = EC_NO_ERRORS;
6313 +  int Ch = Mode & 0xFF;
6314 +  int Queue = (Mode>>8)&0xFF;
6315 +  /*int DoThresholdCheck=1;  */ /* Used when TxIntDisable is set and TxInts are re-enabled */
6316 +
6317 +  if (HalDev->State != enOpened)
6318 +     return(EC_CPPI|EC_FUNC_SEND|EC_VAL_INVALID_STATE);
6319 +
6320 +  if (!HalDev->Linked)
6321 +    {
6322 +     rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NOT_LINKED;
6323 +     return(rc);
6324 +    }
6325 +
6326 +  if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0)                    /*MJH~030611*/ /*PITS 148*/
6327 +    return(EC_CPMAC |EC_FUNC_SEND|EC_VAL_INVALID_CH);              /*+GSG 030303*/
6328 +
6329 +  HalDev->OsFunc->CriticalOn();
6330 +
6331 +  /* Setup Tx mode and size */
6332 +  if (PacketSize<60)
6333 +    {
6334 +     FragList[FragCount-1].len += (60 - PacketSize);              /*MJH~030506*//*PITS 132*/
6335 +     PacketSize = 60;                                             /*MJH~030506*/
6336 +    }
6337 +  Mode &= CB_PASSCRC_BIT;
6338 +
6339 +  tcb_ptr = head = HalDev->TcbPool[Ch][Queue];
6340 +
6341 +  if (tcb_ptr)
6342 +    {
6343 +
6344 +     Mode|=PacketSize|CB_SOF_BIT|CB_OWNERSHIP_BIT;
6345 +
6346 +     for (i=0; i<FragCount; i++)
6347 +
6348 +       {
6349 +        /* Setup Tx mode and size */
6350 +        tcb_ptr->Off_BLen = FragList[i].len;
6351 +
6352 +        tcb_ptr->mode     = Mode;
6353 +        tcb_ptr->BufPtr   = VirtToPhys((bit32 *)FragList[i].data) - HalDev->offset;
6354 +        tcb_ptr->OsInfo = OsSendInfo;
6355 +
6356 +        if (i == (FragCount - 1))
6357 +          {
6358 +           /* last fragment */
6359 +           tcb_ptr->mode |= CB_EOF_BIT;
6360 +
6361 +           /* since this is the last fragment, set the TcbPool pointer before
6362 +              nulling out the Next pointers */
6363 +
6364 +           HalDev->TcbPool[Ch][Queue] = tcb_ptr->Next;
6365 +
6366 +           tcb_ptr->Next = 0;
6367 +           tcb_ptr->HNext = 0;
6368 +
6369 +           /* In the Tx Interrupt handler, we will need to know which TCB is EOP,
6370 +              so we can save that information in the SOP */
6371 +           head->Eop = tcb_ptr;
6372 +
6373 +           /* Emerald fix 10/29 */
6374 +       osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
6375 +
6376 +          }
6377 +         else
6378 +          {
6379 +           Mode=CB_OWNERSHIP_BIT;
6380 +           tcb_ptr->HNext    = VirtToPhys((bit32 *)tcb_ptr->Next) - HalDev->offset;
6381 +
6382 +           /* Emerald fix 10/29 */
6383 +           osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
6384 +
6385 +           tcb_ptr = tcb_ptr->Next;  /* what about the end of TCB list?? */
6386 +
6387 +           if (tcb_ptr == 0)
6388 +             {
6389 +              rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_OUT_OF_TCBS;
6390 +              goto ExitSend;
6391 +             }
6392 +          }
6393 +       } /* for */
6394 +
6395 +     /* put it on the high priority queue */
6396 +     if (HalDev->TxActQueueHead[Ch][Queue] == 0)
6397 +       {
6398 +        HalDev->TxActQueueHead[Ch][Queue]=head;
6399 +        HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
6400 +/*+GSG 030303*//*+GSG 030303*/
6401 +        if (!HalDev->TxActive[Ch][Queue])
6402 +          {
6403 +
6404 +              bit32u base = HalDev->dev_base;
6405 +
6406 +              /* write CPPI TX HDP */
6407 +              (CPMAC_TX_HDP( base , Ch ))  = VirtToPhys(head)  - HalDev->offset;
6408 +              HalDev->TxActive[Ch][Queue]=TRUE;
6409 +
6410 +          }
6411 +       }
6412 +      else
6413 +       {
6414 +           register volatile HAL_TCB *pTailTcb;
6415 +        register bit32u tmode;
6416 +        register bit32u pCurrentTcb;
6417 +
6418 +        HalDev->TxActQueueTail[Ch][Queue]->Next=head;
6419 +        /* Emerald fix 10/29 */
6420 +
6421 +        pTailTcb=(HAL_TCB *)VirtToVirtNoCache(&HalDev->TxActQueueTail[Ch][Queue]->HNext);
6422 +        pCurrentTcb=VirtToPhys(head)  - HalDev->offset;
6423 +        pTailTcb->HNext=pCurrentTcb;
6424 +        HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
6425 +/*+GSG 030303*/
6426 +        tmode=pTailTcb->mode;
6427 +        if (tmode&CB_EOQ_BIT)
6428 +          {
6429 +           bit32u base = HalDev->dev_base;
6430 +
6431 +           tmode&=~CB_EOQ_BIT;
6432 +           pTailTcb->mode=tmode;
6433 +           ((CPMAC_TX_HDP( base , Ch )) )  = pCurrentTcb;
6434 +          }
6435 +
6436 +        else
6437 +          {
6438 +           if(HalDev->TxIntDisable)
6439 +             {
6440 +              /*  Enable Interrupts, to ensure packet goes out on wire */
6441 +              CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch);
6442 +              halPacketProcessEnd(HalDev); /* Allow Interrupt to be seen at the OS */
6443 +              /*DoThresholdCheck = 0; */       /* Disable Threshold Check */
6444 +
6445 +             }
6446 +          }
6447 +
6448 +       }
6449 +     rc = EC_NO_ERRORS;
6450 +     goto ExitSend;
6451 +    } /* if (tcb_ptr) */
6452 +   else
6453 +    {
6454 +     rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NO_TCBS;
6455 +     goto ExitSend;
6456 +    }
6457 +ExitSend:
6458 +
6459 +/* 15 June 2004 - NSP Performance Update : If Tx Ints are disabled then process them here */
6460 +/* 29 June 2004 - NSP Performance Update : Moved to end at request of BCIL */
6461 +/* 23 Aug  2004 - NSP Performance Update : If Tx Ints are re-enabled do not do Threshold check */
6462 +
6463 +   if(HalDev->TxIntDisable /*&& DoThresholdCheck*/)
6464 +   {
6465 +      if(--HalDev->TxIntThreshold[Ch] <= 0)
6466 +      {
6467 +          int MoreWork;
6468 +          TxInt(HalDev, Ch, 0, &MoreWork);
6469 +          HalDev->TxIntThreshold[Ch] = HalDev->TxIntThresholdMaster[Ch];
6470 +      }
6471 +   }
6472 +    HalDev->OsFunc->CriticalOff();
6473 +
6474 +   return(rc);
6475 +  }
6476 +
6477 +/*
6478 + *  This function processes receive interrupts.  It traverses the receive
6479 + *  buffer queue, extracting the data and passing it to the upper layer software via
6480 + *  osReceive().  It handles all error conditions and fragments without valid data by
6481 + *  immediately returning the RCB's to the RCB pool.
6482 + *
6483 + *  @param   HalDev   CPHAL module instance. (set by cphalInitModule())
6484 + *  @param   Ch       Channel Number.
6485 + *  @param   MoreWork Flag that indicates that there is more work to do when set to 1.
6486 + *
6487 + *  @return  0 if OK, non-zero otherwise.
6488 + */
6489 +static int RxInt(HAL_DEVICE *HalDev, int Ch, int *MoreWork)
6490 +  {
6491 +  HAL_RCB *CurrentRcb, *SopRcb, *EofRcb, *EopRcb;
6492 +  bit32u RxBufStatus,PacketsServiced, RxPktLen = 0, RxSopStatus,
6493 +    FrmFrags, TotalFrags, FrmLen;
6494 +  int base = HalDev->dev_base, Ret;
6495 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
6496 +  int RxServiceMax = HalDev->ChData[Ch].RxServiceMax;
6497 +  int FragIndex; /* +GSG 030508 */
6498 +
6499 +  if(HalDev->NeedsCount) /* +MJH 030410 */
6500 +    NeedsCheck(HalDev);  /* +MJH 030410 */
6501 +
6502 +  /* Handle case of teardown interrupt */
6503 +  if (HalDev->RxTeardownPending[Ch] != 0)
6504 +    {
6505 +     Ret = RxTeardownInt(HalDev, Ch);
6506 +     if (Ret == 0)
6507 +       {                                                              /*+GSG 030303*/
6508 +        *MoreWork = 0;
6509 +        return (EC_NO_ERRORS);
6510 +       }                                                              /*+GSG 030303*/
6511 +    }
6512 +
6513 +  /* Examine first RCB on the software active queue */
6514 +  CurrentRcb=HalDev->RxActQueueHead[Ch];
6515 +  osfuncDataCacheHitInvalidate((void*)CurrentRcb, 16);
6516 +  RxBufStatus=CurrentRcb->mode;
6517 +  PacketsServiced=0;
6518 +
6519 +  /* Process received packets until we find hardware owned descriptors
6520 +     or until we hit RxServiceMax */
6521 +  while((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)&&
6522 +    (PacketsServiced<RxServiceMax)) /* ~GSG 030307 */
6523 +    {
6524 +
6525 +     PacketsServiced++; /* ~GSG 030307 */
6526 +     SopRcb=CurrentRcb;
6527 +     RxSopStatus=RxBufStatus;
6528 +     RxPktLen = RxSopStatus&CB_SIZE_MASK;
6529 +
6530 +     FrmFrags=0;
6531 +     TotalFrags=0;
6532 +     FragIndex=0;
6533 +     FrmLen=0;
6534 +     EofRcb=0;
6535 +
6536 +/* +GSG 030508 *//* +GSG 030508 */
6537 +
6538 +     /* Loop through all fragments that comprise current packet.  Build
6539 +        fraglist and exit when the end of the packet is reached, or the
6540 +        end of the descriptor list is reached. */
6541 +     do
6542 +       {
6543 +           bit32u DmaLen;
6544 +
6545 +
6546 +        DmaLen=CurrentRcb->Off_BLen;
6547 +
6548 +        FrmLen+=DmaLen;
6549 +        TotalFrags++;
6550 +        if (!EofRcb)
6551 +          {
6552 +           HalDev->fraglist[FragIndex].data=((char *)CurrentRcb->DatPtr);       /* ~GSG 030508 */
6553 +
6554 +           HalDev->fraglist[FragIndex].len=DmaLen;                              /* ~GSG 030508 */
6555 +
6556 +           /* GSG 12/9 */
6557 +           HalDev->fraglist[FragIndex].OsInfo = CurrentRcb->OsInfo;             /* ~GSG 030508 */
6558 +
6559 +           /* Upper layer must do the data invalidate */
6560 +
6561 +           FrmFrags++;
6562 +           FragIndex++;                                                         /* ~GSG 030508 */
6563 +           if (FrmLen>=RxPktLen)
6564 +             EofRcb=CurrentRcb;
6565 +          }
6566 +        EopRcb=CurrentRcb;
6567 +        CurrentRcb=EopRcb->Next;
6568 +        if (CurrentRcb)
6569 +          {
6570 +           osfuncDataCacheHitInvalidate((void*)CurrentRcb,16);
6571 +          }
6572 +       }while(((EopRcb->mode&CB_EOF_BIT)==0)&&(CurrentRcb));
6573 +
6574 +     /* Write the completion pointer for interrupt acknowledgement*/
6575 +     (CPMAC_RX_INT_ACK( base , Ch ))  = VirtToPhys(EopRcb) - HalDev->offset;
6576 +
6577 +     EopRcb->Next=0;
6578 +
6579 +     if (CurrentRcb == 0)
6580 +       {
6581 +           /* If we are out of RCB's we must not send this packet
6582 +              to the OS. */
6583 +        int RcbSize = HalDev->ChData[Ch].RxBufSize;
6584 +
6585 +        if (TotalFrags>1)
6586 +          {
6587 +           EopRcb->Off_BLen=RcbSize;
6588 +           EopRcb->mode=CB_OWNERSHIP_BIT;
6589 +           osfuncDataCacheHitWritebackAndInvalidate((void *)EopRcb, 16);
6590 +          }
6591 +
6592 +        SopRcb->Off_BLen=RcbSize;
6593 +        SopRcb->mode=CB_OWNERSHIP_BIT;
6594 +        osfuncDataCacheHitWritebackAndInvalidate((void *)SopRcb, 16);
6595 +
6596 +        ((CPMAC_RX_HDP( base , Ch )) )  = VirtToPhys(SopRcb);
6597 +       }
6598 +      else
6599 +       {
6600 +           /* Dequeue packet and send to OS */
6601 +        int mode;
6602 +
6603 +        /* setup SopRcb for the packet */
6604 +        SopRcb->Eop=(void*)EopRcb;
6605 +
6606 +        /* dequeue packet */
6607 +        HalDev->RxActQueueHead[Ch]=CurrentRcb;
6608 +
6609 +        if (EopRcb->mode&CB_EOQ_BIT)
6610 +          {
6611 +              /* Next pointer is non-null and EOQ bit is set, which
6612 +                 indicates misqueue packet in CPPI protocol. */
6613 +
6614 +           ((CPMAC_RX_HDP( base , Ch )) )  = EopRcb->HNext;
6615 +          }
6616 +
6617 +        mode = (SopRcb->mode & 0xFFFF0000) | Ch;
6618 +
6619 +        SopRcb->mode=(FrmFrags<<8)|Ch;
6620 +        SopRcb->Off_BLen=(bit32u)HalDev;
6621 +
6622 +        /* send packet up the higher layer driver */
6623 +        OsFunc->Receive(HalDev->OsDev,HalDev->fraglist,FragIndex,RxPktLen,             /* ~GSG 030508 */
6624 +                       (HAL_RECEIVEINFO *)SopRcb,mode);
6625 +
6626 +        RxBufStatus=CurrentRcb->mode;
6627 +       }
6628 +    } /* while loop */
6629 +
6630 +  if ((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)) /*~GSG 030307*/
6631 +    {
6632 +     *MoreWork = 1;
6633 +    }
6634 +   else
6635 +    {
6636 +     *MoreWork = 0;
6637 +    }
6638 +
6639 +  return (EC_NO_ERRORS);
6640 +}
6641 +
6642 +/*
6643 + *  This function processes transmit interrupts.  It traverses the
6644 + *  transmit buffer queue, detecting sent data buffers and notifying the upper
6645 + *  layer software via osSendComplete().  (for SAR, i originally had this split
6646 + *  into two functions, one for each queue, but joined them on 8/8/02)
6647 + *
6648 + *  @param   HalDev   CPHAL module instance. (set by cphalInitModule())
6649 + *  @param   Queue    Queue number to service (always 0 for MAC, Choose 1 for SAR to service low priority queue)
6650 + *  @param   MoreWork Flag that indicates that there is more work to do when set to 1.
6651 + *
6652 + *  @return  0 if OK, non-zero otherwise.
6653 + */
6654 +int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork)
6655 +  {
6656 +  HAL_TCB *CurrentTcb,*LastTcbProcessed,*FirstTcbProcessed;
6657 +  int PacketsServiced;
6658 +  bit32u TxFrameStatus;
6659 +  int base;
6660 +  int TxServiceMax = HalDev->ChData[Ch].TxServiceMax;
6661 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
6662 +
6663 +/*+GSG 030303*//*+GSG 030303*/
6664 +
6665 +  /* load the module base address */
6666 +  base = HalDev->dev_base;
6667 +
6668 +  /* Handle case of teardown interrupt.  This must be checked at
6669 +     the top of the function rather than the bottom, because
6670 +     the normal data processing can wipe out the completion
6671 +     pointer which is used to determine teardown complete. */
6672 +  if (HalDev->TxTeardownPending[Ch] != 0)
6673 +    {
6674 +        int Ret;
6675 +
6676 +     Ret = TxTeardownInt(HalDev, Ch, Queue);
6677 +     if (Ret == 0)
6678 +       {                                                              /*+GSG 030303*/
6679 +        *MoreWork = 0; /* bug fix 1/6 */                              /*+GSG 030303*/
6680 +        return (EC_NO_ERRORS);
6681 +       }                                                              /*+GSG 030303*/
6682 +    }
6683 +
6684 +  OsFunc->CriticalOn(); /*  240904 */
6685 +
6686 +  CurrentTcb = HalDev->TxActQueueHead[Ch][Queue];
6687 +  FirstTcbProcessed=CurrentTcb;
6688 +
6689 +  if (CurrentTcb==0)
6690 +    {
6691 +     /* I saw this error a couple of times when multi-channels were added */
6692 +     dbgPrintf("[cppi TxInt()]TxH int with no TCB in queue!\n");
6693 +     dbgPrintf("              Ch=%d, CurrentTcb = 0x%08x\n", Ch, (bit32u)CurrentTcb);
6694 +     dbgPrintf("              HalDev = 0x%08x\n", (bit32u)HalDev);
6695 +     osfuncSioFlush();
6696 +     OsFunc->CriticalOff();
6697 +     return(EC_CPPI|EC_FUNC_TXINT|EC_VAL_NULL_TCB);
6698 +    }
6699 +
6700 +  osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
6701 +  TxFrameStatus=CurrentTcb->mode;
6702 +  PacketsServiced=0;
6703 +
6704 +  /* should the ownership bit check be inside of the loop?? could make it a
6705 +     while-do loop and take this check away */
6706 +  if ((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6707 +    {
6708 +    do
6709 +      {
6710 +      /* Pop TCB(s) for packet from the stack */
6711 +      LastTcbProcessed=CurrentTcb->Eop;
6712 +
6713 +      /* new location for acknowledge */
6714 +      /* Write the completion pointer */
6715 +      (CPMAC_TX_INT_ACK( base , Ch ))  = VirtToPhys(LastTcbProcessed) - HalDev->offset;
6716 +
6717 +      HalDev->TxActQueueHead[Ch][Queue] = LastTcbProcessed->Next;
6718 +
6719 +/*+GSG 030303*//*+GSG 030303*/
6720 +
6721 +      osfuncDataCacheHitInvalidate((void *)LastTcbProcessed, 16);
6722 +
6723 +      if (LastTcbProcessed->mode&CB_EOQ_BIT)
6724 +        {
6725 +         if (LastTcbProcessed->Next)
6726 +           {
6727 +            /* Misqueued packet */
6728 +
6729 +               (CPMAC_TX_HDP( base , Ch ))  = LastTcbProcessed->HNext;
6730 +
6731 +           }
6732 +          else
6733 +           {
6734 +       /* Tx End of Queue */
6735 +
6736 +            HalDev->TxActive[Ch][Queue]=FALSE;
6737 +           }
6738 +        }
6739 +
6740 +      OsFunc->SendComplete(CurrentTcb->OsInfo);
6741 +
6742 +      /* Push Tcb(s) back onto the stack */
6743 +      CurrentTcb = LastTcbProcessed->Next;
6744 +
6745 +      LastTcbProcessed->Next=HalDev->TcbPool[Ch][Queue];
6746 +
6747 +      HalDev->TcbPool[Ch][Queue]=FirstTcbProcessed;
6748 +
6749 +      PacketsServiced++;
6750 +
6751 +      TxFrameStatus=CB_OWNERSHIP_BIT;
6752 +      /* set the first(SOP) pointer for the next packet */
6753 +      FirstTcbProcessed = CurrentTcb;
6754 +      if (CurrentTcb)
6755 +        {
6756 +         osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
6757 +         TxFrameStatus=CurrentTcb->mode;
6758 +        }
6759 +
6760 +      }while(((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6761 +             &&(PacketsServiced<TxServiceMax));
6762 +
6763 +    if (((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6764 +             &&(PacketsServiced==TxServiceMax))
6765 +      {
6766 +       *MoreWork = 1;
6767 +      }
6768 +     else
6769 +      {
6770 +       *MoreWork = 0;
6771 +      }
6772 +    }
6773 +    OsFunc->CriticalOff();
6774 +
6775 +  return(EC_NO_ERRORS);
6776 +  }
6777 +
6778 +/**
6779 + *  @ingroup CPHAL_Functions
6780 + *  This function performs a teardown for the given channel.  The value of the
6781 + *  Mode parameter controls the operation of the function, as documented below.
6782 + *
6783 + *  Note: If bit 3 of Mode is set, this call is blocking, and will not return
6784 + *  until the teardown interrupt has occurred and been processed. While waiting
6785 + *  for a blocking teardown to complete, ChannelTeardown() will signal the OS
6786 + *  (via Control(.."Sleep"..)) to allow the OS to perform other tasks if
6787 + *  necessary.  If and only if bit 3 of Mode is clear, the CPHAL will call the
6788 + *  OS TeardownComplete() function to indicate that the teardown has completed.
6789 + *
6790 + *  @param   HalDev  CPHAL module instance. (set by xxxInitModule())
6791 + *  @param   Ch      Channel number.
6792 + *  @param   Mode    Bit 0 (LSB): Perform Tx teardown (if set).<BR>
6793 + *                   Bit 1: Perform Rx teardown (if set). <BR>
6794 + *                   Bit 2: If set, perform full teardown (free buffers/descriptors).
6795 + *                          If clear, perform partial teardown (keep buffers). <BR>
6796 + *                   Bit 3 (MSB): If set, call is blocking.
6797 + *                            If clear, call is non-blocking.
6798 + *
6799 + *  @return  EC_NO_ERRORS (ok). <BR>
6800 + *           Possible Error Codes:<BR>
6801 + *           @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6802 + *           @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
6803 + *           @ref EC_VAL_TX_TEARDOWN_ALREADY_PEND "EC_VAL_TX_TEARDOWN_ALREADY_PEND"<BR>
6804 + *           @ref EC_VAL_RX_TEARDOWN_ALREADY_PEND "EC_VAL_RX_TEARDOWN_ALREADY_PEND"<BR>
6805 + *           @ref EC_VAL_TX_CH_ALREADY_TORNDOWN "EC_VAL_TX_CH_ALREADY_TORNDOWN"<BR>
6806 + *           @ref EC_VAL_RX_CH_ALREADY_TORNDOWN "EC_VAL_RX_CH_ALREADY_TORNDOWN"<BR>
6807 + *           @ref EC_VAL_TX_TEARDOWN_TIMEOUT "EC_VAL_TX_TEARDOWN_TIMEOUT"<BR>
6808 + *           @ref EC_VAL_RX_TEARDOWN_TIMEOUT "EC_VAL_RX_TEARDOWN_TIMEOUT"<BR>
6809 + *           @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
6810 + */
6811 +static int halChannelTeardown(HAL_DEVICE *HalDev, int Ch, bit32 Mode)
6812 +  {
6813 +   int DoTx, DoRx, Sleep=2048, timeout=0;                         /*MJH~030306*/
6814 +   bit32u base = HalDev->dev_base;
6815 +
6816 +/* Set the module, used for error returns */
6817 +
6818 +   DoTx = (Mode & TX_TEARDOWN);
6819 +   DoRx = (Mode & RX_TEARDOWN);
6820 +
6821 +   if (HalDev->State < enInitialized)
6822 +     return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_STATE);
6823 +
6824 +   if ((Ch < 0) || (Ch > (MAX_CHAN-1) ))
6825 +     {
6826 +     return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_CH);
6827 +     }
6828 +
6829 +   /* set teardown pending bits before performing the teardown, because they
6830 +      will be used in the int handler (this is done for AAL5) */
6831 +   if (DoTx)
6832 +     {
6833 +      if (HalDev->TxTeardownPending[Ch] != 0)
6834 +        return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_ALREADY_PEND);
6835 +
6836 +      /* If a full teardown, this also means that the user must
6837 +      setup all channels again to use them */
6838 +      if (Mode & FULL_TEARDOWN)
6839 +        HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
6840 +
6841 +      if (HalDev->State < enOpened)
6842 +        {
6843 +         /* if the hardware has never been opened, the channel has never actually
6844 +         been setup in the hardware, so I just need to reset the software flag
6845 +         and leave */
6846 +         HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
6847 +         return (EC_NO_ERRORS);
6848 +    }
6849 +       else
6850 +    {
6851 +         if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0)
6852 +       {
6853 +            return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_CH_ALREADY_TORNDOWN);
6854 +       }
6855 +
6856 +         /* set teardown flag */
6857 +         HalDev->TxTeardownPending[Ch] = Mode;
6858 +    }
6859 +     }
6860 +
6861 +   if (DoRx)
6862 +     {
6863 +      if (HalDev->RxTeardownPending[Ch] != 0)
6864 +        return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_ALREADY_PEND);
6865 +
6866 +      if (Mode & FULL_TEARDOWN)
6867 +        HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
6868 +
6869 +      if (HalDev->State < enOpened)
6870 +        {
6871 +         HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
6872 +         return (EC_NO_ERRORS);
6873 +    }
6874 +       else
6875 +    {
6876 +         if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == 0)
6877 +           return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_CH_ALREADY_TORNDOWN);
6878 +
6879 +         HalDev->RxTeardownPending[Ch] = Mode;
6880 +    }
6881 +     }
6882 +
6883 +   /* Perform Tx Teardown Duties */
6884 +   if ((DoTx) && (HalDev->State == enOpened))
6885 +     {
6886 +      /* Request TX channel teardown */
6887 +      (CPMAC_TX_TEARDOWN( base ))  = Ch;
6888 +
6889 +      /* wait until teardown has completed */
6890 +      if (Mode & BLOCKING_TEARDOWN)
6891 +        {
6892 +     timeout = 0;
6893 +         while (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
6894 +       {
6895 +            osfuncSleep(&Sleep);
6896 +
6897 +            timeout++;
6898 +        if (timeout > 100000)
6899 +          {
6900 +               return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_TIMEOUT);
6901 +          }
6902 +       }
6903 +    }
6904 +     } /* if DoTx */
6905 +
6906 +   /* Perform Rx Teardown Duties */
6907 +   if ((DoRx) && (HalDev->State == enOpened))
6908 +     {
6909 +
6910 +      /* perform CPMAC specific RX channel teardown */
6911 +      CPMAC_RX_TEARDOWN(base) = Ch;
6912 +
6913 +      if (Mode & BLOCKING_TEARDOWN)
6914 +        {
6915 +     timeout = 0;
6916 +         while (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
6917 +       {
6918 +            osfuncSleep(&Sleep);
6919 +
6920 +            timeout++;
6921 +        if (timeout > 100000)
6922 +          {
6923 +               return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_TIMEOUT);
6924 +          }
6925 +       }
6926 +        }
6927 +     } /* if DoRx */
6928 +
6929 +   return (EC_NO_ERRORS);
6930 +  }
6931 +
6932 +/**
6933 + *  @ingroup CPHAL_Functions
6934 + *  This function closes the CPHAL module.  The module will be reset.
6935 + *  The Mode parameter should be used to determine the actions taken by
6936 + *  Close().
6937 + *
6938 + *  @param   HalDev   CPHAL module instance. (set by xxxInitModule())
6939 + *  @param   Mode     Indicates actions to take on close.  The following integer
6940 + *                    values are valid: <BR>
6941 + *                    1:  Does not free buffer resources, init parameters remain
6942 + *                        intact.  User can then call Open() without calling Init()
6943 + *                        to attempt to reset the device and bring it back to the
6944 + *                        last known state.<BR>
6945 + *                    2:  Frees the buffer resources, but keeps init parameters.  This
6946 + *                        option is a more aggressive means of attempting a device reset.
6947 + *                    3:  Frees the buffer resources, and clears all init parameters. <BR>
6948 + *                        At this point, the caller would have to call to completely
6949 + *                        reinitialize the device (Init()) before being able to call
6950 + *                        Open().  Use this mode if you are shutting down the module
6951 + *                        and do not plan to restart.
6952 + *
6953 + *  @return  EC_NO_ERRORS (ok).<BR>
6954 + *           Possible Error Codes:<BR>
6955 + *           @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6956 + *           Any error code from halChannelTeardown().<BR>
6957 + */
6958 +static int halClose(HAL_DEVICE *HalDev, bit32 Mode)
6959 +  {
6960 +   int Ch, Inst, Ret;
6961 +   OS_DEVICE *TmpOsDev;
6962 +   OS_FUNCTIONS *TmpOsFunc;
6963 +   HAL_FUNCTIONS *TmpHalFunc;
6964 +   char *TmpDeviceInfo;
6965 +
6966 +   int Ticks;                                                     /*MJH~030306*/
6967 +
6968 +   /* Verify proper device state */
6969 +   if (HalDev->State != enOpened)
6970 +     return (EC_CPMAC  | EC_FUNC_CLOSE|EC_VAL_INVALID_STATE);
6971 +
6972 +   /* Teardown all open channels */
6973 +   for (Ch = 0; Ch <= (MAX_CHAN-1) ; Ch++)
6974 +     {
6975 +      if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
6976 +        {
6977 +         if (Mode == 1)
6978 +           {
6979 +            Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
6980 +            if (Ret) return (Ret);
6981 +           }
6982 +          else
6983 +           {
6984 +            Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
6985 +            if (Ret) return (Ret);
6986 +           }
6987 +        }
6988 +
6989 +      if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
6990 +        {
6991 +         if (Mode == 1)
6992 +           {
6993 +            Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
6994 +            if (Ret) return (Ret);
6995 +           }
6996 +          else
6997 +           {
6998 +            Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
6999 +            if (Ret) return (Ret);
7000 +           }
7001 +        }
7002 +     }
7003 +
7004 +   /* free fraglist in HalDev */
7005 +   HalDev->OsFunc->Free(HalDev->fraglist);
7006 +   HalDev->fraglist = 0;
7007 +
7008 +   /* unregister the interrupt */
7009 +   HalDev->OsFunc->IsrUnRegister(HalDev->OsDev, HalDev->interrupt);
7010 +
7011 +   Ticks = 0;    /* Disable Tick Timer */                           /*MJH+030306*/
7012 +   HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcClear, &Ticks); /*MJH+030306*/
7013 +
7014 +   /* Free the Phy Information Structure */
7015 +   if(HalDev->PhyDev)
7016 +   {
7017 +      HalDev->OsFunc->Free(HalDev->PhyDev);                               /*MJH+030513*/
7018 +      HalDev->PhyDev = 0;                                         /*MJH+030522*/
7019 +   }
7020 +
7021 +   /* Perform CPMAC specific closing functions */
7022 +   CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
7023 +   CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
7024 +   CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
7025 +
7026 +   /* put device back into reset */
7027 +   (*(volatile bit32u *)(HalDev->ResetBase)) &=~ (1<<HalDev->ResetBit);
7028 +   Ticks = 64;                                                    /*MJH~030306*/
7029 +   osfuncSleep(&Ticks);
7030 +
7031 +   /* If mode is 3, than clear the HalDev and set next state to DevFound*/
7032 +   if (Mode == 3)
7033 +     {
7034 +      /* I need to keep the HalDev parameters that were setup in InitModule */
7035 +      TmpOsDev = HalDev->OsDev;
7036 +      TmpOsFunc = HalDev->OsFunc;
7037 +      TmpDeviceInfo = HalDev->DeviceInfo;
7038 +
7039 +      TmpHalFunc = HalDev->HalFuncPtr;
7040 +      Inst = HalDev->Inst;
7041 +
7042 +      /* Clear HalDev */
7043 +
7044 +      HalDev->OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
7045 +
7046 +      /* Restore key parameters */
7047 +      HalDev->OsDev = TmpOsDev;
7048 +      HalDev->OsFunc = TmpOsFunc;
7049 +      HalDev->DeviceInfo = TmpDeviceInfo;
7050 +
7051 +      HalDev->HalFuncPtr = TmpHalFunc;
7052 +      HalDev->Inst = Inst;
7053 +
7054 +      HalDev->State = enDevFound;
7055 +     }
7056 +    else
7057 +     {
7058 +      HalDev->State = enInitialized;
7059 +     }
7060 +
7061 +   return(EC_NO_ERRORS);
7062 +  }
7063 diff -urN linux.old/drivers/net/avalanche_cpmac/cpremap_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpremap_cpmac.c
7064 --- linux.old/drivers/net/avalanche_cpmac/cpremap_cpmac.c       1970-01-01 01:00:00.000000000 +0100
7065 +++ linux.dev/drivers/net/avalanche_cpmac/cpremap_cpmac.c       2005-07-12 02:48:42.049593000 +0200
7066 @@ -0,0 +1,28 @@
7067 +#ifndef _INC_CPREMAP_C
7068 +#define _INC_CPREMAP_C
7069 +
7070 +#ifdef __ADAM2
7071 +static inline void osfuncDataCacheHitInvalidate(void *ptr, int Size)
7072 +  {
7073 +  asm(" cache  17, (%0)" : : "r" (ptr));
7074 +  }
7075 +
7076 +static inline void osfuncDataCacheHitWriteback(void *ptr, int Size)
7077 +  {
7078 +  asm(" cache  25, (%0)" : : "r" (ptr));
7079 +  }
7080 +
7081 +static inline void osfuncDataCacheHitWritebackAndInvalidate(void *ptr, int Size)
7082 +  {
7083 +  asm(" cache  21, (%0)" : : "r" (ptr));
7084 +  }
7085 +
7086 +#else
7087 +
7088 +#define osfuncDataCacheHitInvalidate(MemPtr, Size)               __asm__(" .set mips3; cache  17, (%0); .set mips0" : : "r" (MemPtr))
7089 +#define osfuncDataCacheHitWritebackAndInvalidate(MemPtr, Size)   __asm__(" .set mips3; cache  21, (%0); .set mips0" : : "r" (MemPtr))
7090 +#define osfuncDataCacheHitWriteback(MemPtr, Size)                __asm__(" .set mips3; cache  25, (%0); .set mips0" : : "r" (MemPtr))
7091 +
7092 +#endif
7093 +
7094 +#endif
7095 diff -urN linux.old/drivers/net/avalanche_cpmac/cpswhal_cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpswhal_cpmac.h
7096 --- linux.old/drivers/net/avalanche_cpmac/cpswhal_cpmac.h       1970-01-01 01:00:00.000000000 +0100
7097 +++ linux.dev/drivers/net/avalanche_cpmac/cpswhal_cpmac.h       2005-07-12 02:48:42.050593000 +0200
7098 @@ -0,0 +1,632 @@
7099 +/************************************************************************
7100 + *  TNETDxxxx Software Support
7101 + *  Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
7102 + *
7103 + *  FILE: cphal.h
7104 + *
7105 + *  DESCRIPTION:
7106 + *      User include file, contains data definitions shared between the CPHAL
7107 + *      and the upper-layer software.
7108 + *
7109 + *  HISTORY:
7110 + *      Date      Modifier  Ver    Notes
7111 + *      28Feb02   Greg      1.00   Original
7112 + *      06Mar02   Greg      1.01   Documentation enhanced
7113 + *      18Jul02   Greg      1.02   Many updates (OAM additions, general reorg)
7114 + *      22Nov02   Mick      RC2    Additions from Denis' input on Control
7115 + *
7116 + *  author  Greg Guyotte
7117 + *  version 1.02
7118 + *  date    18-Jul-2002
7119 + *****************************************************************************/
7120 +#ifndef _INC_CPHAL_H
7121 +#define _INC_CPHAL_H
7122 +
7123 +#ifdef _CPHAL_CPMAC
7124 +#include "ec_errors_cpmac.h"
7125 +#endif
7126 +
7127 +#ifdef _CPHAL_AAL5
7128 +#include "ec_errors_cpaal5.h"
7129 +#endif
7130 +
7131 +#ifdef _CPHAL_CPSAR
7132 +#include "ec_errors_cpsar.h"
7133 +#endif
7134 +
7135 +#ifdef _CPHAL_AAL2
7136 +#include "ec_errors_cpaal2.h"
7137 +#endif
7138 +
7139 +#ifndef __ADAM2
7140 +typedef char           bit8;
7141 +typedef short          bit16;
7142 +typedef int            bit32;
7143 +
7144 +typedef unsigned char  bit8u;
7145 +typedef unsigned short bit16u;
7146 +typedef unsigned int   bit32u;
7147 +
7148 +/*
7149 +typedef char           INT8;
7150 +typedef short          INT16;
7151 +typedef int            INT32;
7152 +typedef unsigned char  UINT8;
7153 +typedef unsigned short UINT16;
7154 +typedef unsigned int   UINT32;
7155 +*/
7156 +/*typedef unsigned int   size_t;*/
7157 +#endif
7158 +
7159 +#ifdef _CPHAL
7160 +
7161 +#ifndef TRUE
7162 +#define TRUE (1==1)
7163 +#endif
7164 +
7165 +#ifndef FALSE
7166 +#define FALSE (1==2)
7167 +#endif
7168 +
7169 +#ifndef NULL
7170 +#define NULL 0
7171 +#endif
7172 +
7173 +#endif
7174 +
7175 +#define        VirtToPhys(a)                 (((int)a)&~0xe0000000)
7176 +#define        VirtToVirtNoCache(a)          ((void*)((VirtToPhys(a))|0xa0000000))
7177 +#define        VirtToVirtCache(a)            ((void*)((VirtToPhys(a))|0x80000000))
7178 +#define        PhysToVirtNoCache(a)          ((void*)(((int)a)|0xa0000000))
7179 +#define        PhysToVirtCache(a)            ((void*)(((int)a)|0x80000000))
7180 +/*
7181 +#define        DataCacheHitInvalidate(a)     {__asm__(" cache  17, (%0)" :   : "r" (a));}
7182 +#define        DataCacheHitWriteback(a)      {__asm__(" cache  25, (%0)" :   : "r" (a));}
7183 +*/
7184 +
7185 +#define PARTIAL 1     /**< Used in @c Close() and @c ChannelTeardown() */
7186 +#define FULL 2        /**< Used in @c Close() and @c ChannelTeardown() */
7187 +
7188 +/* Channel Teardown Defines */
7189 +#define RX_TEARDOWN 2
7190 +#define TX_TEARDOWN 1
7191 +#define BLOCKING_TEARDOWN 8
7192 +#define FULL_TEARDOWN 4
7193 +#define PARTIAL_TEARDOWN 0
7194 +
7195 +#define MAX_DIR 2
7196 +#define DIRECTION_TX 0
7197 +#define DIRECTION_RX 1
7198 +#define TX_CH 0
7199 +#define RX_CH 1
7200 +#define HAL_ERROR_DEVICE_NOT_FOUND    1
7201 +#define HAL_ERROR_FAILED_MALLOC       2
7202 +#define HAL_ERROR_OSFUNC_SIZE         3
7203 +#define HAL_DEFAULT  0xFFFFFFFF
7204 +#define VALID(val)    (val!=HAL_DEFAULT)
7205 +
7206 +/*
7207 +ERROR REPORTING
7208 +
7209 +HAL Module Codes.  Each HAL module reporting an error code
7210 +should OR the error code with the respective Module error code
7211 +from the list below.
7212 +*/
7213 +#define EC_AAL5                                EC_HAL|EC_DEV_AAL5
7214 +#define EC_AAL2                                EC_HAL|EC_DEV_AAL2
7215 +#define EC_CPSAR                               EC_HAL|EC_DEV_CPSAR
7216 +#define EC_CPMAC                               EC_HAL|EC_DEV_CPMAC
7217 +#define EC_VDMA                                EC_HAL|EC_DEV_VDMA
7218 +#define EC_VLYNQ                               EC_HAL|EC_DEV_VLYNQ
7219 +#define EC_CPPI                                EC_HAL|EC_DEV_CPPI
7220 +
7221 +/*
7222 +HAL Function Codes.  Each HAL module reporting an error code
7223 +should OR the error code with one of the function codes from
7224 +the list below.
7225 +*/
7226 +#define EC_FUNC_HAL_INIT                       EC_FUNC(1)
7227 +#define EC_FUNC_CHSETUP                        EC_FUNC(2)
7228 +#define EC_FUNC_CHTEARDOWN                     EC_FUNC(3)
7229 +#define EC_FUNC_RXRETURN                       EC_FUNC(4)
7230 +#define EC_FUNC_SEND                           EC_FUNC(5)
7231 +#define EC_FUNC_RXINT                          EC_FUNC(6)
7232 +#define EC_FUNC_TXINT                          EC_FUNC(7)
7233 +#define EC_FUNC_AAL2_VDMA                      EC_FUNC(8)
7234 +#define EC_FUNC_OPTIONS                        EC_FUNC(9)
7235 +#define EC_FUNC_PROBE                          EC_FUNC(10)
7236 +#define EC_FUNC_OPEN                           EC_FUNC(11)
7237 +#define EC_FUNC_CONTROL                        EC_FUNC(12)
7238 +#define EC_FUNC_DEVICE_INT                     EC_FUNC(13)
7239 +#define EC_FUNC_STATUS                         EC_FUNC(14)
7240 +#define EC_FUNC_TICK                           EC_FUNC(15)
7241 +#define EC_FUNC_CLOSE                          EC_FUNC(16)
7242 +#define EC_FUNC_SHUTDOWN                       EC_FUNC(17)
7243 +#define EC_FUNC_DEVICE_INT_ALT                 EC_FUNC(18) /* +GSG 030306 */
7244 +
7245 +/*
7246 +HAL Error Codes.  The list below defines every type of error
7247 +used in all HAL modules. DO NOT CHANGE THESE VALUES!  Add new
7248 +values in integer order to the bottom of the list.
7249 +*/
7250 +#define EC_VAL_PDSP_LOAD_FAIL                 EC_ERR(0x01)|EC_CRITICAL
7251 +#define EC_VAL_FIRMWARE_TOO_LARGE             EC_ERR(0x02)|EC_CRITICAL
7252 +#define EC_VAL_DEVICE_NOT_FOUND               EC_ERR(0x03)|EC_CRITICAL
7253 +#define EC_VAL_BASE_ADDR_NOT_FOUND            EC_ERR(0x04)|EC_CRITICAL
7254 +#define EC_VAL_RESET_BIT_NOT_FOUND            EC_ERR(0x05)|EC_CRITICAL
7255 +#define EC_VAL_CH_INFO_NOT_FOUND              EC_ERR(0x06)
7256 +#define EC_VAL_RX_STATE_RAM_NOT_CLEARED       EC_ERR(0x07)|EC_CRITICAL
7257 +#define EC_VAL_TX_STATE_RAM_NOT_CLEARED       EC_ERR(0x08)|EC_CRITICAL
7258 +#define EC_VAL_MALLOC_DEV_FAILED              EC_ERR(0x09)
7259 +#define EC_VAL_OS_VERSION_NOT_SUPPORTED       EC_ERR(0x0A)|EC_CRITICAL
7260 +#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED    EC_ERR(0x0B)|EC_CRITICAL
7261 +#define EC_VAL_NULL_CPSAR_DEV                 EC_ERR(0x0C)|EC_CRITICAL
7262 +
7263 +#define EC_VAL_LUT_NOT_READY                  EC_ERR(0x0D)
7264 +#define EC_VAL_INVALID_CH                     EC_ERR(0x0E)
7265 +#define EC_VAL_NULL_CH_STRUCT                 EC_ERR(0x0F)
7266 +#define EC_VAL_RX_TEARDOWN_ALREADY_PEND       EC_ERR(0x10)
7267 +#define EC_VAL_TX_TEARDOWN_ALREADY_PEND       EC_ERR(0x11)
7268 +#define EC_VAL_RX_CH_ALREADY_TORNDOWN         EC_ERR(0x12)
7269 +#define EC_VAL_TX_CH_ALREADY_TORNDOWN         EC_ERR(0x13)
7270 +#define EC_VAL_TX_TEARDOWN_TIMEOUT            EC_ERR(0x14)
7271 +#define EC_VAL_RX_TEARDOWN_TIMEOUT            EC_ERR(0x15)
7272 +#define EC_VAL_CH_ALREADY_TORNDOWN            EC_ERR(0x16)
7273 +#define EC_VAL_VC_SETUP_NOT_READY             EC_ERR(0x17)
7274 +#define EC_VAL_VC_TEARDOWN_NOT_READY          EC_ERR(0x18)
7275 +#define EC_VAL_INVALID_VC                     EC_ERR(0x19)
7276 +#define EC_VAL_INVALID_LC                     EC_ERR(0x20)
7277 +#define EC_VAL_INVALID_VDMA_CH                EC_ERR(0x21)
7278 +#define EC_VAL_INVALID_CID                    EC_ERR(0x22)
7279 +#define EC_VAL_INVALID_UUI                    EC_ERR(0x23)
7280 +#define EC_VAL_INVALID_UUI_DISCARD            EC_ERR(0x24)
7281 +#define EC_VAL_CH_ALREADY_OPEN                EC_ERR(0x25)
7282 +
7283 +#define EC_VAL_RCB_MALLOC_FAILED              EC_ERR(0x26)
7284 +#define EC_VAL_RX_BUFFER_MALLOC_FAILED        EC_ERR(0x27)
7285 +#define EC_VAL_OUT_OF_TCBS                    EC_ERR(0x28)
7286 +#define EC_VAL_NO_TCBS                        EC_ERR(0x29)
7287 +#define EC_VAL_NULL_RCB                       EC_ERR(0x30)|EC_CRITICAL
7288 +#define EC_VAL_SOP_ERROR                      EC_ERR(0x31)|EC_CRITICAL
7289 +#define EC_VAL_EOP_ERROR                      EC_ERR(0x32)|EC_CRITICAL
7290 +#define EC_VAL_NULL_TCB                       EC_ERR(0x33)|EC_CRITICAL
7291 +#define EC_VAL_CORRUPT_RCB_CHAIN              EC_ERR(0x34)|EC_CRITICAL
7292 +#define EC_VAL_TCB_MALLOC_FAILED              EC_ERR(0x35)
7293 +
7294 +#define EC_VAL_DISABLE_POLLING_FAILED         EC_ERR(0x36)
7295 +#define EC_VAL_KEY_NOT_FOUND                  EC_ERR(0x37)
7296 +#define EC_VAL_MALLOC_FAILED                  EC_ERR(0x38)
7297 +#define EC_VAL_RESET_BASE_NOT_FOUND           EC_ERR(0x39)|EC_CRITICAL
7298 +#define EC_VAL_INVALID_STATE                  EC_ERR(0x40)
7299 +#define EC_VAL_NO_TXH_WORK_TO_DO              EC_ERR(0x41)
7300 +#define EC_VAL_NO_TXL_WORK_TO_DO              EC_ERR(0x42)
7301 +#define EC_VAL_NO_RX_WORK_TO_DO               EC_ERR(0x43)
7302 +#define EC_VAL_NOT_LINKED                     EC_ERR(0x44)
7303 +#define EC_VAL_INTERRUPT_NOT_FOUND            EC_ERR(0x45)
7304 +#define EC_VAL_OFFSET_NOT_FOUND               EC_ERR(0x46)
7305 +#define EC_VAL_MODULE_ALREADY_CLOSED          EC_ERR(0x47)
7306 +#define EC_VAL_MODULE_ALREADY_SHUTDOWN        EC_ERR(0x48)
7307 +#define EC_VAL_ACTION_NOT_FOUND               EC_ERR(0x49)
7308 +#define EC_VAL_RX_CH_ALREADY_SETUP            EC_ERR(0x50)
7309 +#define EC_VAL_TX_CH_ALREADY_SETUP            EC_ERR(0x51)
7310 +#define EC_VAL_RX_CH_ALREADY_OPEN             EC_ERR(0x52)
7311 +#define EC_VAL_TX_CH_ALREADY_OPEN             EC_ERR(0x53)
7312 +#define EC_VAL_CH_ALREADY_SETUP               EC_ERR(0x54)
7313 +#define EC_VAL_RCB_NEEDS_BUFFER               EC_ERR(0x55) /* +GSG 030410 */
7314 +#define EC_VAL_RCB_DROPPED                    EC_ERR(0x56) /* +GSG 030410 */
7315 +#define EC_VAL_INVALID_VALUE                  EC_ERR(0x57)
7316 +
7317 +/**
7318 +@defgroup shared_data Shared Data Structures
7319 +
7320 +The data structures documented here are shared by all modules.
7321 +*/
7322 +
7323 +/**
7324 + *  @ingroup shared_data
7325 + *  This is the fragment list structure.  Each fragment list entry contains a
7326 + *  length and a data buffer.
7327 + */
7328 +typedef struct
7329 +  {
7330 +   bit32u   len;    /**< Length of the fragment in bytes (lower 16 bits are valid).  For SOP, upper 16 bits is the buffer offset. */
7331 +   void     *data;  /**< Pointer to fragment data. */
7332 +   void     *OsInfo; /**< Pointer to OS defined data. */
7333 +  }FRAGLIST;
7334 +
7335 +#if defined (_CPHAL_CPMAC)
7336 +#define CB_PASSCRC_BIT     (1<<26)
7337 +
7338 +/* CPMAC CPHAL STATUS */
7339 +#define CPMAC_STATUS_LINK               (1 << 0)
7340 +#define CPMAC_STATUS_LINK_DUPLEX        (1 << 1)  /* 0 - HD, 1 - FD */
7341 +#define CPMAC_STATUS_LINK_SPEED         (1 << 2)  /* 0 - 10, 1 - 100 */
7342 +
7343 +/*   ADAPTER CHECK Codes */
7344 +
7345 +#define CPMAC_STATUS_ADAPTER_CHECK             (1 << 7)
7346 +#define CPMAC_STATUS_HOST_ERR_DIRECTION        (1 << 8)
7347 +#define CPMAC_STATUS_HOST_ERR_CODE             (0xF << 9)
7348 +#define CPMAC_STATUS_HOST_ERR_CH               (0x7 << 13)
7349 +
7350 +#define _CPMDIO_DISABLE                 (1 << 0)
7351 +#define _CPMDIO_HD                      (1 << 1)
7352 +#define _CPMDIO_FD                      (1 << 2)
7353 +#define _CPMDIO_10                      (1 << 3)
7354 +#define _CPMDIO_100                     (1 << 4)
7355 +#define _CPMDIO_NEG_OFF                 (1 << 5)
7356 +#define _CPMDIO_LOOPBK                  (1 << 16)
7357 +#define _CPMDIO_AUTOMDIX                (1 << 17)   /* Bit 16 and above not used by MII register */
7358 +#define _CPMDIO_NOPHY                   (1 << 20)
7359 +#endif
7360 +
7361 +/**
7362 + *  @ingroup shared_data
7363 + *  Channel specific configuration information.  This structure should be
7364 + *  populated by upper-layer software prior to calling @c ChannelSetup().  Any
7365 + *  configuration item that can be changed on a per channel basis should
7366 + *  be represented here.  Each module may define this structure with additional
7367 + *  module-specific members.
7368 + */
7369 +typedef struct
7370 +  {
7371 +   int Channel;        /**< Channel number. */
7372 +   int Direction;      /**< DIRECTION_RX(1) or DIRECTION_TX(0). */
7373 +   OS_SETUP *OsSetup;  /**< OS defined information associated with this channel. */
7374 +
7375 +#if defined(_CPHAL_AAL5) || defined (_CPHAL_CPSAR) || defined (_CPHAL_CPMAC)
7376 +   int RxBufSize;      /**< Size (in bytes) for each Rx buffer.*/
7377 +   int RxBufferOffset; /**< Number of bytes to offset rx data from start of buffer (must be less than buffer size). */
7378 +   int RxNumBuffers;   /**< The number of Rx buffer descriptors to allocate for Ch. */
7379 +   int RxServiceMax;   /**< Maximum number of packets to service at one time. */
7380 +
7381 +   int TxNumBuffers;   /**< The number of Tx buffer descriptors to allocate for Ch. */
7382 +   int TxNumQueues;    /**< Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue. */
7383 +   int TxServiceMax;   /**< Maximum number of packets to service at one time. */
7384 +#endif
7385 +
7386 +#if defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7387 +   int CpcsUU;      /**< The 2-byte CPCS UU and CPI information. */
7388 +   int Gfc;         /**< Generic Flow Control. */
7389 +   int Clp;         /**< Cell Loss Priority. */
7390 +   int Pti;         /**< Payload Type Indication. */
7391 +#endif
7392 +
7393 +#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7394 +   int DaMask;      /**< Specifies whether credit issuance is paused when Tx data not available. */
7395 +   int Priority;    /**< Priority bin this channel will be scheduled within. */
7396 +   int PktType;     /**< 0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2. */
7397 +   int Vci;         /**< Virtual Channel Identifier. */
7398 +   int Vpi;         /**< Virtual Path Identifier. */
7399 +   int FwdUnkVc;    /**< Enables forwarding of unknown VCI/VPI cells to host. 1=enable, 0=disable. */
7400 +
7401 +   /* Tx VC State */
7402 +   int TxVc_CellRate;  /**< Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR). */
7403 +   int TxVc_QosType;   /**< 0=CBR,1=VBR,2=UBR,3=UBRmcr. */
7404 +   int TxVc_Mbs;       /**< Min Burst Size in cells.*/
7405 +   int TxVc_Pcr;       /**< Peak Cell Rate for VBR in clock ticks between transmissions. */
7406 +
7407 +   bit32 TxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Tx Ch (must be big endian with 0 PTI). */
7408 +   int TxVc_OamTc;     /**< TC Path to transmit OAM cells for TX connection (0,1). */
7409 +   int TxVc_VpOffset;  /**< Offset to the OAM VP state table. */
7410 +   /* Rx VC State */
7411 +   int RxVc_OamCh;     /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
7412 +   int RxVc_OamToHost; /**< 0=do not pass, 1=pass. */
7413 +   bit32 RxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx conn (must be big endian with 0 PTI). */
7414 +   int RxVc_OamTc;     /**< TC Path to transmit OAM cells for RX connection (0,1). */
7415 +   int RxVc_VpOffset;  /**< Offset to the OAM VP state table. */
7416 +   /* Tx VP State */
7417 +   int TxVp_OamTc;     /**< TC Path to transmit OAM cells for TX VP connection (0,1). */
7418 +   bit32 TxVp_AtmHeader; /**< ATM Header placed on firmware gen'd VP OAM cells for this Tx VP conn (must be big endian with 0 VCI). */
7419 +   /* Rx VP State  */
7420 +   int RxVp_OamCh;     /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
7421 +   int RxVp_OamToHost; /**< 0=do not pass, 1=pass. */
7422 +   bit32 RxVp_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx VP conn (must be big endian with 0 VCI). */
7423 +   int RxVp_OamTc;     /**< TC Path to transmit OAM cells for RX VP connection (0,1). */
7424 +   int RxVp_OamVcList; /**< Indicates all VC channels associated with this VP channel (one-hot encoded). */
7425 +#endif
7426 +
7427 +
7428 +#ifdef _CPHAL_VDMAVT
7429 +   bit32u RemFifoAddr; /* Mirror mode only. */
7430 +   bit32u FifoAddr;
7431 +   bit32  PollInt;
7432 +   bit32  FifoSize;
7433 +   int    Ready;
7434 +#endif
7435 +
7436 +  }CHANNEL_INFO;
7437 +
7438 +/*
7439 + *  This structure contains each statistic value gathered by the CPHAL.
7440 + *  Applications may access statistics data by using the @c StatsGet() routine.
7441 + */
7442 +/* STATS */
7443 +#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7444 +typedef struct
7445 +  {
7446 +   bit32u CrcErrors[16];
7447 +   bit32u LenErrors[16];
7448 +   bit32u DmaLenErrors[16];
7449 +   bit32u AbortErrors[16];
7450 +   bit32u StarvErrors[16];
7451 +   bit32u TxMisQCnt[16][2];
7452 +   bit32u RxMisQCnt[16];
7453 +   bit32u RxEOQCnt[16];
7454 +   bit32u TxEOQCnt[16][2];
7455 +   bit32u RxPacketsServiced[16];
7456 +   bit32u TxPacketsServiced[16][2];
7457 +   bit32u RxMaxServiced;
7458 +   bit32u TxMaxServiced[16][2];
7459 +   bit32u RxTotal;
7460 +   bit32u TxTotal;
7461 +  } STAT_INFO;
7462 +#endif
7463 +
7464 +/*
7465 + *  VDMA Channel specific configuration information
7466 + */
7467 +#ifdef _CPHAL_AAL2
7468 +typedef struct
7469 +  {
7470 +   int Ch;           /**< Channel Number */
7471 +   int RemoteEndian; /**< Endianness of remote VDMA-VT device */
7472 +   int CpsSwap;      /**< When 0, octet 0 in CPS pkt located in LS byte of 16-bit word sent to rem VDMA device.  When 1, in MS byte. */
7473 +  }VdmaChInfo;
7474 +#endif
7475 +
7476 +#ifndef _CPHAL
7477 +  typedef void HAL_DEVICE;
7478 +  typedef void HAL_PRIVATE;
7479 +  typedef void HAL_RCB;
7480 +  typedef void HAL_RECEIVEINFO;
7481 +#endif
7482 +
7483 +/**
7484 + *  @ingroup shared_data
7485 + *  The HAL_FUNCTIONS struct defines the function pointers used by upper layer
7486 + *  software.  The upper layer software receives these pointers through the
7487 + *  call to xxxInitModule().
7488 + */
7489 +typedef struct
7490 +  {
7491 +  int  (*ChannelSetup)    (HAL_DEVICE *HalDev, CHANNEL_INFO *Channel, OS_SETUP *OsSetup);
7492 +  int  (*ChannelTeardown) (HAL_DEVICE *HalDev, int Channel, int Mode);
7493 +  int  (*Close)           (HAL_DEVICE *HalDev, int Mode);
7494 +  int  (*Control)         (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
7495 +  int  (*Init)            (HAL_DEVICE *HalDev);
7496 +  int  (*Open)            (HAL_DEVICE *HalDev);
7497 +  int  (*PacketProcessEnd) (HAL_DEVICE *HalDev);
7498 +  int  (*Probe)           (HAL_DEVICE *HalDev);
7499 +  int  (*RxReturn)        (HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
7500 +  int  (*Send)            (HAL_DEVICE *HalDev, FRAGLIST *FragList, int FragCount, int PacketSize, OS_SENDINFO *OsSendInfo, bit32u Mode);
7501 +  int  (*Shutdown)        (HAL_DEVICE *HalDev);
7502 +  int  (*Tick)            (HAL_DEVICE *HalDev);
7503 +
7504 +#ifdef _CPHAL_AAL5
7505 +  int  (*Kick) (HAL_DEVICE *HalDev, int Queue);
7506 +  void (*OamFuncConfig)   (HAL_DEVICE *HalDev, unsigned int OamConfig);
7507 +  void (*OamLoopbackConfig)   (HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag);
7508 +  volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7509 +  STAT_INFO*  (*StatsGetOld)(HAL_DEVICE *HalDev);
7510 +#endif
7511 +  } HAL_FUNCTIONS;
7512 +
7513 +/**
7514 + *  @ingroup shared_data
7515 + *  The OS_FUNCTIONS struct defines the function pointers for all upper layer
7516 + *  functions accessible to the CPHAL.  The upper layer software is responsible
7517 + *  for providing the correct OS-specific implementations for the following
7518 + *  functions. It is populated by calling InitModule() (done by the CPHAL in
7519 + *  xxxInitModule().
7520 + */
7521 +typedef struct
7522 +  {
7523 +  int   (*Control)(OS_DEVICE *OsDev, const char *Key, const char *Action, void *Value);
7524 +  void  (*CriticalOn)(void);
7525 +  void  (*CriticalOff)(void);
7526 +  void  (*DataCacheHitInvalidate)(void *MemPtr, int Size);
7527 +  void  (*DataCacheHitWriteback)(void *MemPtr, int Size);
7528 +  int   (*DeviceFindInfo)(int Inst, const char *DeviceName, void *DeviceInfo);
7529 +  int   (*DeviceFindParmUint)(void *DeviceInfo, const char *Parm, bit32u *Value);
7530 +  int   (*DeviceFindParmValue)(void *DeviceInfo, const char *Parm, void *Value);
7531 +  void  (*Free)(void *MemPtr);
7532 +  void  (*FreeRxBuffer)(OS_RECEIVEINFO *OsReceiveInfo, void *MemPtr);
7533 +  void  (*FreeDev)(void *MemPtr);
7534 +  void  (*FreeDmaXfer)(void *MemPtr);
7535 +  void  (*IsrRegister)(OS_DEVICE *OsDev, int (*halISR)(HAL_DEVICE*, int*), int InterruptBit);
7536 +  void  (*IsrUnRegister)(OS_DEVICE *OsDev, int InterruptBit);
7537 +  void* (*Malloc)(bit32u size);
7538 +  void* (*MallocDev)(bit32u Size);
7539 +  void* (*MallocDmaXfer)(bit32u size, void *MemBase, bit32u MemRange);
7540 +  void* (*MallocRxBuffer)(bit32u size, void *MemBase, bit32u MemRange,
7541 +                       OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
7542 +                       OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
7543 +  void* (*Memset)(void *Dest, int C, bit32u N);
7544 +  int   (*Printf)(const char *Format, ...);
7545 +  int   (*Receive)(OS_DEVICE *OsDev,FRAGLIST *FragList,bit32u FragCount,
7546 +                 bit32u PacketSize,HAL_RECEIVEINFO *HalReceiveInfo, bit32u Mode);
7547 +  int   (*SendComplete)(OS_SENDINFO *OsSendInfo);
7548 +  int   (*Sprintf)(char *S, const char *Format, ...);
7549 +  int   (*Strcmpi)(const char *Str1, const char *Str2);
7550 +  unsigned int (*Strlen)(const char *S);
7551 +  char* (*Strstr)(const char *S1, const char *S2);
7552 +  unsigned long  (*Strtoul)(const char *Str, char **Endptr, int Base);
7553 +  void  (*TeardownComplete)(OS_DEVICE *OsDev, int Ch, int Direction);
7554 +  } OS_FUNCTIONS;
7555 +
7556 +/************** MODULE SPECIFIC STUFF BELOW **************/
7557 +
7558 +#ifdef _CPHAL_CPMAC
7559 +
7560 +/*
7561 +int halCpmacInitModule(HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc, int (*osBridgeInitModule)(OS_FUNCTIONS *), void* (*osMallocDev) (bit32u), int *Size, int inst);
7562 +*/
7563 +
7564 +int halCpmacInitModule(HAL_DEVICE **HalDev,
7565 +                 OS_DEVICE *OsDev,
7566 +                 HAL_FUNCTIONS **HalFunc,
7567 +                 OS_FUNCTIONS *OsFunc,
7568 +                 int OsFuncSize,
7569 +                 int *HalFuncSize,
7570 +                 int Inst);
7571 +#endif
7572 +
7573 +#ifdef _CPHAL_AAL5
7574 +/*
7575 + *  @ingroup shared_data
7576 + *  The AAL5_FUNCTIONS struct defines the AAL5 function pointers used by upper layer
7577 + *  software.  The upper layer software receives these pointers through the
7578 + *  call to cphalInitModule().
7579 + */
7580 +/*
7581 +typedef struct
7582 +  {
7583 +  int  (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7584 +  int  (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
7585 +  int  (*Close)(HAL_DEVICE *HalDev, int Mode);
7586 +  int  (*Init)(HAL_DEVICE *HalDev);
7587 +  int  (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
7588 +  int  (*Open)(HAL_DEVICE *HalDev);
7589 +  int  (*InfoGet)(HAL_DEVICE *HalDev, int Key, void *Value);
7590 +  int  (*Probe)(HAL_DEVICE *HalDev);
7591 +  int  (*RxReturn)(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
7592 +  int  (*Send)(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,
7593 +                 int PacketSize,OS_SENDINFO *OsSendInfo,int Ch, int Queue,
7594 +                 bit32u Mode);
7595 +  int  (*StatsClear)(HAL_DEVICE *HalDev);
7596 +  STAT_INFO*  (*StatsGet)(HAL_DEVICE *HalDev);
7597 +  int  (*Status)(HAL_DEVICE *HalDev);
7598 +  void (*Tick)(HAL_DEVICE *HalDev);
7599 +  int  (*Kick)(HAL_DEVICE *HalDev, int Queue);
7600 +  volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7601 +  } AAL5_FUNCTIONS;
7602 +*/
7603 +
7604 +int cpaal5InitModule(HAL_DEVICE **HalDev,
7605 +                 OS_DEVICE *OsDev,
7606 +                 HAL_FUNCTIONS **HalFunc,
7607 +                 OS_FUNCTIONS *OsFunc,
7608 +                 int OsFuncSize,
7609 +                 int *HalFuncSize,
7610 +                 int Inst);
7611 +#endif
7612 +
7613 +#ifdef _CPHAL_AAL2
7614 +/**
7615 + *  @ingroup shared_data
7616 + *  The AAL2_FUNCTIONS struct defines the AAL2 function pointers used by upper layer
7617 + *  software.  The upper layer software receives these pointers through the
7618 + *  call to cphalInitModule().
7619 + */
7620 +typedef struct
7621 +  {
7622 +  int  (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7623 +  int  (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
7624 +  int  (*Close)(HAL_DEVICE *HalDev, int Mode);
7625 +  int  (*Init)(HAL_DEVICE *HalDev);
7626 +  int  (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
7627 +  int  (*Open)(HAL_DEVICE *HalDev);
7628 +  int  (*OptionsGet)(HAL_DEVICE *HalDev, char *Key, bit32u *Value);
7629 +  int  (*Probe)(HAL_DEVICE *HalDev);
7630 +
7631 +  int  (*StatsClear)(HAL_DEVICE *HalDev);
7632 +  STAT_INFO*  (*StatsGet)(HAL_DEVICE *HalDev);
7633 +  int  (*Status)(HAL_DEVICE *HalDev);
7634 +  void (*Tick)(HAL_DEVICE *HalDev);
7635 +  int  (*Aal2UuiMappingSetup)(HAL_DEVICE *HalDev, int VC, int UUI,
7636 +                                    int VdmaCh, int UUIDiscard);
7637 +  int  (*Aal2RxMappingSetup)(HAL_DEVICE *HalDev, int VC, int CID,
7638 +                                   int LC);
7639 +  int  (*Aal2TxMappingSetup)(HAL_DEVICE *HalDev, int VC, int LC, int VdmaCh);
7640 +  int  (*Aal2VdmaChSetup)(HAL_DEVICE *HalDev, bit32u RemVdmaVtAddr,
7641 +                               VdmaChInfo *VdmaCh);
7642 +  volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7643 +  int  (*Aal2ModeChange)(HAL_DEVICE *HalDev, int Vc, int RxCrossMode,
7644 +                           int RxMultiMode, int TxMultiMode, int SchedMode,
7645 +                           int TcCh);
7646 +  void (*Aal2VdmaEnable)(HAL_DEVICE *HalDev, int Ch);
7647 +  int  (*Aal2VdmaDisable)(HAL_DEVICE *HalDev, int Ch);
7648 +  } AAL2_FUNCTIONS;
7649 +
7650 +int cpaal2InitModule(HAL_DEVICE **HalDev,
7651 +                 OS_DEVICE *OsDev,
7652 +                 AAL2_FUNCTIONS **HalFunc,
7653 +                 OS_FUNCTIONS *OsFunc,
7654 +                 int OsFuncSize,
7655 +                 int *HalFuncSize,
7656 +                 int Inst);
7657 +#endif
7658 +
7659 +#ifdef _CPHAL_VDMAVT
7660 +/**
7661 + *  @ingroup shared_data
7662 + *  The VDMA_FUNCTIONS struct defines the HAL function pointers used by upper layer
7663 + *  software.  The upper layer software receives these pointers through the
7664 + *  call to InitModule().
7665 + *
7666 + *  Note that this list is still under definition.
7667 + */
7668 +typedef struct
7669 +  {
7670 +  bit32  (*Init)( HAL_DEVICE *VdmaVtDev);
7671 +    /*  bit32  (*SetupTxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
7672 +                  bit32u Addr, bit32u Size, bit32u PollInt);
7673 +    bit32  (*SetupRxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
7674 +                  bit32u Addr, bit32u Size, bit32u PollInt); */
7675 +  bit32  (*Tx)(HAL_DEVICE *VdmaVtDev);
7676 +  bit32  (*Rx)(HAL_DEVICE *VdmaVtDev);
7677 +  bit32  (*SetRemoteChannel)(HAL_DEVICE *VdmaVtDev, bit32u RemAddr,
7678 +                         bit32u RemDevID);
7679 +  bit32  (*ClearRxInt)(HAL_DEVICE *VdmaVtDev);
7680 +  bit32  (*ClearTxInt)(HAL_DEVICE *VdmaVtDev);
7681 +  bit32  (*Open)(HAL_DEVICE *VdmaVtDev);
7682 +  bit32  (*Close)(HAL_DEVICE *VdmaVtDev);
7683 +  int    (*Control)         (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
7684 +  int    (*ChannelSetup)(HAL_DEVICE *VdmaVtDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7685 +  int    (*ChannelTeardown)(HAL_DEVICE *VdmaVtDev, int Ch, int Mode);
7686 +  int    (*Send)(HAL_DEVICE *VdmaVtDev,FRAGLIST *FragList,int FragCount,
7687 +                 int PacketSize,OS_SENDINFO *OsSendInfo,bit32u Mode);
7688 +  } VDMA_FUNCTIONS;
7689 +
7690 +int VdmaInitModule(HAL_DEVICE **VdmaVt,
7691 +                 OS_DEVICE *OsDev,
7692 +                 VDMA_FUNCTIONS **VdmaVtFunc,
7693 +                 OS_FUNCTIONS *OsFunc,
7694 +                 int OsFuncSize,
7695 +                 int *HalFuncSize,
7696 +                 int Inst);
7697 +#endif
7698 +
7699 +/*
7700 +extern int cphalInitModule(MODULE_TYPE ModuleType, HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc,
7701 +                      int (*osInitModule)(OS_FUNCTIONS *), void* (*osMallocDev)(bit32u),
7702 +                      int *Size, int Inst);
7703 +*/
7704 +
7705 +
7706 +#ifdef _CPHAL_AAL5
7707 +extern const char hcSarFrequency[];
7708 +#endif
7709 +
7710 +#ifdef _CPHAL_CPMAC
7711 +/* following will be common, once 'utl' added */
7712 +extern const char hcClear[];
7713 +extern const char hcGet[];
7714 +extern const char hcSet[];
7715 +extern const char hcTick[];
7716 +
7717 +extern const char hcCpuFrequency[];
7718 +extern const char hcCpmacFrequency[];
7719 +extern const char hcMdioBusFrequency[];
7720 +extern const char hcMdioClockFrequency[];
7721 +extern const char hcCpmacBase[];
7722 +extern const char hcPhyNum[];
7723 +extern const char hcSize[];
7724 +extern const char hcCpmacSize[];
7725 +extern const char hcPhyAccess[];
7726 +extern const char hcMdixMask[];
7727 +extern const char hcMdioMdixSwitch[];
7728 +#endif
7729 +
7730 +#endif  /*  end of _INC_    */
7731 diff -urN linux.old/drivers/net/avalanche_cpmac/dox_cpmac.h linux.dev/drivers/net/avalanche_cpmac/dox_cpmac.h
7732 --- linux.old/drivers/net/avalanche_cpmac/dox_cpmac.h   1970-01-01 01:00:00.000000000 +0100
7733 +++ linux.dev/drivers/net/avalanche_cpmac/dox_cpmac.h   2005-07-12 02:48:42.050593000 +0200
7734 @@ -0,0 +1,842 @@
7735 +/*****************************************************************************
7736 + *  TNETDxxxx Software Support
7737 + *  Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
7738 + *
7739 + *  FILE:
7740 + *
7741 + *  DESCRIPTION:
7742 + *      This file contains documentation for the CPMAC
7743 + *
7744 + *  HISTORY:
7745 + *  @author Michael Hanrahan/Greg Guyotte
7746 + *  @version 1.00
7747 + *  @date    03-Dec-2002
7748 + *****************************************************************************/
7749 +#ifndef _DOX_CPMAC_H
7750 +#define _DOX_CPMAC_H
7751 +/**
7752 +@page CPMAC_Implementation_Details Version
7753 +
7754 +@copydoc CPMAC_Version
7755 +*/
7756 +
7757 +/**
7758 +@page cpmac_intro Introduction
7759 +
7760 +The CPMAC implementation will support 8 channels for transmit and 8 channel for
7761 +receive.  Each of the 8 transmit channels has 1 queue associated with it.  It is
7762 +recommended that only 1 channel is used for @c Receive() per processor.
7763 +*/
7764 +
7765 +/**
7766 +@page cpmac_details API Implementation Details
7767 +@par osReceive
7768 +@p Mode parameter
7769 +- The Upper 16 bits of Mode match Word 3 of the Rx Buffer Descriptor
7770 +
7771 +@par halSend
7772 +@p Mode parameter
7773 +-  Bits 0-7 contain the Channel Number
7774 +-  Bits 8-25 are reserved
7775 +-  Bit  26 - if 0, the CRC will be calculated, if 1 the CRC will be Passed
7776 +-  Bits 27-31 : reserved
7777 +@section cpmac_keys Control Keys
7778 +
7779 +@par StateChange
7780 +CPHAL calls the OS when a state change is detected.
7781 +OS should check the CPMAC Status. See the Control Key 'Status' for more details.
7782 +
7783 +@par Status
7784 +OS calls the CPHAL to obtain Status information. The Returned status is as follows
7785 +
7786 +@par MaxFrags
7787 +The OS may "Set" or "Get" this value.  This defines the maximum
7788 +number of fragments that can be received by the CPMAC Rx port.  The default
7789 +value for CPMAC is 2.  This provides enough space to receive a maximum
7790 +length packet (1,518 bytes) with the default buffer size of 1518 and any
7791 +amount of RxBufferOffset.  If the buffer size is configured to be smaller,
7792 +the OS *MUST* modify this parameter according to the following formula:
7793 +((System Max packet length)/(RxBufSize)) + 1.  (The extra 1 fragment is to
7794 +allow for RxBufferOffset)
7795 +
7796 +@code
7797 +// Following defined in "cpswhal_cpmac.h"
7798 +// CPMAC CPHAL STATUS
7799 +#define CPMAC_STATUS_LINK               (1 << 0)
7800 +#define CPMAC_STATUS_LINK_DUPLEX        (1 << 1)  // 0 - HD, 1 - FD
7801 +#define CPMAC_STATUS_LINK_SPEED         (1 << 2)  // 0 - 10, 1 - 100
7802 +
7803 +// ADAPTER CHECK Codes
7804 +#define CPMAC_STATUS_ADAPTER_CHECK             (1 << 7)
7805 +#define CPMAC_STATUS_HOST_ERR_DIRECTION        (1 << 8)    // 0 - Tx, 1 - Rx
7806 +#define CPMAC_STATUS_HOST_ERR_CODE             (0xF << 9)  See CPMAC Guide
7807 +#define CPMAC_STATUS_HOST_ERR_CH               (0x7 << 13) See CPMAC Guide
7808 +@endcode
7809 +
7810 +@code
7811 +void osStateChange(OS_DEVICE *OsDev)
7812 +  {
7813 +  int status;
7814 +  OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
7815 +  if(status & CPMAC_STATUS_ADAPTER_CHECK)
7816 +    {
7817 +    printf("[osStateChange[%d]]  HAL notified OS of AdapterCheck (Link Status 0x%08X)\n", OsDev->port, status);
7818 +    adaptercheck(OsDev->port);
7819 +    }
7820 +  else
7821 +    {
7822 +    printf("[osStateChange[%d]]  HAL notified OS of State Change (Link Status %s)\n", OsDev->port, (status & CPMAC_STATUS_LINK) ? "Up" : "Down");
7823 +    if(status & CPMAC_STATUS_LINK)
7824 +      {
7825 +      printf("Speed %s, Duplex %s\n",
7826 +      status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
7827 +      status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
7828 +      }
7829 +    }
7830 +@endcode
7831 +
7832 +@par Tick
7833 +     The CPHAL calls the OS to set the interval for calling halTick()<BR>
7834 +     Note: Predefined value hcTick now recommended for use.
7835 +@code
7836 +***  Example Code ***
7837 +
7838 +*** CPHAL code ***
7839 +int Ticks;
7840 +HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcSet, &Ticks);
7841 +
7842 +*** OS code ***
7843 +  ..
7844 +  if(osStrcmpi(pszKey, hcTick) == 0)
7845 +  {
7846 +    if(osStrcmpi(pszAction, hcSet) == 0)
7847 +    {
7848 +      // Enable the Tick Interval
7849 +      if(*(unsigned int *) ParmValue)
7850 +        printf("osTickSet: Interval = %d ticks\n", Interval);
7851 +    }
7852 +    else
7853 +    if(osStrcmpi(pszAction, hcClear) == 0)
7854 +    {
7855 +        // Request disabling of the Tick Timer, ParmValue is ignored
7856 +    }
7857 +  }
7858 +@endcode
7859 +
7860 +@par The following information can be obtained by the OS via 'Get'
7861 +
7862 +- StatsDump : OS supplies pointer to an 36 element unsigned int array
7863 +CPHAL will populate the array with the current Statistics values.<BR>
7864 +Note: all hcXXXX values are predefined and should be used by the OS.
7865 +
7866 +- hcPhyNum : Returns the PHY number.
7867 +- hcCpmacBase : Returns the base-address of the CPMAC device
7868 +- hcCpmacSize : Returns size of the CPMAC memory map
7869 +
7870 +
7871 +@par Phy Register Communication
7872 +
7873 +halControl() is used to read and write the Phy Registers via the key hcPhyAccess
7874 +
7875 +Both reading and writing the Phy registers involve setting the Value parameter of halControl()
7876 +<BR>
7877 +Value is a 32-bit value with bits partioned as follows
7878 +<BR>
7879 +
7880 +   0 -  4  Phy Number   <BR>
7881 +   5 -  9  Phy Register <BR>
7882 +  10 - 15  reserved     <BR>
7883 +  16 - 31  Data  (write only)
7884 +<BR>
7885 +
7886 +
7887 +<B>Reading the Phy register</B>
7888 +
7889 +@code
7890 +    bit32u Value;
7891 +    bit32u RegAddr;
7892 +    bit32u PhyNum;
7893 +    bit32u PhyRegisterData;
7894 +
7895 +    //  Read Phy 31, register 20
7896 +
7897 +    PhyNum  = 31;
7898 +    RegAddr = 20;
7899 +
7900 +    Value = (RegAddr << 5);
7901 +    Value |= (PhyNum & 0x1F);
7902 +
7903 +    rc  = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
7904 +    If(rc == 0)
7905 +    {
7906 +        // Value is overwriten with the value in Register 20 of Phy number 31.
7907 +        PhyRegisterData = Value;
7908 +    }
7909 +@endcode
7910 +
7911 +<B>Writing the Phy register</B>
7912 +@code
7913 +    bit32u Value;
7914 +    bit32u RegAddr;
7915 +    bit32u PhyNum;
7916 +    bit32u PhyRegisterData;
7917 +
7918 +    //  Reset Phy 23
7919 +
7920 +    PhyNum  = 23;
7921 +    RegAddr = 0;
7922 +    PhyRegisterData = 0x8000;  // Reset bit set
7923 +
7924 +    Value = (RegAddr << 5);
7925 +    Value |= (PhyNum & 0x1F);
7926 +    Value |= (PhyRegisterData << 16);
7927 +
7928 +    rc  = HalFunc->Control(HalDev, hcPhyAccess, hcSet, (bit32u *) &Value)
7929 +
7930 +    // Check is reset if done
7931 +
7932 +    PhyNum  = 23;
7933 +    RegAddr = 0;
7934 +
7935 +    Value = (RegAddr << 5);
7936 +    Value |= (PhyNum & 0x1F);
7937 +
7938 +    rc  = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
7939 +
7940 +    If(rc == 0)
7941 +    {
7942 +        // Value is overwriten with the value in Register 0 of Phy number 23.
7943 +        PhyRegisterData = Value;
7944 +        if((PhyRegisterData & 0x8000) == 0)
7945 +           ResetIsComplete;
7946 +    }
7947 +
7948 +@endcode
7949 +<B>
7950 +*** Example Showing turning values off/on ***
7951 +<BR>
7952 +</B>
7953 +
7954 +@code
7955 +
7956 +int On=1;
7957 +int Off=0;
7958 +   # Turn On loopback
7959 +   OsDev->HalFunc->Control(OsDev->HalDev, "CTRL_LOOPBACK", hcSet, (int*) &On);
7960 +
7961 +   #  Turn off RX Flow
7962 +   OsDev->HalFunc->Control(OsDev->HalDev, "RX_FLOW_EN", hcSet, (int*) &Off);
7963 +@endcode
7964 +
7965 +@par CPMAC Configurable Parameters
7966 +
7967 +- RX_PASS_CRC        : See MBP_Enable description
7968 +- RX_QOS_EN          : See MBP_Enable description
7969 +- RX_NO_CHAIN        : See MBP_Enable description
7970 +- RX_CMF_EN          : See MBP_Enable description
7971 +- RX_CSF_EN          : See MBP_Enable description
7972 +- RX_CEF_EN          : See MBP_Enable description
7973 +- RX_CAF_EN          : See MBP_Enable description
7974 +- RX_PROM_CH         : See MBP_Enable description
7975 +- RX_BROAD_EN        : See MBP_Enable description
7976 +- RX_BROAD_CH        : See MBP_Enable description
7977 +- RX_MULT_EN         : See MBP_Enable description
7978 +- RX_MULT_CH         : See MBP_Enable description
7979 +
7980 +- TX_PTYPE           : See MacControl description
7981 +- TX_PACE            : See MacControl description
7982 +- TX_FLOW_EN         : See MacControl description
7983 +- RX_FLOW_EN         : See MacControl description
7984 +- CTRL_LOOPBACK      : See MacControl description
7985 +
7986 +- RX_MAXLEN          : See CPMAC Guide
7987 +- RX_FILTERLOWTHRESH : See CPMAC Guide
7988 +- RX0_FLOWTHRESH     : See CPMAC Guide
7989 +- RX_UNICAST_SET     : See CPMAC Guide
7990 +- RX_UNICAST_CLEAR   : See CPMAC Guide
7991 +
7992 +@par Multicast Support
7993 +- RX_MULTI_ALL       : When used with hcSet, sets all the Hash Bits. When used
7994 +with hcClear clears all the Hash Bits.
7995 +- RX_MULTI_SINGLE    : When used with hcSet, adds the Hashed Mac Address. When used
7996 +with hcClear deletes the Hashed Mac Address.
7997 +Note: Support will be added to keep track of Single additions and deletions.
7998 +
7999 +@code
8000 +*** Example Code ***
8001 +
8002 +*** OS code ***
8003 +  bit8u  MacAddress[6];
8004 +  MacAddress[0] = 0x80;
8005 +  MacAddress[1] = 0x12;
8006 +  MacAddress[2] = 0x34;
8007 +  MacAddress[3] = 0x56;
8008 +  MacAddress[4] = 0x78;
8009 +  MacAddress[5] = 0x78;
8010 +  OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcSet, (bit8u*) &MacAddress);
8011 +  OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcClear, (bit8u*) &MacAddress);
8012 +  OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcSet, NULL);
8013 +  OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcClear, NULL);
8014 +@endcode
8015 +@par MdioConnect Fields
8016 +<BR>
8017 +- "MdioConnect"     : The OS can set the Phy connection using this key. The default connection is Auto-Negotiation ON, All modes possible.
8018 +
8019 +
8020 +- _CPMDIO_HD       <----- Allow Half Duplex, default is 1 (On)
8021 +- _CPMDIO_FD       <----- Allow Full Duplex, default is 1 (On)
8022 +- _CPMDIO_10       <----- Allow 10  Mbs, default is 1 (On)
8023 +- _CPMDIO_100      <----- Allow 100 Mbs, default is 1 (On)
8024 +- _CPMDIO_NEG_OFF  <----- Turn off Auto Negotiation, default is 0 (Auto Neg is on)
8025 +- _CPMDIO_NOPHY    <----- Set for use with Marvel-type switch, default is 0 (Phy present)
8026 +- _CPMDIO_AUTOMDIX  <---- Enables Auto Mdix (in conjunction with MdixMask), default is 1 (On)
8027 +
8028 +Note: When _CPMDIO_NOPHY is set, CPMAC will report being linked at 100/FD. Reported PhyNum will be 0xFFFFFFFF
8029 +
8030 +@par Setting CPMAC for use with a Marvel-type Switch
8031 +@code
8032 +     bit32u MdioConnect;
8033 +
8034 +     MdioConnect = _CPMDIO_NOPHY;
8035 +     OsDev->HalFunc->Control(OsDev->HalDev, "MdioConnect", hcSet, (bit32u*) &MdioConnect);
8036 +@endcode
8037 +
8038 +@par OS Support for MDIO
8039 +@p The OS will need to supply the following values which the CPHAL will request via halControl()
8040 +<BR>
8041 +- MdioBusFrequency : The frequency of the BUS that MDIO is on (requested via hcMdioBusFrequency)
8042 +<BR>
8043 +- MdioClockFrequency : The desired Clock Frequency that MDIO qill operate at (requested via hcMdioClockFrequency)
8044 +*/
8045 +
8046 +/**
8047 +@page cpmac_conf DeviceFindxxx() Parameters
8048 +
8049 +These are some of the parameters that the CPMAC will request via the DeviceFindxxx() functions -
8050 +<BR>
8051 +- "Mlink"    : bit mask indicating what link status method Phy is using. Default is MDIO state machine (0x0)
8052 +- "PhyMask"  : bit mask indicating PhyNums used by this CPMAC (e.g 0x8000000, PhyNum is 31)
8053 +- "MdixMask" : bit mask indicating which Phys support AutoMdix. Default is 0x0 (None)
8054 +<BR>
8055 +@par Example cpmac definition from the options.conf for the Sangam VDB
8056 +<BR>
8057 +- cpmac( id=eth0, base=0xA8610000, size=0x800, reset_bit=17, int_line=19, PhyMask=0x80000000, MLink=0, MdixMask=0 )
8058 +*/
8059 +
8060 +/**
8061 +@page auto_mdix Auto Mdix Support
8062 +
8063 +Auto Mdix selection is controlled by two elements in the CPMAC. First the OS can turn Auto Midx On or Off by the use of the
8064 +MdioConnect field, _CPMDIO_AUTOMDIX. This is defaulted ON.  For actual Auto Mdix operation the Phy must also be Auto Mdix capable.
8065 +This is specified by the DeviceFindxxx() field, "MdixMask" (supplied as the variable hcMdixMask).
8066 +If both these fields are set then the CPMDIO state machine will be enabled for Auto Mdix checking.
8067 +If a switch to MDI or MDIX mode is needed, the CPMAC will signal this to the OS via Control() using
8068 +the hcMdioMdixSwitch key.
8069 +
8070 +@par OS example for responding to a Mdix Switch Request
8071 +<BR>
8072 +@code
8073 +if(osStrcmpi(pszKey, hcMdioMdixSwitch) == 0)  // See if key is Mdix Switch Request
8074 +  {
8075 +      if(osStrcmpi(pszAction, hcSet) == 0)   // Only respond to Set requests
8076 +      {
8077 +
8078 +          bit32u Mdix;
8079 +
8080 +          Mdix = *(bit32u *) ParmValue;     // Extract requested Mode
8081 +                                            // 0 : MDI
8082 +                                            // 1 : MDIX
8083 +          if(Mdix)
8084 +            osSetPhyIntoMdixMode();         // Device specific logic
8085 +          else
8086 +            osSetPhyIntoMdiMode();          // Device specific logic
8087 +          rc = 0;                           // Set return code as Successfull
8088 +      }
8089 +@endcode
8090 +*/
8091 +
8092 +/**
8093 +@page cpmac_stats CPMAC Specific Statistics
8094 +
8095 +Statistics level '0' contains all CPMAC specific statistics.
8096 +
8097 +
8098 +*/
8099 +
8100 +/**
8101 +@page Example_Driver_Code
8102 +
8103 +@section  example_intro Introduction
8104 +This section provides an in-depth code example for driver implementations.  The code
8105 +below illustrates the use of the CPMAC HAL, but is equally applicable to any CPHAL
8106 +implementation. Note: the CPHAl constants hcGet, hcSet etc., are currently available for use with teh CPMAC module.
8107 +Other modules should continue to use pszGET, etc. until these are made generally available.
8108 +
8109 +@par Pull Model Example
8110 +
8111 +@code
8112 +
8113 +#define _CPHAL_CPMAC
8114 +
8115 +typedef struct _os_device_s  OS_DEVICE;
8116 +typedef struct _os_receive_s OS_RECEIVEINFO;
8117 +typedef struct _os_send_s    OS_SENDINFO;
8118 +typedef struct _os_setup_s   OS_SETUP;
8119 +
8120 +#include "cpswhal_cpmac.h"
8121 +
8122 +#define dbgPrintf printf
8123 +
8124 +typedef struct  _os_device_s
8125 +{
8126 +   HAL_DEVICE    *HalDev;
8127 +   HAL_FUNCTIONS *HalFunc;
8128 +   OS_FUNCTIONS  *OsFunc;
8129 +   OS_SETUP      *OsSetup;
8130 +   bit32u        Interrupt;
8131 +   int           (*halIsr)(HAL_DEVICE  *HalDev, int*);
8132 +   int           ModulePort;
8133 +   int           Protocol;
8134 +   int           LinkStatus;  // 0-> down, otherwise up
8135 +}os_device_s;
8136 +
8137 +typedef struct  _os_receive_s
8138 +{
8139 +   HAL_RECEIVEINFO *HalReceiveInfo;
8140 +   char   *ReceiveBuffer;
8141 +   OS_DEVICE  *OsDev;
8142 +}os_receive_s;
8143 +
8144 +typedef struct  _os_send_s
8145 +{
8146 +   OS_DEVICE  *OsDev;
8147 +}os_send_s;
8148 +
8149 +typedef struct  _os_setup_s
8150 +{
8151 +   OS_DEVICE  *OsDev;
8152 +}os_setup_s;
8153 +
8154 +
8155 +
8156 +void FlowForCphal(OS_DEVICE *OsDev)
8157 +{
8158 +  CHANNEL_INFO ChannelInfo;
8159 +  int nChannels = 200;
8160 +  int halFuncSize;
8161 +  int rc;
8162 +
8163 +  //  Populate OsFunc structure
8164 +  rc =  osInitModule(OsDev);
8165 +
8166 +  if(rc)
8167 +  {
8168 +    sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
8169 +    errorout(bufTmp);
8170 +  }
8171 +
8172 +
8173 +  //  OS-Cphal handshake
8174 +  rc = halCpmacInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
8175 +                              sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
8176 +
8177 +  if(rc)
8178 +  {
8179 +    sprintf(bufTmp, "%s: return code from halCpmacInitModule:'0x%08X'", __FUNCTION__, rc);
8180 +    errorout(bufTmp);
8181 +  }
8182 +
8183 +  // See if hardware module exists
8184 +  rc = OsDev->HalFunc->Probe(OsDev->HalDev);
8185 +
8186 +  if(rc)
8187 +  {
8188 +    sprintf(bufTmp, "%s: return code from Probe:'0x%08X'", __FUNCTION__, rc);
8189 +    errorout(bufTmp);
8190 +  }
8191 +
8192 +  // Initialize hardware module
8193 +  rc = OsDev->HalFunc->Init(OsDev->HalDev);
8194 +
8195 +  if(rc)
8196 +  {
8197 +    sprintf(bufTmp, "%s: return code from Init:'0x%08X'", __FUNCTION__, rc);
8198 +    errorout(bufTmp);
8199 +  }
8200 +
8201 +  // Setup Channel Information (Tranmsit, channel 0)
8202 +  ChannelInfo.Channel      = 0;
8203 +  ChannelInfo.Direction    = DIRECTION_TX;
8204 +  ChannelInfo.TxNumBuffers = nChannels;
8205 +  ChannelInfo.TxNumQueues  = 1;
8206 +  ChannelInfo.TxServiceMax = nChannels/3;
8207 +
8208 +  rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8209 +
8210 +  // Setup Channel Information (Receive, channel 0)
8211 +  ChannelInfo.Channel        = 0;
8212 +  ChannelInfo.Direction      = DIRECTION_RX;
8213 +  ChannelInfo.RxBufSize      = 1518;
8214 +  ChannelInfo.RxBufferOffset = 0;
8215 +  ChannelInfo.RxNumBuffers   = 2*nChannels;
8216 +  ChannelInfo.RxServiceMax   = nChannels/3;
8217 +
8218 +  rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8219 +
8220 +  // Open the hardware module
8221 +  rc = OsDev->HalFunc->Open(OsDev->HalDev);
8222 +
8223 +  // Module now ready to Send/Receive data
8224 +}
8225 +
8226 +
8227 +int osInitModule(OS_FUNCTIONS **pOsFunc)
8228 +  {
8229 +   OS_FUNCTIONS *OsFunc;
8230 +
8231 +   OsFunc = (OS_FUNCTIONS *) malloc(sizeof(OS_FUNCTIONS));
8232 +   if (!OsFunc)
8233 +     return (-1);
8234 +
8235 +   *pOsFunc = OsFunc;
8236 +
8237 +   OsFunc->CriticalOff               = osCriticalOff;
8238 +   OsFunc->CriticalOn                = osCriticalOn;
8239 +   OsFunc->DataCacheHitInvalidate    = osDataCacheHitInvalidate;
8240 +   OsFunc->DataCacheHitWriteback     = osDataCacheHitWriteback;
8241 +   OsFunc->DeviceFindInfo            = osDeviceFindInfo;
8242 +   OsFunc->DeviceFindParmUint        = osDeviceFindParmUint;
8243 +   OsFunc->DeviceFindParmValue       = osDeviceFindParmValue;
8244 +   OsFunc->Free                      = osFree;
8245 +   OsFunc->FreeDev                   = osFreeDev;
8246 +   OsFunc->FreeDmaXfer               = osFreeDmaXfer;
8247 +   OsFunc->FreeRxBuffer              = osFreeRxBuffer;
8248 +   OsFunc->IsrRegister               = osIsrRegister;
8249 +   OsFunc->IsrUnRegister             = osIsrUnRegister;
8250 +   OsFunc->Malloc                    = osMalloc;
8251 +   OsFunc->MallocDev                 = osMallocDev;
8252 +   OsFunc->MallocDmaXfer             = osMallocDmaXfer;
8253 +   OsFunc->MallocRxBuffer            = osMallocRxBuffer;
8254 +
8255 +
8256 +   OsFunc->Memset                    = memset;
8257 +   OsFunc->Printf                    = printf;
8258 +   OsFunc->Sprintf                   = sprintf;
8259 +   OsFunc->Strcmpi                   = osStrcmpi;
8260 +   OsFunc->Strlen                    = strlen;
8261 +   OsFunc->Strstr                    = strstr;
8262 +   OsFunc->Strtoul                   = strtoul;
8263 +
8264 +   OsFunc->Control                   = osControl;
8265 +   OsFunc->Receive                   = osReceive;
8266 +   OsFunc->SendComplete              = osSendComplete;
8267 +   OsFunc->TeardownComplete          = osTearDownComplete;
8268 +
8269 +   return(0);
8270 +  }
8271 +
8272 +
8273 +int osReceive(OS_DEVICE *OsDev,FRAGLIST *Fraglist,bit32u FragCount,bit32u PacketSize,HAL_RECEIVEINFO *halInfo, bit32u mode)
8274 +  {
8275 +  OS_RECEIVEINFO *skb = (OS_RECEIVEINFO *)Fraglist[0].OsInfo;
8276 +  dcache_i((char *)Fraglist->data, Fraglist->len);
8277 +  OsDev->HalFunc->RxReturn(halInfo,0);
8278 +  return(0);
8279 +  }
8280 +
8281 +int osSendComplete(OS_SENDINFO *skb)
8282 +  {
8283 +  return(0);
8284 +  }
8285 +
8286 +
8287 +static void *osMallocRxBuffer(bit32u Size,void *MemBase, bit32u MemRange,
8288 +                              OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
8289 +                              OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev )
8290 +  {
8291 +   void *HalBuffer;
8292 +   OS_RECEIVEINFO *OsPriv;
8293 +
8294 +   HalBuffer=malloc(Size);
8295 +   if (!HalBuffer)
8296 +     {
8297 +      return(0);
8298 +     }
8299 +
8300 +   // Malloc the OS block
8301 +   *OsReceiveInfo = malloc(sizeof(OS_RECEIVEINFO));
8302 +   if (!*OsReceiveInfo)
8303 +     {
8304 +      free(HalBuffer);
8305 +      return(0);
8306 +     }
8307 +
8308 +   // Initialize the new buffer descriptor
8309 +   OsPriv                 = *OsReceiveInfo;
8310 +   OsPriv->OsDev          =  OsDev;
8311 +   OsPriv->ReceiveBuffer  =  HalBuffer;
8312 +   OsPriv->HalReceiveInfo =  HalReceiveInfo;
8313 +
8314 +   return(HalBuffer);
8315 +  }
8316 +
8317 +
8318 +void SendBuffer(OS_DEVICE *OsDev, char *Buffer, int Size)
8319 +{
8320 +  FRAGLIST Fraglist;
8321 +  bit32u FragCount;
8322 +
8323 +  tcb_pending++;
8324 +  Fraglist.len  = Size;
8325 +  Fraglist.data = (unsigned *) Buffer;
8326 +  FragCount     = 1;
8327 +  mode          = 0;   //  Channel 0
8328 +
8329 +  dcache_wb(Fraglist.data, Fraglist.len);
8330 +  OsDev->HalFunc->Send(OsDev->HalDev, &Fraglist, FragCount, Size, (OS_SENDINFO *) Buffer, mode);
8331 +}
8332 +
8333 +
8334 +void osStateChange(OS_DEVICE *OsDev)
8335 +  {
8336 +  int status;
8337 +  int LinkStatus;
8338 +  OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
8339 +  if(status & CPMAC_STATUS_ADAPTER_CHECK)
8340 +    {
8341 +    //  Adapter Check, take appropiate action
8342 +    }
8343 +  else
8344 +    {
8345 +    LinkStatus = status & CPMAC_STATUS_LINK;
8346 +    if(LinkStatus != OsDev->LinkStatus)
8347 +      {
8348 +      dbgPrintf("\n%s:Link %s for inst %d Speed %s, Duplex %s\n",
8349 +                 __FUNCTION__,
8350 +                 LinkStatus ? "up" : "down",
8351 +                 OsDev->ModulePort,
8352 +                 status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
8353 +                 status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
8354 +      OsDev->LinkStatus = LinkStatus;
8355 +      }
8356 +    }
8357 +  }
8358 +
8359 +
8360 +int osControl(OS_DEVICE *OsDev, const char *pszKey, const char* pszAction, void *ParmValue)
8361 +  {
8362 +  int rc=-1;
8363 +
8364 +  if (osStrcmpi(pszKey, hcCpuFrequency) == 0)
8365 +   {
8366 +   if(osStrcmpi(pszAction, hcGet) == 0)
8367 +     {
8368 +     *(bit32u*) ParmValue = cpufreq;
8369 +     rc = 0;
8370 +     }
8371 +   }
8372 +  if (osStrcmpi(pszKey, hcMdioBusFrequency) == 0)
8373 +   {
8374 +   if(osStrcmpi(pszAction, hcGet) == 0)
8375 +     {
8376 +     *(bit32u *)ParmValue = MdioBusFrequency;
8377 +     rc = 0;
8378 +     }
8379 +   }
8380 +if (osStrcmpi(pszKey, hcMdioClockFrequency) == 0)
8381 +   {
8382 +   if(osStrcmpi(pszAction, hcGet) == 0)
8383 +     {
8384 +     *(bit32u *)ParmValue = MdioClockFrequency;
8385 +     rc = 0;
8386 +     }
8387 +   }
8388 +
8389 +  if (osStrcmpi(pszKey, hcTick) == 0)
8390 +   {
8391 +   if(osStrcmpi(pszAction, hcSet) == 0)
8392 +     {
8393 +       osTickSetInterval(OsDev, *(unsigned int *) ParmValue);
8394 +       rc = 0;
8395 +     }
8396 +   else
8397 +   if(osStrcmpi(pszAction, hcClear) == 0)
8398 +     {
8399 +       osTickDisable(OsDev);
8400 +       rc = 0;
8401 +     }
8402 +   }
8403 +
8404 +  if (osStrcmpi(pszKey, "SioFlush") == 0)
8405 +    {
8406 +       MySioFlush();
8407 +       rc = 0;
8408 +    }
8409 +
8410 +  if (osStrcmpi(pszKey, "StateChange") == 0)
8411 +    {
8412 +       osStateChange(OsDev);
8413 +       rc = 0;
8414 +    }
8415 +
8416 +  if (osStrcmpi(pszKey, "Sleep") == 0)
8417 +    {
8418 +       osSleep(*(int *)ParmValue);
8419 +       rc = 0;
8420 +    }
8421 +  return(rc);
8422 +  }
8423 +
8424 +@endcode
8425 +
8426 +
8427 +@par Push Model Example (Currently Eswitch ONLY)
8428 +
8429 +@code
8430 +
8431 +typedef struct _os_device_s  OS_DEVICE;
8432 +typedef struct _os_receive_s OS_RECEIVEINFO;
8433 +typedef struct _os_send_s    OS_SENDINFO;
8434 +typedef struct _os_setup_s   OS_SETUP;
8435 +
8436 +#include "cpswhal.h"          //Get glogal HAL stuff
8437 +#include "cpswhaleswitch.h"   //Get device specific hal stuff
8438 +
8439 +
8440 +typedef struct  _os_device_s
8441 +{
8442 +   HAL_DEVICE    *HalDev;
8443 +   HAL_FUNCTIONS *HalFunc;
8444 +   OS_FUNCTIONS  *OsFunc;
8445 +   OS_SETUP      *OsSetup;
8446 +   bit32u        Interrupt;
8447 +   int           (*halIsr)(HAL_DEVICE  *HalDev, int*);
8448 +   int           ModulePort;
8449 +   int           Protocol;
8450 +   int           LinkStatus;  // 0-> down, otherwise up
8451 +}os_device_s;
8452 +
8453 +typedef struct  _os_receive_s
8454 +{
8455 +   HAL_RECEIVEINFO *HalReceiveInfo;
8456 +   char   *ReceiveBuffer;
8457 +   OS_DEVICE  *OsDev;
8458 +}os_receive_s;
8459 +
8460 +typedef struct  _os_send_s
8461 +{
8462 +   OS_DEVICE  *OsDev;
8463 +}os_send_s;
8464 +
8465 +typedef struct  _os_setup_s
8466 +{
8467 +   OS_DEVICE  *OsDev;
8468 +}os_setup_s;
8469 +
8470 +
8471 +
8472 +void FlowForCphal(OS_DEVICE *OsDev)
8473 +{
8474 +CHANNEL_INFO ChannelInfo;
8475 +  int nChannels = 200;
8476 +  int halFuncSize;
8477 +  int rc;
8478 +
8479 +  //  Populate OsFunc structure
8480 +  rc =  osInitModule(OsDev);
8481 +
8482 +  if(rc)
8483 +  {
8484 +    sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
8485 +    errorout(bufTmp);
8486 +  }
8487 +
8488 +
8489 +  //  OS-Cphal handshake
8490 +  rc = cpswHalEswitchInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
8491 +                              sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
8492 +
8493 +  if(rc)
8494 +  {
8495 +    sprintf(bufTmp, "%s: return code from cpswHalEswitchInitModule:'0x%08X'", __FUNCTION__, rc);
8496 +    errorout(bufTmp);
8497 +  }
8498 +
8499 +
8500 +  ChannelInfo.Channel      = 7;
8501 +  ChannelInfo.Direction    = DIRECTION_RX;
8502 +  ChanInfo.Receive = osReceiveSS;         //  Specify function to receive data for this channel
8503 +
8504 +  rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8505 +
8506 +  MyConfig.debug=0;
8507 +  MyConfig.CpuFrequency = CpuFreq;
8508 +  MyConfig.EswitchFrequency = EswitchFreq;
8509 +  MyConfig.ResetBase  = 0xa8611600;
8510 +  MyConfig.MacAddress = MacAddr;
8511 +
8512 +  MyConfig.EswitchResetBit= 27;
8513 +  MyConfig.Cpmac0ResetBit = 17;
8514 +  MyConfig.Cpmac1ResetBit = 21;
8515 +  MyConfig.MdioResetBit   = 22;
8516 +  MyConfig.Phy0ResetBit   = 26;
8517 +  MyConfig.Phy1ResetBit   = 28;
8518 +  MyConfig.HdmaResetBit   = 13;
8519 +  MyConfig.Cpmac0IntBit   = 19;
8520 +  MyConfig.Cpmac1IntBit   = 33;
8521 +  MyConfig.EswitchIntBit  = 27;
8522 +  MyConfig.EswitchBase    = 0xa8640000;
8523 +  MyConfig.EswitchBufferSize     = 64;
8524 +  MyConfig.EswitchHostBufCount   = 0;
8525 +  MyConfig.EswitchDefaultCamSize = 64;
8526 +  MyConfig.EswitchOverFlowCount  = 200;
8527 +  MyConfig.EswitchOverFlowSize   = 256;
8528 +
8529 +
8530 +
8531 +
8532 +  rc=EswitchConfig(HalDev,HalFunc,&MyConfig);
8533 +
8534 +
8535 +  // Open the hardware module
8536 +  rc = OsDev->HalFunc->Open(OsDev->HalDev);
8537 +
8538 +  // Module now ready to Send/Receive data
8539 +}
8540 +
8541 +
8542 +int EswitchConfig(HAL_DEVICE *HalDev, HAL_FUNCTIONS *HalFunc, ESWITCH_CONFIG *Config)
8543 +{
8544 +  bit32u sts;
8545 +  sts = 0;
8546 +
8547 +  sts |= cpswhalPushBin(hcdebug, Config->debug);
8548 +  sts |= cpswhalPushBin(hcCpuFrequency     , Config->CpuFrequency );
8549 +  sts |= cpswhalPushBin(hcEswitchFrequency , Config->EswitchFrequency );
8550 +  sts |= cpswhalPushBin(hcResetBase        , Config->ResetBase  );
8551 +  sts |= cpswhalPushBin(hcMacAddress       , Config->MacAddress );
8552 +  sts |= cpswhalPushBin(hcEswitchResetBit, Config->EswitchResetBit);
8553 +  sts |= cpswhalPushBin(hcCpmac0ResetBit , Config->Cpmac0ResetBit );
8554 +  sts |= cpswhalPushBin(hcCpmac1ResetBit , Config->Cpmac1ResetBit );
8555 +  sts |= cpswhalPushBin(hcMdioResetBit   , Config->MdioResetBit   );
8556 +  sts |= cpswhalPushBin(hcPhy0ResetBit   , Config->Phy0ResetBit   );
8557 +  sts |= cpswhalPushBin(hcPhy1ResetBit   , Config->Phy1ResetBit   );
8558 +  sts |= cpswhalPushBin(hcHdmaResetBit   , Config->HdmaResetBit   );
8559 +  sts |= cpswhalPushBin(hcCpmac0IntBit   , Config->Cpmac0IntBit   );
8560 +  sts |= cpswhalPushBin(hcCpmac1IntBit   , Config->Cpmac1IntBit   );
8561 +  sts |= cpswhalPushBin(hcEswitchIntBit  , Config->EswitchIntBit  );
8562 +  sts |= cpswhalPushBin(hcEswitchBase           , Config->EswitchBase    );
8563 +  sts |= cpswhalPushBin(hcEswitchBufferSize     , Config->EswitchBufferSize     );
8564 +  sts |= cpswhalPushBin(hcEswitchHostBufCount   , Config->EswitchHostBufCount   );
8565 +  sts |= cpswhalPushBin(hcEswitchDefaultCamSize , Config->EswitchDefaultCamSize );
8566 +  sts |= cpswhalPushBin(hcEswitchOverFlowCount  , Config->EswitchOverFlowCount  );
8567 +  sts |= cpswhalPushBin(hcEswitchOverFlowSize   , Config->EswitchOverFlowSize   );
8568 +  return(sts);
8569 +}
8570 +
8571 +
8572 +
8573 +@endcode
8574 +*/
8575 +
8576 +#endif
8577 diff -urN linux.old/drivers/net/avalanche_cpmac/ec_errors_cpmac.h linux.dev/drivers/net/avalanche_cpmac/ec_errors_cpmac.h
8578 --- linux.old/drivers/net/avalanche_cpmac/ec_errors_cpmac.h     1970-01-01 01:00:00.000000000 +0100
8579 +++ linux.dev/drivers/net/avalanche_cpmac/ec_errors_cpmac.h     2005-07-12 02:48:42.051592000 +0200
8580 @@ -0,0 +1,118 @@
8581 +/***************************************************************************
8582 + Copyright(c) 2001, Texas Instruments Incorporated. All Rights Reserved.
8583 +
8584 + FILE:  ec_errors.h
8585 +
8586 + DESCRIPTION:
8587 +   This file contains definitions and function declarations for
8588 +   error code support.
8589 +
8590 + HISTORY:
8591 +   14Dec00 MJH             Added masking to EC_CLASS etc macros
8592 +   17Sep02 GSG             Added HAL support (new class&devices)
8593 +   03Oct02 GSG             Removed C++ style comments
8594 +***************************************************************************/
8595 +#ifndef _INC_EC_ERRORS
8596 +#define _INC_EC_ERRORS
8597 +
8598 +/*
8599 +  31    - CRITICAL
8600 +  30-28 - CLASS         (ie. DIAG, KERNEL, FLASH, etc)
8601 +  27-24 - INSTANCE      (ie. 1, 2, 3, etc )
8602 +  23-16 - DEVICE        (ie. EMAC, IIC, etc)
8603 +  15-08 - FUNCTION      (ie. RX, TX, INIT, etc)
8604 +  07-00 - ERROR CODE    (ie. NO_BASE, FILE_NOT_FOUND, etc )
8605 +*/
8606 +
8607 +/*---------------------------------------------------------------------------
8608 +  Useful defines for accessing fields within error code
8609 +---------------------------------------------------------------------------*/
8610 +#define CRITICAL_SHIFT    31
8611 +#define CLASS_SHIFT       28
8612 +#define INST_SHIFT        24
8613 +#define DEVICE_SHIFT      16
8614 +#define FUNCTION_SHIFT     8
8615 +#define ERROR_CODE_SHIFT   0
8616 +
8617 +#define CRITICAL_MASK     1
8618 +#define CLASS_MASK        0x07
8619 +#define DEVICE_MASK       0xFF
8620 +#define INST_MASK         0x0F
8621 +#define FUNCTION_MASK     0xFF
8622 +#define ERROR_CODE_MASK   0xFF
8623 +
8624 +#define EC_CLASS(val)     ((val&CLASS_MASK)      << CLASS_SHIFT)
8625 +#define EC_DEVICE(val)    ((val&DEVICE_MASK)     << DEVICE_SHIFT)
8626 +#define EC_INST(val)      ((val&INST_MASK)       << INST_SHIFT)
8627 +#define EC_FUNC(val)      ((val&FUNCTION_MASK)   << FUNCTION_SHIFT)
8628 +#define EC_ERR(val)       ((val&ERROR_CODE_MASK) << ERROR_CODE_SHIFT)
8629 +
8630 +/*---------------------------------------------------------------------------
8631 +   Operation classes
8632 +---------------------------------------------------------------------------*/
8633 +#define EC_HAL              EC_CLASS(0)
8634 +#define EC_DIAG             EC_CLASS(8)
8635 +
8636 +/*---------------------------------------------------------------------------
8637 +   Device types
8638 +---------------------------------------------------------------------------*/
8639 +#define EC_DEV_EMAC         EC_DEVICE(1)
8640 +#define EC_DEV_IIC          EC_DEVICE(2)
8641 +#define EC_DEV_RESET        EC_DEVICE(3)
8642 +#define EC_DEV_ATMSAR       EC_DEVICE(4)
8643 +#define EC_DEV_MEM          EC_DEVICE(5)
8644 +#define EC_DEV_DES          EC_DEVICE(6)
8645 +#define EC_DEV_DMA          EC_DEVICE(7)
8646 +#define EC_DEV_DSP          EC_DEVICE(8)
8647 +#define EC_DEV_TMR          EC_DEVICE(9)
8648 +#define EC_DEV_WDT          EC_DEVICE(10)
8649 +#define EC_DEV_DCL          EC_DEVICE(11)
8650 +#define EC_DEV_BBIF         EC_DEVICE(12)
8651 +#define EC_DEV_PCI              EC_DEVICE(13)
8652 +#define EC_DEV_XBUS         EC_DEVICE(14)
8653 +#define EC_DEV_DSLIF            EC_DEVICE(15)
8654 +#define EC_DEV_USB                      EC_DEVICE(16)
8655 +#define EC_DEV_CLKC                     EC_DEVICE(17)
8656 +#define EC_DEV_RAPTOR       EC_DEVICE(18)
8657 +#define EC_DEV_DSPC                     EC_DEVICE(19)
8658 +#define EC_DEV_INTC                     EC_DEVICE(20)
8659 +#define EC_DEV_GPIO                     EC_DEVICE(21)
8660 +#define EC_DEV_BIST                     EC_DEVICE(22)
8661 +#define EC_DEV_HDLC                     EC_DEVICE(23)
8662 +#define EC_DEV_UART                     EC_DEVICE(24)
8663 +#define EC_DEV_VOIC                     EC_DEVICE(25)
8664 +/* 9.17.02 (new HAL modules) */
8665 +#define EC_DEV_CPSAR        EC_DEVICE(0x1A)
8666 +#define EC_DEV_AAL5         EC_DEVICE(0x1B)
8667 +#define EC_DEV_AAL2         EC_DEVICE(0x1C)
8668 +#define EC_DEV_CPMAC        EC_DEVICE(0x1D)
8669 +#define EC_DEV_VDMA         EC_DEVICE(0x1E)
8670 +#define EC_DEV_VLYNQ        EC_DEVICE(0x1F)
8671 +#define EC_DEV_CPPI         EC_DEVICE(0x20)
8672 +#define EC_DEV_CPMDIO       EC_DEVICE(0x21)
8673 +
8674 +/*---------------------------------------------------------------------------
8675 +   Function types
8676 +---------------------------------------------------------------------------*/
8677 +#define EC_FUNC_READ_CONF   EC_FUNC(1)
8678 +#define EC_FUNC_INIT        EC_FUNC(2)
8679 +
8680 +/*---------------------------------------------------------------------------
8681 +   Error codes
8682 +---------------------------------------------------------------------------*/
8683 +#define EC_CRITICAL         (1<<CRITICAL_SHIFT)
8684 +#define EC_NO_ERRORS        0
8685 +#define EC_VAL_NO_BASE      EC_ERR(1)
8686 +#define EC_VAL_NO_RESET_BIT EC_ERR(2)
8687 +#define EC_VAL_NO_RESET     EC_ERR(3)
8688 +#define EC_VAL_BAD_BASE     EC_ERR(4)
8689 +#define EC_VAL_MALLOCFAILED EC_ERR(5)
8690 +#define EC_VAL_NO_RESETBASE EC_ERR(6)
8691 +#define EC_DEVICE_NOT_FOUND EC_ERR(7)
8692 +
8693 +/*---------------------------------------------------------------------------
8694 +   Function declarations
8695 +---------------------------------------------------------------------------*/
8696 +extern void ec_log_error( unsigned int );
8697 +
8698 +#endif /* _INC_EC_ERRORS */
8699 diff -urN linux.old/drivers/net/avalanche_cpmac/hcpmac.c linux.dev/drivers/net/avalanche_cpmac/hcpmac.c
8700 --- linux.old/drivers/net/avalanche_cpmac/hcpmac.c      1970-01-01 01:00:00.000000000 +0100
8701 +++ linux.dev/drivers/net/avalanche_cpmac/hcpmac.c      2005-07-12 02:48:42.174574000 +0200
8702 @@ -0,0 +1,1878 @@
8703 +/******************************************************************************
8704 + *  TNETDxxxx Software Support
8705 + *  Copyright (c) 2002-2004 Texas Instruments Incorporated. All Rights Reserved.
8706 + *
8707 + *  FILE:
8708 + *
8709 + *  DESCRIPTION:
8710 + *      This file contains the code for the HAL EMAC Bridge Test
8711 + *
8712 + *  HISTORY:
8713 + *  xxXxx01 Denis            RC1.00  Original Version created.
8714 + *  22Jan02 Denis/Mick       RC1.01  Modified for HAL EMAC API
8715 + *  24Jan02 Denis/Mick       RC1.02  Speed Improvements
8716 + *  28Jan02 Denis/Mick       RC1.16  Made function calls pointers
8717 + *  28Jan02 Mick             RC1.18  Split into separate modules
8718 + *  29Jan02 Mick             RC1.19  Hal include file cleaned up
8719 + *  15Jul02 Michael Hanrahan RC1.20  Synch'd with Linux Version
8720 + *  23Sep02 Michael Hanrahan RC1.21  Added CPPI.C
8721 + *  16Oct02 Michael Hanrahan RC1.22  Added CAF etc to Options.Conf
8722 + *  09Jan03 Michael Hanrahan RC3.01  Fixed incorrect MDIO check
8723 + *  01Feb03 Michael Hanrahan RC3.02  Updated for GPIO/PBUSFREQ
8724 + *  29Mar03 Michael Hanrahan 1.03 Corrected  ChannelConfigGet
8725 + *  29Mar03 Michael Hanrahan 1.03 Removed user setting of TxNumQueues
8726 + *  23Aug04 Michael Hanrahan 1.7.8 Support for Setting Mac Address
8727 + *  @author Michael Hanrahan
8728 + *  @version 1.02
8729 + *  @date    24-Jan-2002
8730 + *****************************************************************************/
8731 +#define _HAL_CPMAC
8732 +#define _CPHAL_CPMAC
8733 +#define _CPHAL
8734 +#define __CPHAL_CPMDIO
8735 +
8736 +#include "dox_cpmac.h"  /*  Documentation information */
8737 +
8738 +/*  OS Data Structure definitions  */
8739 +
8740 +typedef void OS_PRIVATE;
8741 +typedef void OS_DEVICE;
8742 +typedef void OS_SENDINFO;
8743 +typedef void OS_RECEIVEINFO;
8744 +typedef void OS_SETUP;
8745 +
8746 +/*  HAL Data Structure definitions  */
8747 +
8748 +typedef struct _phy_device PHY_DEVICE;
8749 +typedef struct hal_device  HAL_DEVICE;
8750 +typedef struct hal_private HAL_PRIVATE;
8751 +typedef struct hal_private HAL_RECEIVEINFO;
8752 +
8753 +#include "cpcommon_cpmac.h"
8754 +#include "cpswhal_cpmac.h"
8755 +#include "cpmdio.h"
8756 +#include "hcpmac.h"
8757 +#include "cpmac_reg.h"
8758 +
8759 +
8760 +#define EC_MODULE
8761 +
8762 +/* MDIO Clock Frequency Default Value */
8763 +
8764 +/* Rcb/Tcb Constants */
8765 +
8766 +#define CB_SOF_BIT         (1<<31)
8767 +#define CB_EOF_BIT         (1<<30)
8768 +#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
8769 +#define CB_OWNERSHIP_BIT   (1<<29)
8770 +#define CB_EOQ_BIT         (1<<28)
8771 +#define CB_SIZE_MASK       0x0000ffff
8772 +#define RCB_ERRORS_MASK    0x03fe0000
8773 +
8774 +static char *channel_names[]   = CHANNEL_NAMES; /* GSG 11/22 (may change this implementation) */
8775 +
8776 +#define scFound(Module) if (HalDev->State != enDevFound)    return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8777 +#define scInit(Module)  if (HalDev->State <  enInitialized) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8778 +#define scOpen(Module)  if (HalDev->State <  enOpened)      return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8779 +
8780 +
8781 +
8782 +/********************************************************************
8783 +**
8784 +**  L O C A L  F U N C T I O N S
8785 +**
8786 +********************************************************************/
8787 +static int halIsr(HAL_DEVICE *HalDev, int *MorePackets);
8788 +static int cpmacRandom(HAL_DEVICE *HalDev);
8789 +static int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max);
8790 +static int halPacketProcessEnd(HAL_DEVICE *HalDev);
8791 +
8792 +#include "cpcommon_cpmac.c"                                                /*~RC3.02*/
8793 +#include "cppi_cpmac.c"
8794 +#include "cpmdio.c"                                                  /*~RC3.02*/
8795 +
8796 +static int MacAddressSave(HAL_DEVICE *HalDev, unsigned char *MacAddr)
8797 +  {
8798 +  int i;
8799 +  int inst             = HalDev->inst;
8800 +
8801 +  HalDev->MacAddr = MacAddr;
8802 +
8803 +  if(HalDev->debug)
8804 +    {
8805 +    dbgPrintf("MacAddrSave[%d]: ", inst);
8806 +    for (i=0;i<6;i++)
8807 +       dbgPrintf("%X", HalDev->MacAddr[i]);
8808 +    dbgPrintf("\n");
8809 +    osfuncSioFlush();
8810 +    }
8811 +  return(EC_NO_ERRORS);
8812 +  }
8813 +static int MacAddressSet(HAL_DEVICE *HalDev)
8814 +  {
8815 +  unsigned char *macadr = &HalDev->MacAddr[0];
8816 +  int base             = HalDev->dev_base;
8817 +
8818 +  scOpen(EC_CPMAC);
8819 +  CPMAC_MACADDRLO_0(base) = macadr[5];
8820 +  CPMAC_MACADDRMID(base)  = macadr[4];
8821 +  CPMAC_MACADDRHI(base)   = (macadr[0])|(macadr[1]<<8)|(macadr[2]<<16)|(macadr[3]<<24);
8822 +  if(HalDev->debug)
8823 +    {
8824 +     dbgPrintf("MacAddrSet: MacAddr(%d) %X %X %X\n", HalDev->inst, CPMAC_MACADDRLO_0(base),
8825 +                                                     CPMAC_MACADDRMID(base),
8826 +                                                     CPMAC_MACADDRHI(base));
8827 +
8828 +     dbgPrintf("Start MAC: %d\n",HalDev->dev_base);
8829 +     osfuncSioFlush();
8830 +    }
8831 +  return(EC_NO_ERRORS);
8832 +  }
8833 +
8834 +
8835 +/*
8836 +  Updates the MacHash registers
8837 +*/
8838 +static void MacHashSet(HAL_DEVICE *HalDev)
8839 +  {
8840 +  if(HalDev->State <  enOpened)
8841 +    return;
8842 +
8843 +  CPMAC_MACHASH1(HalDev->dev_base) = HalDev->MacHash1;
8844 +  CPMAC_MACHASH2(HalDev->dev_base) = HalDev->MacHash2;
8845 +  if (DBG(11))
8846 +    dbgPrintf("CPMAC[%X]: MacHash1 0x%08X, MacHash2 0x%08X\n", HalDev->dev_base, CPMAC_MACHASH1(HalDev->dev_base), CPMAC_MACHASH2(HalDev->dev_base));
8847 +  }
8848 +
8849 +/*
8850 +  Reads the MacControl register and updates
8851 +  the changable bits. (See MACCONTROL_MASK)
8852 +*/
8853 +static void RxMBP_EnableSet(HAL_DEVICE *HalDev)
8854 +  {
8855 +   bit32u RxMbpEnable;
8856 +   if(HalDev->State <  enOpened)
8857 +     return;
8858 +   RxMbpEnable  = CPMAC_RX_MBP_ENABLE(HalDev->dev_base);
8859 +   RxMbpEnable &= ~RX_MBP_ENABLE_MASK; /* Clear out updatable bits */
8860 +   RxMbpEnable |= HalDev->RxMbpEnable;
8861 +   CPMAC_RX_MBP_ENABLE(HalDev->dev_base) = RxMbpEnable;
8862 +  }
8863 +/*
8864 +  Reads the MacControl register and updates
8865 +  the changable bits. (See MACCONTROL_MASK)
8866 +*/
8867 +static void MacControlSet(HAL_DEVICE *HalDev)
8868 +  {
8869 +   bit32u MacControl;
8870 +   if(HalDev->State <  enOpened)
8871 +     return;
8872 +   MacControl  = CPMAC_MACCONTROL(HalDev->dev_base);
8873 +   MacControl &= ~MACCONTROL_MASK; /* Clear out updatable bits */
8874 +   MacControl |= HalDev->MacControl;
8875 +   if(!(MacControl & MII_EN)) /* If Enable is not set just update register  */
8876 +      CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8877 +   else
8878 +     {
8879 +     if(MacControl & CTRL_LOOPBACK)    /*  Loopback Set  */
8880 +       {
8881 +       /* mii_en is set and loopback is needed,
8882 +          clear mii_en, set loopback, then set mii_en
8883 +       */
8884 +       MacControl &= ~MII_EN;  /* Clear MII_EN  */
8885 +       CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8886 +       CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN; /* Set MII_EN  */
8887 +       HalDev->Linked = 1; /* if in loopback the logically linked */
8888 +       }
8889 +     else  /* If Loopback not set just update */
8890 +       {
8891 +       CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8892 +       }
8893 +     }
8894 +    if(DBG(0))
8895 +      dbgPrintf("[halMacControlSet]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
8896 +  }
8897 +static int UnicastSet(HAL_DEVICE *HalDev)
8898 +  {
8899 +  CPMAC_RX_UNICAST_SET(HalDev->dev_base)    = HalDev->RxUnicastSet;
8900 +  CPMAC_RX_UNICAST_CLEAR(HalDev->dev_base)  = HalDev->RxUnicastClear;
8901 +  return(EC_NO_ERRORS);
8902 +  }
8903 +
8904 +
8905 +static bit32u HashGet(bit8u *Address)
8906 +  {
8907 +  bit32u hash;
8908 +    bit8u  tmpval;
8909 +    int    i;
8910 +
8911 +    hash = 0;
8912 +    for( i=0; i<2; i++ )
8913 +    {
8914 +        tmpval = *Address++;
8915 +        hash  ^= (tmpval>>2)^(tmpval<<4);
8916 +        tmpval = *Address++;
8917 +        hash  ^= (tmpval>>4)^(tmpval<<2);
8918 +        tmpval = *Address++;
8919 +        hash  ^= (tmpval>>6)^(tmpval);
8920 +    }
8921 +
8922 +    return( hash & 0x3F );
8923 +  }
8924 +
8925 +static void HashAdd(HAL_DEVICE *HalDev, bit8u *MacAddress)
8926 +{
8927 +  bit32u HashValue;
8928 +  bit32u HashBit;
8929 +
8930 +  HashValue = HashGet(MacAddress);
8931 +
8932 +  if(HashValue < 32)
8933 +    {
8934 +    HashBit = (1 << HashValue);
8935 +    HalDev->MacHash1 |= HashBit;
8936 +    }
8937 +    else
8938 +    {
8939 +    HashBit = (1 << (HashValue-32));
8940 +    HalDev->MacHash2 |= HashBit;
8941 +    }
8942 +}
8943 +
8944 +static void HashDel(HAL_DEVICE *HalDev, bit8u *MacAddress)
8945 +{
8946 +  bit32u HashValue;
8947 +  bit32u HashBit;
8948 +
8949 +  HashValue = HashGet(MacAddress);
8950 +
8951 +  if(HashValue < 32)
8952 +    {
8953 +    HashBit = (1 << HashValue);
8954 +    HalDev->MacHash1 &= ~HashBit;
8955 +    }
8956 +    else
8957 +    {
8958 +    HashBit = (1 << (HashValue-32));
8959 +    HalDev->MacHash2 &= ~HashBit;
8960 +    }
8961 +}
8962 +
8963 +/*  Replace with an array based on key, with a ptr to the code to do */
8964 +/* e.g.  [enRX_PASS_CRC] = {Set, MBP_UPDATE() } */
8965 +static void DuplexUpdate(HAL_DEVICE *HalDev)
8966 +{
8967 +  int base           = HalDev->dev_base;
8968 +  PHY_DEVICE *PhyDev = HalDev->PhyDev;
8969 +
8970 +  if(HalDev->State <  enOpened)
8971 +    return;
8972 +
8973 +   /* No Phy Condition */
8974 +   if(HalDev->MdioConnect & _CPMDIO_NOPHY)                        /*MJH+030805*/
8975 +   {
8976 +       /*  No Phy condition, always linked */
8977 +       HalDev->Linked     = 1;
8978 +       HalDev->EmacSpeed  = 1;
8979 +       HalDev->EmacDuplex = 1;
8980 +       HalDev->PhyNum     = 0xFFFFFFFF;  /* No Phy Num */
8981 +       CPMAC_MACCONTROL(base) |= FULLDUPLEX;                      /*MJH+030909*/
8982 +       osfuncStateChange();
8983 +       return;
8984 +   }
8985 +
8986 +  if(HalDev->MacControl & CTRL_LOOPBACK)    /*  Loopback Set  */
8987 +    {
8988 +    HalDev->Linked = 1;
8989 +    return;
8990 +    }
8991 +
8992 +  if (HalDev->MdioConnect & _CPMDIO_LOOPBK)
8993 +    {
8994 +    HalDev->Linked = cpMacMdioGetLoopback(HalDev->PhyDev);
8995 +    }
8996 +  else
8997 +    {
8998 +    HalDev->Linked = cpMacMdioGetLinked(HalDev->PhyDev);
8999 +    }
9000 +  if (HalDev->Linked)
9001 +    {
9002 +     /*  Retreive Duplex and Speed and the Phy Number  */
9003 +     if(HalDev->MdioConnect & _CPMDIO_LOOPBK)
9004 +       HalDev->EmacDuplex = 1;
9005 +     else
9006 +       HalDev->EmacDuplex = cpMacMdioGetDuplex(PhyDev);
9007 +     HalDev->EmacSpeed  = cpMacMdioGetSpeed(PhyDev);
9008 +     HalDev->PhyNum     = cpMacMdioGetPhyNum(PhyDev);
9009 +
9010 +     if(HalDev->EmacDuplex)
9011 +       CPMAC_MACCONTROL(base) |= FULLDUPLEX;
9012 +     else
9013 +       CPMAC_MACCONTROL(base) &= ~FULLDUPLEX;
9014 +     if(HalDev->debug)
9015 +        dbgPrintf("%d: Phy= %d, Speed=%s, Duplex=%s\n",HalDev->inst,HalDev->PhyNum,(HalDev->EmacSpeed)?"100":"10",(HalDev->EmacDuplex)?"Full":"Half");
9016 +    }
9017 +  if(HalDev->debug)
9018 +     dbgPrintf("DuplexUpdate[%d]: MACCONTROL 0x%08X, %s\n", HalDev->inst, CPMAC_MACCONTROL(base),(HalDev->Linked)?"Linked":"Not Linked");
9019 +}
9020 +static void MdioSetPhyMode(HAL_DEVICE *HalDev)
9021 +  {
9022 +  unsigned int PhyMode;
9023 +  /* Verify proper device state */
9024 +  if (HalDev->State < enOpened)
9025 +    return;
9026 +
9027 +  PhyMode = NWAY_AUTO|NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10;
9028 +  if(DBG(0))
9029 +    {
9030 +    dbgPrintf("halSetPhyMode1: MdioConnect:%08X ,", HalDev->MdioConnect);
9031 +    dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
9032 +           PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
9033 +           PhyMode&NWAY_HD100);
9034 +    }
9035 +
9036 +
9037 +  if (  HalDev->MdioConnect & _CPMDIO_NEG_OFF)  /* ~RC3.01                */
9038 +    PhyMode &= ~(NWAY_AUTO);                    /* Disable Auto Neg       */
9039 +  if (!(HalDev->MdioConnect & _CPMDIO_HD))
9040 +    PhyMode &= ~(NWAY_HD100|NWAY_HD10);         /* Cannot support HD      */
9041 +  if (!(HalDev->MdioConnect & _CPMDIO_FD))
9042 +    PhyMode &= ~(NWAY_FD100|NWAY_FD10);         /* Cannot support FD      */
9043 +  if (!(HalDev->MdioConnect & _CPMDIO_10))
9044 +    PhyMode &= ~(NWAY_HD10|NWAY_FD10);          /* Cannot support 10 Mbs  */
9045 +  if (!(HalDev->MdioConnect & _CPMDIO_100))
9046 +    PhyMode &= ~(NWAY_HD100|NWAY_FD100);        /* Cannot support 100 Mbs */
9047 +
9048 +  if(HalDev->MdioConnect & _CPMDIO_AUTOMDIX)   PhyMode |= NWAY_AUTOMDIX; /* Set AutoMdix */
9049 +
9050 +  if (HalDev->CpmacFrequency <= 50000000)
9051 +    PhyMode &= ~(NWAY_FD100|NWAY_HD100); /* Cannot support 100 MBS */
9052 +  if(DBG(7))
9053 +    dbgPrintf("halNeg: PhyMode[0x%08X] %d\n", HalDev->dev_base, PhyMode);
9054 +
9055 +  if(DBG(0))
9056 +    {
9057 +    dbgPrintf("halSetPhyMode2: MdioConnect:%08X ,", HalDev->MdioConnect);
9058 +    dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
9059 +               PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
9060 +               PhyMode&NWAY_HD100);
9061 +    }
9062 +
9063 +
9064 +  cpMacMdioSetPhyMode(HalDev->PhyDev,PhyMode);
9065 +  DuplexUpdate(HalDev);
9066 +  }
9067 +static int StatsClear(HAL_DEVICE *HalDev)
9068 +{
9069 +  int i;
9070 +  MEM_PTR pStats;
9071 +
9072 +  scOpen(EC_CPMAC);
9073 +
9074 +  pStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
9075 +  for (i=0;i<STATS_MAX;i++)
9076 +    {
9077 +    *(MEM_PTR)(pStats) =  0xFFFFFFFF;
9078 +    pStats++;
9079 +    }
9080 +
9081 +  return(EC_NO_ERRORS);
9082 +}
9083 +static void StatsDump(HAL_DEVICE *HalDev, void *Value)
9084 + {
9085 + MEM_PTR ptrStats;
9086 + MEM_PTR ptrValue;
9087 + int i;
9088 + ptrStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
9089 + ptrValue = (bit32u*) Value;
9090 + for (i=0; i<STATS_MAX; i++)
9091 +  {
9092 +     *ptrValue = *ptrStats;
9093 +     if(DBG(4))
9094 +      {
9095 +      dbgPrintf("halStatsDump: Stat[%d:0x%08X] %d 0x%08X %d\n", i, ptrStats, *ptrStats, ptrValue, *ptrValue);
9096 +      osfuncSioFlush();
9097 +      }
9098 +     ptrStats++;
9099 +     ptrValue++;
9100 +  }
9101 + }
9102 +static void ConfigApply(HAL_DEVICE *HalDev)
9103 +  {
9104 +  CPMAC_RX_MAXLEN(HalDev->dev_base)          = HalDev->RxMaxLen;
9105 +  CPMAC_RX_FILTERLOWTHRESH(HalDev->dev_base) = HalDev->RxFilterLowThresh;
9106 +  CPMAC_RX0_FLOWTHRESH(HalDev->dev_base)     = HalDev->Rx0FlowThresh;
9107 +  UnicastSet(HalDev);
9108 +  MacAddressSet(HalDev);
9109 +  RxMBP_EnableSet(HalDev);
9110 +  MacHashSet(HalDev);
9111 +  MacControlSet(HalDev);
9112 +  if(DBG(0))
9113 +     dbgPrintf("ValuesUpdate[%d]: MBP_ENABLE 0x%08X\n", HalDev->inst, CPMAC_RX_MBP_ENABLE(HalDev->dev_base));
9114 +  }
9115 +static int halStatus(HAL_DEVICE *HalDev)
9116 +{
9117 +   int status;
9118 +
9119 +    if(HalDev->State <  enOpened)
9120 +      return (EC_CPMAC|EC_FUNC_STATUS|EC_VAL_INVALID_STATE);      /*MJH+030805*/
9121 +
9122 +   /* No Phy Condition */
9123 +   if(HalDev->MdioConnect & _CPMDIO_NOPHY)                        /*MJH+030805*/
9124 +   {
9125 +       /*  No Phy condition, always linked */
9126 +       status = HalDev->Linked;
9127 +       status |= CPMAC_STATUS_LINK_DUPLEX;
9128 +       status |= CPMAC_STATUS_LINK_SPEED;
9129 +       return(status);
9130 +   }
9131 +
9132 +
9133 +   if (HalDev->HostErr)  /* Adapter Check  */
9134 +    {
9135 +    bit32u tmp;
9136 +    status = CPMAC_STATUS_ADAPTER_CHECK;
9137 +    if(HalDev->MacStatus & RX_HOST_ERR_CODE)
9138 +      {
9139 +      status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
9140 +      tmp     = (HalDev->MacStatus & RX_HOST_ERR_CODE) >> 12; /* Code */
9141 +      status |= (tmp << 9); /* Code */
9142 +      tmp     = (HalDev->MacStatus & RX_ERR_CH) >> 8; /* Channel */
9143 +      status |= (tmp << 13);
9144 +      }
9145 +    else
9146 +    if(HalDev->MacStatus & TX_HOST_ERR_CODE)
9147 +      {
9148 +      status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
9149 +      tmp     = (HalDev->MacStatus & TX_HOST_ERR_CODE) >> 20; /* Code */
9150 +      status |= (tmp << 9); /* Code */
9151 +      tmp     = (HalDev->MacStatus & TX_ERR_CH) >> 16; /* Channel */
9152 +      status |= (tmp << 13);
9153 +      }
9154 +    }
9155 +   else
9156 +    {
9157 +    status = HalDev->Linked;
9158 +    if(status)
9159 +      {
9160 +      status = CPMAC_STATUS_LINK;
9161 +      if(cpMacMdioGetDuplex(HalDev->PhyDev))
9162 +        status |= CPMAC_STATUS_LINK_DUPLEX;
9163 +      if(cpMacMdioGetSpeed(HalDev->PhyDev))
9164 +        status |= CPMAC_STATUS_LINK_SPEED;
9165 +      }
9166 +    }
9167 +   if(HalDev->debug)
9168 +      dbgPrintf("[halStatus] Link Status is %d for 0x%X\n", status, HalDev->dev_base);
9169 +   return(status);
9170 +}
9171 +static int InfoAccess(HAL_DEVICE *HalDev, int Key, int Action, void *ParmValue)
9172 +  {
9173 +  int rc = 0;
9174 +  int Update=0;
9175 +
9176 +  switch (Key)
9177 +  {
9178 +    /********************************************************************/
9179 +    /*                                                                  */
9180 +    /*                      GENERAL                                     */
9181 +    /*                                                                  */
9182 +    /********************************************************************/
9183 +
9184 +    case enVersion :
9185 +         if(Action==enGET)
9186 +           {
9187 +           *(const char **)ParmValue = pszVersion_CPMAC;
9188 +           }
9189 +    break;
9190 +    case enDebug  :
9191 +         if(Action==enSET)
9192 +           {
9193 +           HalDev->debug = *(unsigned int *)ParmValue;
9194 +           }
9195 +    break;
9196 +
9197 +    case enStatus      :
9198 +         if(Action==enGET)
9199 +           {
9200 +           int status;
9201 +           status = halStatus(HalDev);
9202 +           *(int *)ParmValue = status;
9203 +           }
9204 +    break;
9205 +    /********************************************************************/
9206 +    /*                                                                  */
9207 +    /*                      RX_MBP_ENABLE                               */
9208 +    /*                                                                  */
9209 +    /********************************************************************/
9210 +
9211 +    case enRX_PASS_CRC  :
9212 +         if(Action==enSET)
9213 +           {
9214 +           UPDATE_RX_PASS_CRC(*(unsigned int *)ParmValue);
9215 +           Update=1;
9216 +           }
9217 +    break;
9218 +    case enRX_QOS_EN  :
9219 +         if(Action==enSET)
9220 +           {
9221 +           UPDATE_RX_QOS_EN(*(unsigned int *)ParmValue);
9222 +           Update=1;
9223 +           }
9224 +    break;
9225 +    case enRX_NO_CHAIN :
9226 +         if(Action==enSET)
9227 +           {
9228 +           UPDATE_RX_NO_CHAIN(*(unsigned int *)ParmValue);
9229 +           Update=1;
9230 +           }
9231 +    break;
9232 +    case enRX_CMF_EN :
9233 +         if(Action==enSET)
9234 +           {
9235 +           UPDATE_RX_CMF_EN(*(unsigned int *)ParmValue);
9236 +           Update=1;
9237 +           }
9238 +    break;
9239 +    case enRX_CSF_EN :
9240 +         if(Action==enSET)
9241 +           {
9242 +           UPDATE_RX_CSF_EN(*(unsigned int *)ParmValue);
9243 +           Update=1;
9244 +           }
9245 +    break;
9246 +    case enRX_CEF_EN :
9247 +         if(Action==enSET)
9248 +           {
9249 +           UPDATE_RX_CEF_EN(*(unsigned int *)ParmValue);
9250 +           Update=1;
9251 +           }
9252 +    break;
9253 +    case enRX_CAF_EN :
9254 +         if(Action==enSET)
9255 +           {
9256 +           UPDATE_RX_CAF_EN(*(unsigned int *)ParmValue);
9257 +           Update=1;
9258 +           }
9259 +    break;
9260 +    case enRX_PROM_CH :
9261 +         if(Action==enSET)
9262 +           {
9263 +           UPDATE_RX_PROM_CH(*(unsigned int *)ParmValue);
9264 +           Update=1;
9265 +           }
9266 +    break;
9267 +    case enRX_BROAD_EN :
9268 +         if(Action==enSET)
9269 +           {
9270 +           UPDATE_RX_BROAD_EN(*(unsigned int *)ParmValue);
9271 +           Update=1;
9272 +           }
9273 +    break;
9274 +    case enRX_BROAD_CH :
9275 +         if(Action==enSET)
9276 +           {
9277 +           UPDATE_RX_BROAD_CH(*(unsigned int *)ParmValue);
9278 +           Update=1;
9279 +           }
9280 +    break;
9281 +    case enRX_MULT_EN :
9282 +         if(Action==enSET)
9283 +           {
9284 +           UPDATE_RX_MULT_EN(*(unsigned int *)ParmValue);
9285 +           Update=1;
9286 +           }
9287 +    break;
9288 +    case enRX_MULT_CH :
9289 +         if(Action==enSET)
9290 +           {
9291 +           UPDATE_RX_MULT_CH(*(unsigned int *)ParmValue);
9292 +           Update=1;
9293 +           }
9294 +    break;
9295 +
9296 +    /********************************************************************/
9297 +    /*                                                                  */
9298 +    /*                      MAC_CONTROL                                 */
9299 +    /*                                                                  */
9300 +    /********************************************************************/
9301 +
9302 +    case enTX_PTYPE :
9303 +         if(Action==enSET)
9304 +           {
9305 +           UPDATE_TX_PTYPE(*(unsigned int *)ParmValue);
9306 +           Update=1;
9307 +           }
9308 +    break;
9309 +    case enTX_PACE :
9310 +         if(Action==enSET)
9311 +           {
9312 +           UPDATE_TX_PACE(*(unsigned int *)ParmValue);
9313 +           Update=1;
9314 +           }
9315 +    break;
9316 +    case enTX_FLOW_EN :
9317 +         if(Action==enSET)
9318 +           {
9319 +           UPDATE_TX_FLOW_EN(*(unsigned int *)ParmValue);
9320 +           Update=1;
9321 +           }
9322 +    break;
9323 +    case enRX_FLOW_EN :
9324 +         if(Action==enSET)
9325 +           {
9326 +           UPDATE_RX_FLOW_EN(*(unsigned int *)ParmValue);
9327 +           Update=1;
9328 +           }
9329 +    break;
9330 +
9331 +    case enCTRL_LOOPBACK :
9332 +         if(Action==enSET)
9333 +           {
9334 +           UPDATE_CTRL_LOOPBACK(*(unsigned int *)ParmValue);
9335 +           Update=1;
9336 +           }
9337 +    break;
9338 +    /********************************************************************/
9339 +    /*                                                                  */
9340 +    /*                      RX_UNICAST_SET                              */
9341 +    /*                                                                  */
9342 +    /********************************************************************/
9343 +
9344 +    case enRX_UNICAST_SET :
9345 +         if(Action==enSET)
9346 +          {
9347 +           HalDev->RxUnicastSet   |=  (1 << *(unsigned int *)ParmValue);
9348 +           HalDev->RxUnicastClear &= ~(1 << *(unsigned int *)ParmValue);
9349 +           Update=1;
9350 +          }
9351 +    break;
9352 +    case enRX_UNICAST_CLEAR :
9353 +         if(Action==enSET)
9354 +          {
9355 +          HalDev->RxUnicastClear |=  (1 << *(unsigned int *)ParmValue);
9356 +          HalDev->RxUnicastSet   &= ~(1 << *(unsigned int *)ParmValue);
9357 +          Update=1;
9358 +          }
9359 +    break;
9360 +
9361 +    case enRX_MAXLEN :
9362 +         if(Action==enSET)
9363 +           {
9364 +           HalDev->RxMaxLen    =   *(unsigned int *)ParmValue;
9365 +           Update=1;
9366 +           }
9367 +    break;
9368 +
9369 +    case enRX_FILTERLOWTHRESH :
9370 +         if(Action==enSET)
9371 +           {
9372 +           HalDev->RxFilterLowThresh  =   *(unsigned int *)ParmValue;
9373 +           Update=1;
9374 +           }
9375 +    break;
9376 +    case enRX0_FLOWTHRESH :
9377 +         if(Action==enSET)
9378 +           {
9379 +           HalDev->Rx0FlowThresh =   *(unsigned int *)ParmValue;
9380 +           Update=1;
9381 +           }
9382 +    break;
9383 +    /********************************************************************/
9384 +    /*                                                                  */
9385 +    /*                      RX_MULTICAST                                */
9386 +    /*                                                                  */
9387 +    /********************************************************************/
9388 +
9389 +    case enRX_MULTICAST :
9390 +    break;
9391 +    case enRX_MULTI_SINGLE :
9392 +         if(DBG(11))
9393 +          {
9394 +           int tmpi;
9395 +           bit8u *MacAddress;
9396 +           MacAddress = (bit8u *) ParmValue;
9397 +           dbgPrintf("CPMAC[%X]:  MacAddress '", HalDev->dev_base);
9398 +           for (tmpi=0; tmpi<6; tmpi++)
9399 +             dbgPrintf("%02X:", MacAddress[tmpi]);
9400 +             dbgPrintf("\n");
9401 +          }
9402 +         if(Action==enCLEAR)
9403 +           {
9404 +           HashDel(HalDev, ParmValue);
9405 +           Update=1;
9406 +           }
9407 +         else
9408 +         if(Action==enSET)
9409 +           {
9410 +           HashAdd(HalDev, ParmValue);
9411 +           Update=1;
9412 +           }
9413 +    break;
9414 +    case enRX_MULTI_ALL :
9415 +         if(Action==enCLEAR)
9416 +           {
9417 +           HalDev->MacHash1 = 0;
9418 +           HalDev->MacHash2 = 0;
9419 +           Update=1;
9420 +           }
9421 +         else
9422 +         if(Action==enSET)
9423 +           {
9424 +           HalDev->MacHash1 = 0xFFFFFFFF;
9425 +           HalDev->MacHash2 = 0xFFFFFFFF;
9426 +           Update=1;
9427 +           }
9428 +    break;
9429 +
9430 +    /********************************************************************/
9431 +    /*                                                                  */
9432 +    /*                      MDIO                                        */
9433 +    /*                                                                  */
9434 +    /********************************************************************/
9435 +
9436 +    case enMdioConnect :
9437 +         if(Action==enSET)
9438 +           {
9439 +           HalDev->MdioConnect = *(unsigned int *)ParmValue;
9440 +           MdioSetPhyMode(HalDev);
9441 +           }
9442 +           if(Action==enGET)
9443 +           {
9444 +           *(unsigned int *)ParmValue = HalDev->MdioConnect;
9445 +           }
9446 +    break;
9447 +
9448 +
9449 +    /********************************************************************/
9450 +    /*                                                                  */
9451 +    /*                      STATISTICS                                  */
9452 +    /*                                                                  */
9453 +    /********************************************************************/
9454 +    case enStatsClear :
9455 +           StatsClear(HalDev);
9456 +    break;
9457 +    case enStatsDump :
9458 +         if(Action==enGET)
9459 +           {
9460 +           StatsDump(HalDev, ParmValue);
9461 +           }
9462 +    break;
9463 +
9464 +/*  Not implemented
9465 +    case enStats1 :
9466 +         if(Action==enGET)
9467 +           {
9468 +           StatsGet(HalDev, ParmValue, 1);
9469 +           }
9470 +    break;
9471 +
9472 +    case enStats2 :
9473 +         if(Action==enGET)
9474 +           {
9475 +           StatsGet(HalDev, ParmValue, 2);
9476 +           }
9477 +    break;
9478 +    case enStats3 :
9479 +         if(Action==enGET)
9480 +           {
9481 +           StatsGet(HalDev, ParmValue, 3);
9482 +           }
9483 +    break;
9484 +    case enStats4 :
9485 +         if(Action==enGET)
9486 +           {
9487 +           StatsGet(HalDev, ParmValue, 4);
9488 +           }
9489 +    break;
9490 +
9491 +*/
9492 +
9493 +    default:
9494 +    rc = EC_CPMAC|EC_FUNC_OPTIONS|EC_VAL_KEY_NOT_FOUND;
9495 +    break;
9496 +  }
9497 +
9498 +  /* Verify proper device state */
9499 +  if (HalDev->State == enOpened)
9500 +    switch (Update)
9501 +      {
9502 +      case 1 :
9503 +           ConfigApply(HalDev);
9504 +      break;
9505 +      default:
9506 +      break;
9507 +      }
9508 +
9509 +  return (rc);
9510 +  }
9511 +static const char pszStats[]       = "Stats;";
9512 +
9513 +static int halControl(HAL_DEVICE *HalDev, const char *pszKey, const char *pszAction, void *Value)
9514 +  {
9515 +  int i;
9516 +  int rc=0;
9517 +  int Action;
9518 +  int ActionFound;
9519 +  int KeyFound;
9520 +
9521 +#ifdef __CPHAL_DEBUG
9522 +  if (DBG(1))
9523 +    {
9524 +    dbgPrintf("\nhalControl-HalDev:%08X,Action:%s,Key:%s\n", (bit32u)HalDev, pszAction, pszKey);
9525 +    }
9526 +#endif
9527 +
9528 +  /* 23Aug04 - BCIL needs to set Mac Address  */
9529 +  if(HalDev->OsFunc->Strcmpi(pszKey, pszMacAddr) == 0)
9530 +    {
9531 +    KeyFound=1;
9532 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9533 +      {
9534 +        unsigned char *MacAddr;
9535 +        MacAddr = (unsigned char *) Value;
9536 +        MacAddressSave(HalDev, MacAddr);
9537 +        MacAddressSet(HalDev);
9538 +        return(0);
9539 +      }
9540 +    else
9541 +      {
9542 +       return(-1);
9543 +      }
9544 +    }
9545 +
9546 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcLinked) == 0)
9547 +    {
9548 +    KeyFound=1;
9549 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9550 +      {
9551 +        HalDev->Linked = *(int *)Value;
9552 +        return(0);
9553 +      }
9554 +    else
9555 +      {
9556 +       return(-1);
9557 +      }
9558 +    }
9559 +
9560 +  if(HalDev->OsFunc->Strcmpi(pszKey, "TxIntDisable") == 0)
9561 +    {
9562 +    KeyFound=1;
9563 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9564 +      {
9565 +        HalDev->TxIntDisable = *(int *)Value;
9566 +        if(HalDev->TxIntDisable && (HalDev->State == enOpened))
9567 +          {
9568 +              /* if Opened and need TxIntDisabled, clear Ints for Channel 0 */
9569 +              CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 1;
9570 +          }
9571 +        return(0);
9572 +      }
9573 +    else
9574 +      {
9575 +       return(-1);
9576 +      }
9577 +    }
9578 +
9579 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyAccess) == 0)
9580 +    {
9581 +    bit32u RegAddr;
9582 +    bit32u PhyNum;
9583 +    bit32u Data;
9584 +    bit32u ValueIn;
9585 +
9586 +    ValueIn = *(bit32u*) Value;
9587 +
9588 +    KeyFound=1;
9589 +    /* Cannot access MII if not opended */
9590 +
9591 +    if(HalDev->State < enOpened)
9592 +      return(-1);
9593 +
9594 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9595 +      {
9596 +
9597 +      PhyNum  = (ValueIn & 0x1F);        /* Phynum 0-32 */
9598 +      RegAddr = (ValueIn >> 5) & 0xFF;   /* RegAddr in upper 11 bits */
9599 +
9600 +      *(bit32u*)Value = _mdioUserAccessRead(HalDev->PhyDev, RegAddr, PhyNum);
9601 +
9602 +      return(0);
9603 +      } /* end of hcGet */
9604 +
9605 +
9606 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9607 +      {
9608 +      PhyNum  = (ValueIn & 0x1F);        /* Phynum 0-32 */
9609 +      RegAddr = (ValueIn >> 5) & 0xFF;   /* RegAddr in upper 11 bits of lower 16 */
9610 +
9611 +      Data    = ValueIn >> 16;           /* Data store in upper 16 bits */
9612 +
9613 +      _mdioUserAccessWrite(HalDev->PhyDev, RegAddr, PhyNum, Data);
9614 +      return(0);
9615 +      }
9616 +    } /*  End of hcPhyAccess */
9617 +
9618 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyNum) == 0)
9619 +    {
9620 +    KeyFound=1;
9621 +    if(!HalDev->Linked)
9622 +      return(-1);  /* if not linked the no Phy Connected */
9623 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9624 +      {
9625 +        *(int *)Value = HalDev->PhyNum;
9626 +      return(0);
9627 +      }
9628 +    }
9629 +
9630 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacSize) == 0)
9631 +    {
9632 +    KeyFound=1;
9633 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9634 +      {
9635 +        *(bit32u *)Value = HalDev->CpmacSize;
9636 +      return(0);
9637 +      }
9638 +    }
9639 +
9640 +   if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacBase) == 0)
9641 +    {
9642 +    KeyFound=1;
9643 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9644 +      {
9645 +        *(int *)Value = HalDev->dev_base;
9646 +      return(0);
9647 +      }
9648 +    }
9649 +
9650 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcFullDuplex) == 0)
9651 +    {
9652 +    KeyFound=1;
9653 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9654 +      {
9655 +        UPDATE_FULLDUPLEX(*(unsigned int *)Value);
9656 +        if(HalDev->State == enOpened)
9657 +           ConfigApply(HalDev);
9658 +      return(0);
9659 +      }
9660 +    else
9661 +      return(-1);
9662 +    }
9663 +
9664 +  if(HalDev->OsFunc->Strcmpi(pszKey, pszDebug) == 0)
9665 +    {
9666 +    KeyFound=1;
9667 +    if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9668 +      {
9669 +        ActionFound=1;
9670 +        HalDev->debug = *(int *)Value;
9671 +      }
9672 +    }
9673 +
9674 +  if(HalDev->OsFunc->Strcmpi(pszKey, hcMaxFrags) == 0)
9675 +    {
9676 +     KeyFound=1;
9677 +     if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9678 +       {
9679 +        ActionFound=1;
9680 +
9681 +        if ((*(int *)Value) > 0)
9682 +          HalDev->MaxFrags = *(int *)Value;
9683 +         else
9684 +          rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_VALUE);
9685 +      }
9686 +
9687 +     if (HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9688 +       {
9689 +        ActionFound=1;
9690 +
9691 +        *(int *)Value = HalDev->MaxFrags;
9692 +       }
9693 +    }
9694 +
9695 +  if(HalDev->OsFunc->Strstr(pszKey, pszStats) != 0)
9696 +    {
9697 +     KeyFound=1;
9698 +     if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9699 +         {
9700 +       int Level;
9701 +       int Ch;
9702 +       char *TmpKey = (char *)pszKey;
9703 +       ActionFound=1;
9704 +       TmpKey += HalDev->OsFunc->Strlen(pszStats);
9705 +       Level   = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
9706 +       TmpKey++;
9707 +       Ch      = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
9708 +       TmpKey++;
9709 +       osfuncSioFlush();
9710 +#ifdef __CPHAL_DEBUG
9711 +  if (DBG(1))
9712 +    {
9713 +    dbgPrintf("\nhalControl-HalDev:%08X, Level:%d, Ch:%d\n", (bit32u)HalDev, Level, Ch);
9714 +    }
9715 +#endif
9716 +         StatsGet(HalDev, (void **)Value, Level, Ch, 0);
9717 +       osfuncSioFlush();
9718 +         }
9719 +    }
9720 +
9721 +
9722 +  if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9723 +    Action = enSET;
9724 +  else
9725 +  if(HalDev->OsFunc->Strcmpi(pszAction, hcClear) == 0)
9726 +    Action = enCLEAR;
9727 +  else
9728 +  if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9729 +    Action = enGET;
9730 +  else
9731 +    Action = enNULL;
9732 +
9733 +
9734 +
9735 +  for(i=enCommonStart+1;i<enCommonEnd;i++)
9736 +    {
9737 +    if(HalDev->OsFunc->Strcmpi(KeyCommon[i].strKey, pszKey)==0)
9738 +      {
9739 +      rc = InfoAccess(HalDev, KeyCommon[i].enKey, Action, Value);
9740 +      }
9741 +    }
9742 +  for(i=enCpmacStart+1;i<enCpmacEnd;i++)
9743 +    {
9744 +    if(HalDev->OsFunc->Strcmpi(KeyCpmac[i].strKey, pszKey)==0)
9745 +      {
9746 +      rc = InfoAccess(HalDev, KeyCpmac[i].enKey, Action, Value);
9747 +      }
9748 +    }
9749 +/*
9750 +  if (KeyFound == 0)
9751 +    rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND);
9752 +
9753 +  if (ActionFound == 0)
9754 +    rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND);
9755 +*/
9756 +
9757 +  return(rc);
9758 +  }
9759 +static bit32u ConfigGet(HAL_DEVICE *HalDev)
9760 +  {
9761 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
9762 +  char *DeviceInfo     = HalDev->DeviceInfo;
9763 +  int i                = HalDev->inst;
9764 +  bit32u Value;
9765 +  int Error;
9766 +
9767 +  /* get the configuration parameters common to all modules */
9768 +  Error = ConfigGetCommon(HalDev);
9769 +  if (Error) return (EC_CPMAC|Error);
9770 +
9771 +  if (HalDev->debug)
9772 +    {
9773 +      dbgPrintf("ConfigGet: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
9774 +      osfuncSioFlush();
9775 +    }
9776 +
9777 +  Error = OsFunc->DeviceFindParmUint(DeviceInfo, pszMdioConnect,&Value); /*MJH+030805*/
9778 +  if(!Error) HalDev->MdioConnect = Value;
9779 +
9780 +  Error = OsFunc->DeviceFindParmUint(DeviceInfo, "PhyMask",&Value);
9781 +  if(!Error) HalDev->PhyMask = Value;
9782 +
9783 +  Error = OsFunc->DeviceFindParmUint(DeviceInfo, "MLink",&Value);
9784 +  if(!Error) HalDev->MLinkMask = Value;
9785 +
9786 +  Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcMdixMask, &Value);
9787 +  if(!Error)
9788 +    HalDev->MdixMask = Value;
9789 +  else
9790 +    HalDev->MdixMask = 0;
9791 +
9792 +  Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcSize, &Value); /*MJH+030425*/
9793 +  if(!Error) HalDev->CpmacSize = Value;
9794 +
9795 +  for(i=enCommonStart+1;i<enCommonEnd;i++)
9796 +    {
9797 +    Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCommon[i].strKey, (bit32u*)&Value);
9798 +    if(!Error)
9799 +      {
9800 +      InfoAccess(HalDev, KeyCommon[i].enKey, enSET, (bit32u*)&Value);
9801 +      }
9802 +    }
9803 +  for(i=enCpmacStart+1;i<enCpmacEnd;i++)
9804 +    {
9805 +    Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCpmac[i].strKey, (bit32u*)&Value);
9806 +    if(!Error)
9807 +      {
9808 +      InfoAccess(HalDev, KeyCpmac[i].enKey, enSET, (bit32u*)&Value);
9809 +      }
9810 +    }
9811 +   return (EC_NO_ERRORS);
9812 +  }
9813 +
9814 +
9815 +static void ConfigInit(HAL_DEVICE *HalDev)
9816 +  {
9817 +  if(HalDev->inst == 0)
9818 +    {
9819 +     HalDev->dev_base  = 0xA8610000;
9820 +     HalDev->ResetBit  = 17;
9821 +     HalDev->interrupt = 19;
9822 +     HalDev->MLinkMask = 0;
9823 +     HalDev->PhyMask   = 0xAAAAAAAA;
9824 +    }
9825 +  else
9826 +    {
9827 +     HalDev->dev_base  = 0xA8612800;
9828 +     HalDev->ResetBit  = 21;
9829 +     HalDev->interrupt = 33;                                         /*~RC3.02*/
9830 +     HalDev->MLinkMask = 0;
9831 +     HalDev->PhyMask   = 0x55555555;
9832 +    }
9833 +  HalDev->RxMaxLen    = 1518;
9834 +  HalDev->MaxFrags    = 2;
9835 +  HalDev->MdioConnect = _CPMDIO_HD|_CPMDIO_FD|_CPMDIO_10|_CPMDIO_100|_CPMDIO_AUTOMDIX;
9836 +  HalDev->debug=0xFFFFFFFF;
9837 +  HalDev->debug=0;
9838 +  }
9839 +/* Shuts down the EMAC device
9840 + *
9841 + *@param HalDev EMAC instance. This was returned by halOpen()
9842 + *@param mode Indicates actions to tak on close.
9843 + <br>
9844 + *PARTIAL - Disable EMAC
9845 + <br>
9846 + *FULL    - Disable EMAC and call OS to free all allocated memory
9847 + *
9848 + *@retval
9849 + *        0 OK
9850 + <br>
9851 + *        Non-Zero Not OK
9852 + *
9853 + */
9854 +static int halInit( HAL_DEVICE *HalDev)
9855 +  {
9856 +   int rc;
9857 +
9858 +  /* Verify proper device state */
9859 +  if (HalDev->State != enDevFound)
9860 +    return(EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_INVALID_STATE);
9861 +
9862 +  /* Configure HAL defaults */
9863 +  ConfigInit(HalDev);
9864 +
9865 +  /* Retrieve HAL configuration parameters from data store */
9866 +  rc = ConfigGet(HalDev);
9867 +  if (rc) return (rc);
9868 +
9869 +  /* Updated 030403*/
9870 +  rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpuFrequency, hcGet, &HalDev->CpuFrequency); /*MJH+030403*/
9871 +  if(rc)
9872 +    HalDev->CpuFrequency = 20000000;  /*20 Mhz default */         /*MJH+030403*/
9873 +
9874 +  rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpmacFrequency, hcGet, &HalDev->CpmacFrequency); /*MJH+030331*/
9875 +  if(rc)
9876 +    HalDev->CpmacFrequency = HalDev->CpuFrequency/2;               /*MJH~030404*/
9877 +
9878 +  rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioBusFrequency,  hcGet, &HalDev->MdioBusFrequency);  /*MJH+030402*/
9879 +  if(rc)
9880 +    HalDev->MdioBusFrequency = HalDev->CpmacFrequency;
9881 +
9882 +  rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioClockFrequency,  hcGet, &HalDev->MdioClockFrequency);  /*MJH+030402*/
9883 +  if(rc)
9884 +    HalDev->MdioClockFrequency = 2200000; /* 2.2 Mhz PITS #14 */
9885 +
9886 +
9887 +  /* update device state */
9888 +  HalDev->State = enInitialized;
9889 +
9890 +  /* initialize statistics */
9891 +  StatsInit(HalDev);                                                  /* +RC3.02 */
9892 +
9893 +  /*                                                                  -RC3.02
9894 +  StatsTable3[0].StatPtr  = &HalDev->ChData[0].RxBufSize;
9895 +  StatsTable3[1].StatPtr  = &HalDev->ChData[0].RxBufferOffset;
9896 +  StatsTable3[2].StatPtr  = &HalDev->ChData[0].RxNumBuffers;
9897 +  StatsTable3[3].StatPtr  = &HalDev->ChData[0].RxServiceMax;
9898 +  StatsTable3[4].StatPtr  = &HalDev->ChData[0].TxNumBuffers;
9899 +  StatsTable3[5].StatPtr  = &HalDev->ChData[0].TxNumQueues;
9900 +  StatsTable3[6].StatPtr  = &HalDev->ChData[0].TxServiceMax;
9901 +  */
9902 +
9903 +  return(EC_NO_ERRORS);
9904 +  }
9905 +static int halProbe(HAL_DEVICE *HalDev)
9906 +  {
9907 +  int inst             = HalDev->inst;
9908 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
9909 +  int error_code;
9910 +
9911 +  if (HalDev->State != enConnected)
9912 +     return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_INVALID_STATE);
9913 +
9914 +  if(HalDev->debug) dbgPrintf("halProbe: %d ",inst);
9915 +
9916 +  error_code = OsFunc->DeviceFindInfo(inst,"cpmac",&HalDev->DeviceInfo);
9917 +
9918 +  if(error_code)
9919 +     return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND );
9920 +
9921 +  /* Set device state to DevFound */
9922 +  HalDev->State = enDevFound;
9923 +  return(EC_NO_ERRORS);
9924 +  }
9925 +static void ChannelConfigInit(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
9926 +  {
9927 +  int Ch        = HalChn->Channel;
9928 +  int Direction = HalChn->Direction;
9929 +  int nTxBuffers = 256;
9930 +
9931 +  if (Direction == DIRECTION_TX)
9932 +    {
9933 +    HalDev->ChData[Ch].TxNumBuffers   = nTxBuffers;
9934 +    HalDev->ChData[Ch].TxNumQueues    = 1;
9935 +    HalDev->ChData[Ch].TxServiceMax   = nTxBuffers/3;
9936 +    HalDev->TxIntThreshold[Ch]        = HalDev->ChData[Ch].TxServiceMax;
9937 +    HalDev->TxIntThresholdMaster[Ch]  = HalDev->TxIntThreshold[Ch];
9938 +    }
9939 +
9940 +  if (Direction == DIRECTION_RX)
9941 +    {
9942 +    HalDev->ChData[Ch].RxNumBuffers   = nTxBuffers*2;
9943 +    HalDev->ChData[Ch].RxBufferOffset = 0;
9944 +    HalDev->ChData[Ch].RxBufSize      = 1518;
9945 +    HalDev->ChData[Ch].RxServiceMax   = nTxBuffers/3; /*Not a typo*/
9946 +    }
9947 +  }
9948 +static int ChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
9949 +  {
9950 +   int Ch        = HalChn->Channel;
9951 +   int Direction = HalChn->Direction;
9952 +
9953 +   if (DBG(11))
9954 +     {
9955 +      dbgPrintf("halChannelConfigApply[%d:%d] haldev:0x%08X inst:%d base:0x%08X reset:%d\n", Ch, Direction, (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
9956 +      osfuncSioFlush();
9957 +     }
9958 +
9959 +   if (Direction == DIRECTION_TX)
9960 +   {
9961 +     if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
9962 +     {
9963 +      return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_TX_CH_ALREADY_OPEN);
9964 +     }
9965 +
9966 +     /* Initialize Queue Data */
9967 +     HalDev->TxActQueueHead[Ch][0]  = 0;
9968 +     HalDev->TxActQueueCount[Ch][0] = 0;
9969 +     HalDev->TxActive[Ch][0]        = FALSE;
9970 +
9971 +     /* Need to use a macro that takes channel as input */
9972 +     CPMAC_TX0_HDP(HalDev->dev_base)=0;
9973 +
9974 +     /* Initialize buffer memory for the channel */
9975 +     InitTcb(HalDev, Ch);
9976 +
9977 +     if(!HalDev->TxIntDisable)
9978 +       CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch); /* GSG 11/22 */
9979 +   }
9980 +   else
9981 +   {
9982 +     if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
9983 +     {
9984 +      return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_RX_CH_ALREADY_OPEN);
9985 +     }
9986 +
9987 +     /* Initialize Queue Data */
9988 +     HalDev->RxActQueueHead[Ch]     = 0;
9989 +     HalDev->RxActQueueCount[Ch]    = 0;
9990 +
9991 +     HalDev->RxActive[Ch]           = FALSE;
9992 +
9993 +     /* Need to use a macro that takes channel as input */
9994 +     CPMAC_RX0_HDP(HalDev->dev_base)=0;
9995 +
9996 +     /* Initialize buffer memory for the channel */
9997 +     InitRcb(HalDev, Ch);
9998 +
9999 +     CPMAC_RX_INTMASK_SET(HalDev->dev_base)  = (1<<Ch); /* GSG 11/22 */
10000 +   }
10001 +
10002 +   HalDev->ChIsOpen[Ch][Direction] = TRUE; /* channel is open */
10003 +
10004 +   return (EC_NO_ERRORS);
10005 +  }
10006 +
10007 +/* GSG 11/22
10008 + * Retrieves channel parameters from configuration file.  Any parameters
10009 + * which are not found are ignored, and the HAL default value will apply,
10010 + * unless a new value is given through the channel structure in the call
10011 + * to ChannelSetup.
10012 + */
10013 +static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
10014 +  {
10015 +  int Ch        = HalChn->Channel;
10016 +  int Direction = HalChn->Direction;
10017 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10018 +  unsigned int rc, Value;
10019 +  void *ChInfo;
10020 +
10021 +   rc=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
10022 +   /*  Do not fail if Channel Info not available for RC2 */
10023 +   if (rc) return(0);
10024 +/*   if (rc) return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);*/
10025 +
10026 +   /* i don't care if a value is not found because they are optional */
10027 +   if(Direction == DIRECTION_TX)
10028 +     {
10029 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
10030 +     if (!rc) HalDev->ChData[Ch].TxNumBuffers = Value;
10031 +
10032 +     /*rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);*/ /*MJH-030329*/
10033 +     /*if (!rc) HalDev->ChData[Ch].TxNumQueues = Value;*/              /*MJH-030329*/
10034 +
10035 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
10036 +     if (!rc)
10037 +       {
10038 +         HalDev->ChData[Ch].TxServiceMax = Value;
10039 +         HalDev->TxIntThreshold[Ch]      = HalDev->ChData[Ch].TxServiceMax;
10040 +         HalDev->TxIntThresholdMaster[Ch]  = HalDev->TxIntThreshold[Ch];
10041 +       }
10042 +     }
10043 +   if(Direction == DIRECTION_RX)
10044 +     {
10045 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
10046 +     if (!rc) HalDev->ChData[Ch].RxNumBuffers = Value;
10047 +
10048 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
10049 +     if (!rc) HalDev->ChData[Ch].RxBufferOffset = Value;
10050 +
10051 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
10052 +     if (!rc) HalDev->ChData[Ch].RxBufSize = Value;
10053 +
10054 +     rc=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
10055 +     if (!rc) HalDev->ChData[Ch].RxServiceMax = Value;
10056 +     }
10057 +   return (EC_NO_ERRORS);
10058 +  }
10059 +#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
10060 +
10061 +static void ChannelConfigUpdate(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
10062 +  {
10063 +  int Ch        = HalChn->Channel;
10064 +  int Direction = HalChn->Direction;
10065 +#ifdef __CPHAL_DEBUG
10066 +  if (DBG(1))
10067 +    {
10068 +    dbgPrintf("\nChnUpd-HalDev:%08X,Chn:%d:%d\n", (bit32u)HalDev, Ch, Direction); osfuncSioFlush();
10069 +    }
10070 +#endif
10071 +  if (Direction == DIRECTION_TX)
10072 +    {
10073 +    ChannelUpdate(TxNumBuffers);
10074 +    /*ChannelUpdate(TxNumQueues);*/                               /*MJH~030329*/
10075 +    ChannelUpdate(TxServiceMax);
10076 +    HalDev->TxIntThreshold[Ch]        = HalDev->ChData[Ch].TxServiceMax;
10077 +    HalDev->TxIntThresholdMaster[Ch]  = HalDev->TxIntThreshold[Ch];
10078 +    }
10079 +  else
10080 +  if (Direction == DIRECTION_RX)
10081 +    {
10082 +    ChannelUpdate(RxBufferOffset);
10083 +    ChannelUpdate(RxBufSize);
10084 +    ChannelUpdate(RxNumBuffers);
10085 +    ChannelUpdate(RxServiceMax);
10086 +#ifdef __CPHAL_DEBUG
10087 +  if (DBG(1))
10088 +    {
10089 +    dbgPrintf("\nRxNumBuffers %d\n",HalChn->RxNumBuffers); osfuncSioFlush();
10090 +    }
10091 +#endif
10092 +    }
10093 +  }
10094 +static int halChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn, OS_SETUP *OsSetup)
10095 +  {
10096 +  int Direction;
10097 +  int Ch;
10098 +  int rc;
10099 +
10100 +  /* Verify proper device state */
10101 +  if (HalDev->State < enInitialized)
10102 +    return (EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE);
10103 +
10104 +  /* We require the channel structure to be passed, even if it only contains
10105 +     the channel number */
10106 +  if (HalChn == NULL)
10107 +    {
10108 +     return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_NULL_CH_STRUCT);
10109 +    }
10110 +
10111 +  Ch        = HalChn->Channel;
10112 +  Direction = HalChn->Direction;
10113 +
10114 +  /* This should check on Maximum Channels for RX or TX,
10115 +     they might be different Mick 021124 */
10116 +  if ((Ch < 0) || (Ch > (MAX_CHAN-1)))
10117 +    {
10118 +     return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_CH);
10119 +    }
10120 +
10121 +  /* if channel is already open, this call is invalid */
10122 +  if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
10123 +    {
10124 +     return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
10125 +    }
10126 +
10127 +  /* channel is closed, but might be setup.  If so, reopen the hardware channel. */
10128 +  if (HalDev->ChIsSetup[Ch][Direction] == FALSE)
10129 +    {
10130 +     /* Setup channel configuration */
10131 +     HalDev->ChData[Ch].Channel = Ch;
10132 +
10133 +     /* Store OS_SETUP */
10134 +     HalDev->ChData[Ch].OsSetup = OsSetup;
10135 +
10136 +     /*  Framework :
10137 +         Set Default Values
10138 +         Update with options.conf
10139 +     Apply driver updates
10140 +     */
10141 +     ChannelConfigInit(HalDev, HalChn);
10142 +     ChannelConfigGet(HalDev, HalChn);
10143 +     ChannelConfigUpdate(HalDev, HalChn);
10144 +
10145 +     /* cppi.c needs to use Rx/TxServiceMax */
10146 +     HalDev->BuffersServicedMax  = 169;  /* TEMP */
10147 +
10148 +     HalDev->ChIsSetup[Ch][Direction] = TRUE;
10149 +    }
10150 +
10151 +  rc = EC_NO_ERRORS;
10152 +
10153 +  /* If the hardware has been opened (is out of reset), then configure the channel
10154 +     in the hardware. NOTE: ChannelConfigApply calls the CPSAR ChannelSetup()! */
10155 +  if (HalDev->State == enOpened)
10156 +    {
10157 +     rc = ChannelConfigApply(HalDev, HalChn);
10158 +    }
10159 +
10160 +  return (rc);
10161 +  }
10162 +
10163 +
10164 +static int miiInfoGet(HAL_DEVICE *HalDev, bit32u *miiBaseAddress, bit32u *miiResetBit)
10165 +  {
10166 +  int rc;
10167 +  void *DeviceInfo;
10168 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10169 +
10170 +  /*  Only one instance of cpmdio   */
10171 +  rc = OsFunc->DeviceFindInfo(0,"cpmdio",&DeviceInfo);               /*~RC3.02*/
10172 +
10173 +  if(rc)
10174 +     return (EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_DEVICE_NOT_FOUND );
10175 +
10176 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",miiBaseAddress);
10177 +  if(rc)
10178 +      rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
10179 +
10180 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",miiResetBit);
10181 +  if(rc)
10182 +      rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
10183 +
10184 +
10185 +  /* See if need to make mdio functional in GPIO */
10186 +  gpioCheck(HalDev, DeviceInfo);
10187 +
10188 +  if(DBG(0))
10189 +    dbgPrintf("miiBase: 0x%08X %u\n", *miiBaseAddress, *miiResetBit);
10190 +  return(rc);
10191 +  }
10192 +static void ephyCheck(HAL_DEVICE *HalDev)
10193 +  {                                                                  /*+RC3.02*/
10194 +  int rc;
10195 +  void *DeviceInfo;
10196 +  int mii_phy;
10197 +  int reset_bit;
10198 +  OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10199 +
10200 +  rc = OsFunc->DeviceFindInfo(0,"ephy",&DeviceInfo);
10201 +  if(rc) return;
10202 +
10203 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "mii_phy",&mii_phy);
10204 +  if(rc) return;
10205 +
10206 +  rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
10207 +  if(rc) return;
10208 +
10209 +  if (HalDev->PhyMask & (1 << mii_phy))
10210 +    {
10211 +    *(volatile bit32u *)(HalDev->ResetBase) |=  (1 << reset_bit);                      /*+RC3.02*/
10212 +    resetWait(HalDev);
10213 +    }
10214 +  }                                                                  /*+RC3.02*/
10215 +static void AutoNegotiate(HAL_DEVICE *HalDev)
10216 +  {
10217 +  int size;
10218 +  bit32u ModID,  RevMaj,  RevMin;
10219 +  PHY_DEVICE *PhyDev;
10220 +  bit32u miiBaseAddress;
10221 +  bit32u miiResetBit;
10222 +
10223 +  /* Verify proper device state */
10224 +  if (HalDev->State < enOpened)
10225 +    return;
10226 +
10227 +  miiInfoGet(HalDev, &miiBaseAddress, &miiResetBit);
10228 +
10229 +  cpMacMdioGetVer(miiBaseAddress, &ModID,  &RevMaj,  &RevMin);
10230 +  if(HalDev->debug)
10231 +     dbgPrintf("Mdio Module Id %d, Version %d.%d\n", ModID,  RevMaj,  RevMin);
10232 +
10233 +  size = cpMacMdioGetPhyDevSize();
10234 +  PhyDev = (PHY_DEVICE *) HalDev->OsFunc->Malloc( size );
10235 +
10236 +  HalDev->PhyDev = PhyDev;
10237 +
10238 +  ephyCheck(HalDev);
10239 +
10240 +  cpMacMdioInit( PhyDev, miiBaseAddress, HalDev->inst, HalDev->PhyMask, HalDev->MLinkMask, HalDev->MdixMask, HalDev->ResetBase, miiResetBit, HalDev->MdioBusFrequency, HalDev->MdioClockFrequency, HalDev->debug, HalDev); /*MJH~030402*/
10241 +  MdioSetPhyMode(HalDev);
10242 +
10243 +  return;
10244 +  }
10245 +static int halOpen(HAL_DEVICE *HalDev)
10246 +  {
10247 +  unsigned char *MacAddr;
10248 +  int i;
10249 +  int j;
10250 +  int rc, Ticks;
10251 +
10252 +  if (HalDev->debug)
10253 +    {
10254 +      dbgPrintf("halOpen: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
10255 +      osfuncSioFlush();
10256 +    }
10257 +
10258 +   /* Verify proper device state */
10259 +   if (HalDev->State < enInitialized)
10260 +     return (EC_CPMAC|EC_FUNC_OPEN|EC_VAL_INVALID_STATE);
10261 +
10262 +
10263 +  /* take CPMAC out of reset - GSG 11/20*/
10264 +  if ((VOLATILE32(HalDev->ResetBase) & (1 << HalDev->ResetBit)) != 0)
10265 +    {
10266 +     /* perform normal close duties */
10267 +     CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
10268 +     CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
10269 +     CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
10270 +
10271 +     /* disable interrupt masks */
10272 +     CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
10273 +     CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
10274 +    }
10275 +
10276 +   /* take CPMAC out of reset */
10277 +   *(volatile bit32u *)(HalDev->ResetBase) &= ~(1 << HalDev->ResetBit);
10278 +   resetWait(HalDev);
10279 +   *(volatile bit32u *)(HalDev->ResetBase) |=  (1 << HalDev->ResetBit);
10280 +   resetWait(HalDev);
10281 +
10282 +  /* After Reset clear the Transmit and Receive DMA Head Descriptor Pointers */
10283 +
10284 +  CPMAC_TX0_HDP(HalDev->dev_base)=0;
10285 +  CPMAC_TX1_HDP(HalDev->dev_base)=0;
10286 +  CPMAC_TX2_HDP(HalDev->dev_base)=0;
10287 +  CPMAC_TX3_HDP(HalDev->dev_base)=0;
10288 +  CPMAC_TX4_HDP(HalDev->dev_base)=0;
10289 +  CPMAC_TX5_HDP(HalDev->dev_base)=0;
10290 +  CPMAC_TX6_HDP(HalDev->dev_base)=0;
10291 +  CPMAC_TX7_HDP(HalDev->dev_base)=0;
10292 +
10293 +  /* Rx Init  */
10294 +
10295 +  CPMAC_RX0_HDP(HalDev->dev_base) = 0;
10296 +  CPMAC_RX1_HDP(HalDev->dev_base) = 0;
10297 +  CPMAC_RX2_HDP(HalDev->dev_base) = 0;
10298 +  CPMAC_RX3_HDP(HalDev->dev_base) = 0;
10299 +  CPMAC_RX4_HDP(HalDev->dev_base) = 0;
10300 +  CPMAC_RX5_HDP(HalDev->dev_base) = 0;
10301 +  CPMAC_RX6_HDP(HalDev->dev_base) = 0;
10302 +  CPMAC_RX7_HDP(HalDev->dev_base) = 0;
10303 +
10304 +  CPMAC_RX_BUFFER_OFFSET(HalDev->dev_base) = 0;
10305 +
10306 +  /* Init Tx and Rx DMA */
10307 +
10308 +  CPMAC_TX_CONTROL(HalDev->dev_base) |= TX_EN;
10309 +  CPMAC_RX_CONTROL(HalDev->dev_base) |= RX_EN;
10310 +
10311 +  CPMAC_MAC_INTMASK_SET(HalDev->dev_base) |=2; /* Enable Adaptercheck Ints */
10312 +  HalDev->OsFunc->Control(HalDev->OsDev, pszMacAddr, hcGet, &MacAddr); /* GSG 11/22 */
10313 +  MacAddressSave(HalDev, MacAddr);
10314 +
10315 +  HalDev->HostErr = 0;      /* Clear Adapter Check indicator */
10316 +  HalDev->State = enOpened; /* Change device state */
10317 +
10318 +  /* Start MDIO Negotiation */
10319 +  AutoNegotiate(HalDev);
10320 +
10321 +  /*  Enable the Os Timer  */
10322 +  Ticks = HalDev->CpuFrequency / 100;  /*  10 milli-secs */       /*MJH~030402*/
10323 +  HalDev->OsFunc->Control(HalDev->OsDev, pszTick, hcSet, &Ticks); /* GSG 11/22 */
10324 +  HalDev->OsFunc->IsrRegister(HalDev->OsDev, halIsr, HalDev->interrupt);
10325 +
10326 +  /* GSG +030523 Malloc space for the Rx fraglist */
10327 +  HalDev->fraglist = HalDev->OsFunc->Malloc(HalDev->MaxFrags * sizeof(FRAGLIST));
10328 +
10329 +  /* Any pre-open configuration */
10330 +
10331 +  /* For any channels that have been pre-initialized, set them up now */
10332 +  /* Note : This loop should not use MAX_CHN, it should only
10333 +            loop through Channels Setup, memory should not be reserved
10334 +            until Channel is Setup
10335 +  */
10336 +  for(i=0; i<MAX_CHAN; i++) /* i loops through Channels */
10337 +  for(j=0; j<2; j++)        /* j loops through DIRECTION values, 0 and 1  */
10338 +    {
10339 +     if(HalDev->ChIsSetup[i][j]==TRUE)   /* If the Channel and Direction have been Setup */
10340 +       if(HalDev->ChIsOpen[i][j]==FALSE) /* but not opened, then Apply Values now */
10341 +         {
10342 +          CHANNEL_INFO HalChn;
10343 +          HalChn.Channel   = i;
10344 +          HalChn.Direction = j;
10345 +          rc = ChannelConfigApply(HalDev, &HalChn);
10346 +          if(rc != EC_NO_ERRORS)
10347 +            return(rc);
10348 +         }
10349 +    }  /* End of looping through Channel/Direction */
10350 +
10351 +  ConfigApply(HalDev);  /* Apply Configuration Values to Device */
10352 +  CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN;  /* MAC_EN */
10353 +  if(DBG(0))
10354 +     dbgPrintf("[halOpen]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
10355 +  return(EC_NO_ERRORS);
10356 +  }
10357 +
10358 +#define INT_PENDING (MAC_IN_VECTOR_TX_INT_OR | MAC_IN_VECTOR_RX_INT_OR | MAC_IN_VECTOR_HOST_INT)
10359 +static int halShutdown(HAL_DEVICE *HalDev)
10360 +  {
10361 +   int Ch, Queue;                                                  /*GSG+030514*/
10362 +
10363 +   /* Verify proper device state */
10364 +   if (HalDev->State == enOpened)
10365 +     halClose(HalDev, 3); /* GSG ~030429 */
10366 +
10367 +   /* Buffer/descriptor resources may still need to be freed if a Close
10368 +      Mode 1 was performed prior to Shutdown - clean up here */    /*GSG+030514*/
10369 +   for (Ch=0; Ch<MAX_CHAN; Ch++)
10370 +     {
10371 +      if (HalDev->RcbStart[Ch] != 0)
10372 +        FreeRx(HalDev,Ch);
10373 +
10374 +      for(Queue=0; Queue<MAX_QUEUE; Queue++)
10375 +        {
10376 +         if (HalDev->TcbStart[Ch][Queue] != 0)
10377 +           FreeTx(HalDev,Ch,Queue);
10378 +        }
10379 +     }
10380 +
10381 +   /* free the HalFunc */
10382 +   HalDev->OsFunc->Free(HalDev->HalFuncPtr);
10383 +
10384 +   /* free the HAL device */
10385 +   HalDev->OsFunc->Free(HalDev);
10386 +
10387 +   return(EC_NO_ERRORS);
10388 +  }
10389 +int halIsr(HAL_DEVICE *HalDev, int *MorePackets)
10390 +{
10391 +  bit32u IntVec;
10392 +  int Serviced;
10393 +  int PacketsServiced=0;
10394 +  int Channel;
10395 +  int TxMorePackets=0;
10396 +  int RxMorePackets=0;
10397 +
10398 +  /* Verify proper device state - important because a call prior to Open would
10399 +      result in a lockup */
10400 +  if (HalDev->State != enOpened)
10401 +     return(EC_CPMAC|EC_FUNC_DEVICE_INT|EC_VAL_INVALID_STATE);
10402 +
10403 +  IntVec = CPMAC_MAC_IN_VECTOR(HalDev->dev_base);
10404 +
10405 +#ifdef __CPHAL_DEBUG
10406 +  if (DBG(0))
10407 +    {
10408 +    dbgPrintf("\nhalIsr: inst %d, IntVec 0x%X\n", HalDev->inst, IntVec); osfuncSioFlush();/* GSG 11/22 */
10409 +    }
10410 +#endif
10411 +
10412 +  HalDev->IntVec = IntVec;
10413 +  if (IntVec & MAC_IN_VECTOR_TX_INT_OR)
10414 +   {
10415 +     int TxServiceMax=0;  /* Compiler complains if not initialized */
10416 +
10417 +     Channel = (IntVec & 0x7);
10418 +
10419 +     if(HalDev->TxIntDisable)
10420 +       {
10421 +         CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Channel);  /* Disable Interrupt for Channel */
10422 +         TxServiceMax = HalDev->ChData[Channel].TxServiceMax;
10423 +         HalDev->ChData[Channel].TxServiceMax = 10000;             /* Need to service all packets in the Queue */
10424 +       }
10425 +
10426 +     PacketsServiced |= TxInt(HalDev, Channel, 0, &TxMorePackets);
10427 +
10428 +     if(HalDev->TxIntDisable)
10429 +          HalDev->ChData[Channel].TxServiceMax  = TxServiceMax;
10430 +    }
10431 +
10432 +  if (IntVec & MAC_IN_VECTOR_RX_INT_OR)
10433 +    {
10434 +     Channel = (IntVec >> 8) & 0x7;
10435 +     Serviced = RxInt(HalDev, Channel, &RxMorePackets);
10436 +     PacketsServiced |= (Serviced<<16);
10437 +    }
10438 +
10439 +  if (IntVec & MAC_IN_VECTOR_HOST_INT)
10440 +    {
10441 +    /* Adaptercheck */
10442 +    HalDev->HostErr = 1;
10443 +    HalDev->MacStatus = CPMAC_MACSTATUS(HalDev->dev_base);
10444 +    osfuncStateChange();                                          /*MJH+030328*/
10445 +    if(DBG(0))
10446 +      {
10447 +      dbgPrintf("Adaptercheck: %08x for base:%X\n",HalDev->MacStatus, (bit32u)HalDev->dev_base);
10448 +      osfuncSioFlush();
10449 +      }
10450 +    }
10451 +  *MorePackets = (TxMorePackets | RxMorePackets);
10452 +  return (PacketsServiced);
10453 +}
10454 +
10455 +int halPacketProcessEnd(HAL_DEVICE *HalDev)
10456 +{
10457 +  int base             = HalDev->dev_base;
10458 +  CPMAC_MAC_EOI_VECTOR(base) = 0;
10459 +  return(0);
10460 +}
10461 +
10462 +
10463 +
10464 +static int PhyCheck(HAL_DEVICE *HalDev)
10465 +  {
10466 +      return(cpMacMdioTic(HalDev->PhyDev));
10467 +  }
10468 +static int halTick(HAL_DEVICE *HalDev)
10469 +{
10470 +    int TickChange;
10471 +
10472 +    if(HalDev->State <  enOpened)
10473 +      return (EC_CPMAC|EC_FUNC_TICK|EC_VAL_INVALID_STATE);
10474 +
10475 +    /* if NO Phy no need to check Link */
10476 +    if(HalDev->MdioConnect & _CPMDIO_NOPHY)
10477 +      return(EC_NO_ERRORS);  /* No change in Phy State detected */
10478 +
10479 +    TickChange = PhyCheck(HalDev);
10480 +    /* Phy State Change Detected */
10481 +    if(TickChange == 1)
10482 +    {
10483 +        /*  MDIO indicated a change  */
10484 +        DuplexUpdate(HalDev);
10485 +        osfuncStateChange();
10486 +        return(EC_NO_ERRORS);
10487 +    }
10488 +
10489 +    /* if in AutoMdix mode, and Flip request received, inform OS */
10490 +    if( (HalDev->MdioConnect & _CPMDIO_AUTOMDIX)  &&
10491 +        (TickChange & _MIIMDIO_MDIXFLIP))
10492 +    {
10493 +       bit32u Mdix;
10494 +       Mdix = TickChange & 0x1;   /*  Mdix mode stored in bit 0 */
10495 +       HalDev->OsFunc->Control(HalDev->OsDev, hcMdioMdixSwitch, hcSet, &Mdix);
10496 +       return(EC_NO_ERRORS);
10497 +    }
10498 +
10499 +    return(EC_NO_ERRORS);
10500 +}
10501 +
10502 +int halCpmacInitModule(HAL_DEVICE **pHalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS **pHalFunc,
10503 +                       OS_FUNCTIONS *OsFunc, int OsFuncSize,     int *HalFuncSize, int Inst)
10504 +  {
10505 +    HAL_DEVICE *HalDev;
10506 +    HAL_FUNCTIONS *HalFunc;
10507 +
10508 +    if (OsFuncSize < sizeof(OS_FUNCTIONS))
10509 +      return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_OS_VERSION_NOT_SUPPORTED);
10510 +
10511 +    HalDev = (HAL_DEVICE *) OsFunc->MallocDev(sizeof(HAL_DEVICE));
10512 +    if (!HalDev)
10513 +      return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
10514 +
10515 +    /* clear the HalDev area */
10516 +    OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
10517 +
10518 +    /* Initialize the size of hal functions */
10519 +    *HalFuncSize = sizeof (HAL_FUNCTIONS);
10520 +
10521 +    HalFunc = (HAL_FUNCTIONS *) OsFunc->Malloc(sizeof(HAL_FUNCTIONS));
10522 +    if (!HalFunc)
10523 +      return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
10524 +
10525 +    /* clear the function pointers */
10526 +    OsFunc->Memset(HalFunc, 0, sizeof(HAL_FUNCTIONS));
10527 +
10528 +    HalDev->OsDev   = OsDev;
10529 +    HalDev->OsOpen  = OsDev;
10530 +    HalDev->inst    = Inst;
10531 +    HalDev->OsFunc  = OsFunc;
10532 +    HalDev->HalFunc = HalFunc;
10533 +    /* Remove the following from cppi, replace with HalFunc */
10534 +    HalDev->HalFuncPtr = HalFunc; /* GSG 11/20 changed name to match cppi */
10535 +
10536 +    /****************************************************************/
10537 +    /*                 POPULATE HALFUNC                             */
10538 +    /****************************************************************/
10539 +    HalFunc->ChannelSetup     = halChannelSetup;
10540 +    HalFunc->ChannelTeardown  = halChannelTeardown; /* GSG 11/20 */
10541 +    HalFunc->Close            = halClose; /* GSG 11/20 */
10542 +    HalFunc->Control          = halControl; /* GSG 11/22 */
10543 +    HalFunc->Init             = halInit;
10544 +    HalFunc->Open             = halOpen;
10545 +    HalFunc->PacketProcessEnd = halPacketProcessEnd;
10546 +    HalFunc->Probe            = halProbe;
10547 +    HalFunc->RxReturn         = halRxReturn;
10548 +    HalFunc->Send             = halSend;
10549 +    HalFunc->Shutdown         = halShutdown;
10550 +    HalFunc->Tick             = halTick;
10551 +
10552 +    /* HalFunc->Status        = halStatus;*/ /* GSG 11/22 */
10553 +    /* pass the HalDev and HalFunc back to the caller */
10554 +
10555 +    *pHalDev  = HalDev;
10556 +    *pHalFunc = HalFunc;
10557 +
10558 +    HalDev->State = enConnected;   /* Initialize the hardware state */
10559 +
10560 +    if (HalDev->debug) HalDev->OsFunc->Printf("halCpmacInitModule: Leave\n");
10561 +    return(0);
10562 +  }
10563 +
10564 +int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max)
10565 +{
10566 +    int iTmp;
10567 +    iTmp  = cpmacRandom(HalDev);
10568 +    iTmp %= ((max-min)+1);
10569 +    iTmp += min;
10570 +    return(iTmp);
10571 +}
10572 +
10573 +int cpmacRandom(HAL_DEVICE *HalDev)
10574 +{
10575 +    int iTmp;
10576 +    iTmp = CPMAC_BOFFTEST(HalDev->dev_base);
10577 +    iTmp >>= 16;      /*  get rndnum field */
10578 +    iTmp &= (0x3FF); /* field is 10 bits wide */
10579 +    return(iTmp);
10580 +}
10581 diff -urN linux.old/drivers/net/avalanche_cpmac/hcpmac.h linux.dev/drivers/net/avalanche_cpmac/hcpmac.h
10582 --- linux.old/drivers/net/avalanche_cpmac/hcpmac.h      1970-01-01 01:00:00.000000000 +0100
10583 +++ linux.dev/drivers/net/avalanche_cpmac/hcpmac.h      2005-07-12 02:48:42.175574000 +0200
10584 @@ -0,0 +1,383 @@
10585 +/** @file***********************************************************************
10586 + *  TNETDxxxx Software Support
10587 + *  Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
10588 + *
10589 + *  FILE:
10590 + *
10591 + *  DESCRIPTION:
10592 + *      This file contains definitions for the HAL EMAC API
10593 + *
10594 + *  HISTORY:
10595 + *  xxXxx01 Denis      1.00  Original Version created.
10596 + *  22Jan02 Denis/Mick 1.01  Modified for HAL EMAC API
10597 + *  24Jan02 Denis/Mick 1.02  Speed Improvements
10598 + *  28Jan02 Denis/Mick 1.16  Made function calls pointers
10599 + *  28Jan02 Mick       1.18  Split into separate modules
10600 + *  @author Michael Hanrahan
10601 + *  @version 1.02
10602 + *  @date    24-Jan-2002
10603 + *****************************************************************************/
10604 +#ifndef _INC_HCPMAC
10605 +#define _INC_HCPMAC
10606 +
10607 +/** \namespace CPMAC_Version
10608 +This documents version 01.07.04 of the CPMAC CPHAL.
10609 +*/
10610 +const char *pszVersion_CPMAC="CPMAC 01.07.08 "__DATE__" "__TIME__;
10611 +
10612 +/* CHECK THESE LOCATIONS */
10613 +#define TEARDOWN_VAL       0xfffffffc
10614 +#define CB_OFFSET_MASK     0xFFFF0000
10615 +
10616 +
10617 +#define MAX_CHAN 8
10618 +#define MAX_QUEUE 1
10619 +
10620 +typedef struct
10621 +  {
10622 +  bit32 HNext;      /*< Hardware's pointer to next buffer descriptor  */
10623 +  bit32 BufPtr;     /*< Pointer to the data buffer                    */
10624 +  bit32 Off_BLen;   /*< Contains buffer offset and buffer length      */
10625 +  bit32 mode;       /*< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
10626 +  void *Next;
10627 +  void *OsInfo;
10628 +  void *Eop;
10629 +#ifdef __CPHAL_DEBUG
10630 +  bit32 DbgSop;
10631 +  bit32 DbgData;
10632 +  bit32 DbgFraglist;
10633 +#endif
10634 +  }HAL_TCB;
10635 +
10636 +typedef volatile struct hal_private
10637 +  {
10638 +  bit32 HNext;      /*< Hardware's pointer to next buffer descriptor     */
10639 +  bit32 BufPtr;     /*< Pointer to the data buffer                       */
10640 +  bit32 Off_BLen;   /*< Contains buffer offset and buffer length         */
10641 +  bit32 mode;       /*< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
10642 +  void *DatPtr;
10643 +  void *Next;
10644 +  void *OsInfo;
10645 +  void *Eop;
10646 +  }HAL_RCB;
10647 +
10648 +#define MAX_NEEDS 512                                             /*MJH+030409*/
10649 +/*  HAL  */
10650 +
10651 +typedef struct hal_device
10652 +  {
10653 +  OS_DEVICE *OsDev;
10654 +  OS_FUNCTIONS *OsFunc;
10655 +    /*OS_SETUP *OsSetup;*/                                     /* -GSG 030508 */
10656 +  int inst;
10657 +  bit32u rxbufseq;
10658 +
10659 +
10660 +  bit32 dev_base;
10661 +  bit32  offset;
10662 +
10663 +  bit32u ResetBase; /* GSG 10/20 */
10664 +  int ResetBit;
10665 +  void *OsOpen;
10666 +  bit32u IntVec;
10667 +  PHY_DEVICE *PhyDev;
10668 +  bit32u EmacDuplex;
10669 +  bit32u EmacSpeed;
10670 +  bit32u PhyNum;
10671 +  bit32u MLinkMask;
10672 +  bit32u PhyMask;
10673 +  bit32u MdixMask;
10674 +
10675 +  bit32u Linked;
10676 +  DEVICE_STATE State;
10677 +  unsigned char *MacAddr;
10678 +  HAL_FUNCTIONS *HalFuncPtr; /* GSG 11/20 changed name to match cppi */
10679 +  HAL_FUNCTIONS *HalFunc;
10680 +/*  unsigned int CpuFreq;*/                                       /*MJH-030402*/
10681 +  unsigned int MdioConnect;
10682 +  unsigned int HostErr;
10683 +
10684 +/************************************************************************/
10685 +/*                                                                      */
10686 +/*      R E G I S T E R S                                               */
10687 +/*                                                                      */
10688 +/************************************************************************/
10689 +
10690 +  bit32u RxMbpEnable;
10691 +  bit32u RxUnicastSet;
10692 +  bit32u RxUnicastClear;
10693 +  bit32u RxMaxLen;
10694 +  bit32u RxFilterLowThresh;
10695 +  bit32u Rx0FlowThresh;
10696 +  bit32u MacControl;
10697 +  bit32u MacStatus;
10698 +  bit32u MacHash1;
10699 +  bit32u MacHash2;
10700 +
10701 +/************************************************************************/
10702 +/*                                                                      */
10703 +/*      O P T I O N S                                                   */
10704 +/*                                                                      */
10705 +/************************************************************************/
10706 +
10707 +  char *DeviceInfo;
10708 +  bit32u interrupt;
10709 +
10710 +
10711 +  bit32u RxPassCrc;
10712 +  bit32u RxCaf;
10713 +  bit32u RxCef;
10714 +  bit32u RxBcast;
10715 +  bit32u RxBcastCh;
10716 +  HAL_RCB *RcbPool[MAX_CHAN];
10717 +  bit32 RxActQueueCount[MAX_CHAN];
10718 +  HAL_RCB *RxActQueueHead[MAX_CHAN];
10719 +  HAL_RCB *RxActQueueTail[MAX_CHAN];
10720 +  bit32 RxActive[MAX_CHAN];
10721 +  HAL_TCB *TcbPool[MAX_CHAN][MAX_QUEUE];
10722 +  bit32 TxActQueueCount[MAX_CHAN][MAX_QUEUE];
10723 +  HAL_TCB *TxActQueueHead[MAX_CHAN][MAX_QUEUE];
10724 +  HAL_TCB *TxActQueueTail[MAX_CHAN][MAX_QUEUE];
10725 +  bit32 TxActive[MAX_CHAN][MAX_QUEUE];
10726 +  bit32 TxTeardownPending[MAX_CHAN];
10727 +  bit32 RxTeardownPending[MAX_CHAN];
10728 +  bit32 ChIsOpen[MAX_CHAN][2];
10729 +  bit32 ChIsSetup[MAX_CHAN][2];
10730 +  FRAGLIST *fraglist;
10731 +  char *TcbStart[MAX_CHAN][MAX_QUEUE];
10732 +  char *RcbStart[MAX_CHAN];
10733 +  bit32 RcbSize[MAX_CHAN];
10734 +/*  STAT_INFO Stats;  */
10735 +  bit32  Inst;
10736 +  bit32u BuffersServicedMax;
10737 +  CHANNEL_INFO ChData[MAX_CHAN];
10738 +  bit32u MdioClockFrequency;                                      /*MJH+030402*/
10739 +  bit32u MdioBusFrequency;                                        /*MJH+030402*/
10740 +  bit32u CpuFrequency;                                            /*MJH+030402*/
10741 +  bit32u CpmacFrequency;                                          /*MJH+030403*/
10742 +  bit32u CpmacSize;                                               /*MJH+030425*/
10743 +  int debug;
10744 +  bit32u NeedsCount;                                              /*MJH+030409*/
10745 +  HAL_RECEIVEINFO *Needs[MAX_NEEDS];                              /*MJH+030409*/
10746 +  int MaxFrags;
10747 +  int TxIntThreshold[MAX_CHAN];                   /* MJH 040621  NSP Performance Update */
10748 +  int TxIntThresholdMaster[MAX_CHAN];             /* MJH 040827  NSP Performance Update */
10749 +  int TxIntDisable;                     /* MJH 040621  NSP Performance Update */
10750 +  }HALDEVICE;
10751 +
10752 +#define STATS_MAX 36
10753 +
10754 +#define MACCONTROL_MASK    (TX_PTYPE|TX_PACE|TX_FLOW_EN|RX_FLOW_EN|CTRL_LOOPBACK)
10755 +#define RX_MBP_ENABLE_MASK                                       \
10756 +        (RX_PASS_CRC|RX_QOS_EN|RX_NO_CHAIN|                      \
10757 +         RX_CMF_EN|RX_CSF_EN|RX_CEF_EN|RX_CAF_EN|RX_PROM_CH_MASK|     \
10758 +         RX_BROAD_EN|RX_BROAD_CH_MASK|RX_MULT_EN|RX_MULT_CH_MASK)
10759 +
10760 +
10761 +#define MBP_UPDATE(Mask, On)                      \
10762 +         if(On)   HalDev->RxMbpEnable |=  Mask;   \
10763 +         else     HalDev->RxMbpEnable &= ~Mask
10764 +
10765 +#define CONTROL_UPDATE(Mask, On)                  \
10766 +         if(On)   HalDev->MacControl |=  Mask;    \
10767 +         else     HalDev->MacControl &= ~Mask
10768 +
10769 +
10770 +#define UPDATE_TX_PTYPE(Value)       CONTROL_UPDATE(TX_PTYPE,Value)
10771 +#define UPDATE_TX_PACE(Value)        CONTROL_UPDATE(TX_PACE,Value)
10772 +#define UPDATE_MII_EN(Value)         CONTROL_UPDATE(MII_EN,Value)
10773 +#define UPDATE_TX_FLOW_EN(Value)     CONTROL_UPDATE(TX_FLOW_EN,Value)
10774 +#define UPDATE_RX_FLOW_EN(Value)     CONTROL_UPDATE(RX_FLOW_EN,Value)
10775 +#define UPDATE_CTRL_LOOPBACK(Value)  CONTROL_UPDATE(CTRL_LOOPBACK,Value)
10776 +#define UPDATE_FULLDUPLEX(Value)     CONTROL_UPDATE(FULLDUPLEX,(Value))
10777 +
10778 +#define UPDATE_RX_PASS_CRC(Value)    MBP_UPDATE(RX_PASS_CRC,  Value)
10779 +#define UPDATE_RX_QOS_EN(Value)      MBP_UPDATE(RX_QOS_EN,    Value)
10780 +#define UPDATE_RX_NO_CHAIN(Value)    MBP_UPDATE(RX_NO_CHAIN,  Value)
10781 +#define UPDATE_RX_CMF_EN(Value)      MBP_UPDATE(RX_CMF_EN,    Value)
10782 +#define UPDATE_RX_CSF_EN(Value)      MBP_UPDATE(RX_CSF_EN,    Value)
10783 +#define UPDATE_RX_CEF_EN(Value)      MBP_UPDATE(RX_CEF_EN,    Value)
10784 +#define UPDATE_RX_CAF_EN(Value)      MBP_UPDATE(RX_CAF_EN,    Value)
10785 +#define UPDATE_RX_BROAD_EN(Value)    MBP_UPDATE(RX_BROAD_EN,  Value)
10786 +#define UPDATE_RX_MULT_EN(Value)     MBP_UPDATE(RX_MULT_EN,   Value)
10787 +
10788 +#define UPDATE_RX_PROM_CH(Value)                         \
10789 +        HalDev->RxMbpEnable &=  ~RX_PROM_CH_MASK;        \
10790 +        HalDev->RxMbpEnable |=   RX_PROM_CH(Value)
10791 +
10792 +#define UPDATE_RX_BROAD_CH(Value)                        \
10793 +           HalDev->RxMbpEnable &=  ~RX_BROAD_CH_MASK;    \
10794 +           HalDev->RxMbpEnable |=   RX_BROAD_CH(Value)
10795 +
10796 +#define UPDATE_RX_MULT_CH(Value)                         \
10797 +           HalDev->RxMbpEnable &=  ~RX_MULT_CH_MASK;     \
10798 +           HalDev->RxMbpEnable |=   RX_MULT_CH(Value)
10799 +
10800 +
10801 +
10802 +typedef enum
10803 +  {
10804 +   /*  CPMAC */
10805 +    enCpmacStart=0,
10806 +    enStats0,
10807 +    enStats1,
10808 +    enStats2,
10809 +    enStats3,
10810 +    enStats4,
10811 +    enStatsDump,
10812 +    enStatsClear,
10813 +    enRX_PASS_CRC,
10814 +    enRX_QOS_EN,
10815 +    enRX_NO_CHAIN,
10816 +    enRX_CMF_EN,
10817 +    enRX_CSF_EN,
10818 +    enRX_CEF_EN,
10819 +    enRX_CAF_EN,
10820 +    enRX_PROM_CH,
10821 +    enRX_BROAD_EN,
10822 +    enRX_BROAD_CH,
10823 +    enRX_MULT_EN,
10824 +    enRX_MULT_CH,
10825 +
10826 +    enTX_PTYPE,
10827 +    enTX_PACE,
10828 +    enMII_EN,
10829 +    enTX_FLOW_EN,
10830 +    enRX_FLOW_EN,
10831 +    enCTRL_LOOPBACK,
10832 +
10833 +    enRX_MAXLEN,
10834 +    enRX_FILTERLOWTHRESH,
10835 +    enRX0_FLOWTHRESH,
10836 +    enRX_UNICAST_SET,
10837 +    enRX_UNICAST_CLEAR,
10838 +    enMdioConnect,
10839 +    enMAC_ADDR_GET,
10840 +    enTick,
10841 +    enRX_MULTICAST,
10842 +    enRX_MULTI_ALL,
10843 +    enRX_MULTI_SINGLE,
10844 +    enVersion,
10845 +    enCpmacEnd                                   /* Last entry */
10846 +  }INFO_KEY_CPMAC;
10847 +
10848 +static const char pszVersion[]                 = "Version";
10849 +static const char pszStats0[]                  = "Stats0";
10850 +static const char pszStats1[]                  = "Stats1";
10851 +static const char pszStats2[]                  = "Stats2";
10852 +static const char pszStats3[]                  = "Stats3";
10853 +static const char pszStats4[]                  = "Stats4";
10854 +static const char pszStatsDump[]               = "StatsDump";
10855 +static const char pszStatsClear[]              = "StatsClear";
10856 +
10857 +/********************************************************************
10858 +**
10859 +**  RX MBP ENABLE
10860 +**
10861 +********************************************************************/
10862 +static const char pszRX_PASS_CRC[]             = "RX_PASS_CRC";
10863 +static const char pszRX_QOS_EN[]               = "RX_QOS_EN";
10864 +static const char pszRX_NO_CHAIN[]             = "RX_NO_CHAIN";
10865 +static const char pszRX_CMF_EN[]               = "RX_CMF_EN";
10866 +static const char pszRX_CSF_EN[]               = "RX_CSF_EN";
10867 +static const char pszRX_CEF_EN[]               = "RX_CEF_EN";
10868 +static const char pszRX_CAF_EN[]               = "RX_CAF_EN";
10869 +static const char pszRX_PROM_CH[]              = "RX_PROM_CH";
10870 +static const char pszRX_BROAD_EN[]             = "RX_BROAD_EN";
10871 +static const char pszRX_BROAD_CH[]             = "RX_BROAD_CH";
10872 +static const char pszRX_MULT_EN[]              = "RX_MULT_EN";
10873 +static const char pszRX_MULT_CH[]              = "RX_MULT_CH";
10874 +
10875 +
10876 +/********************************************************************
10877 +**
10878 +**  MAC CONTROL
10879 +**
10880 +********************************************************************/
10881 +static const char pszTX_PTYPE[]                = "TX_PTYPE";
10882 +static const char pszTX_PACE[]                 = "TX_PACE";
10883 +static const char pszMII_EN[]                  = "MII_EN";
10884 +static const char pszTX_FLOW_EN[]              = "TX_FLOW_EN";
10885 +static const char pszRX_FLOW_EN[]              = "RX_FLOW_EN";
10886 +static const char pszCTRL_LOOPBACK[]           = "CTRL_LOOPBACK";
10887 +
10888 +static const char pszRX_MAXLEN[]               = "RX_MAXLEN";
10889 +static const char pszRX_FILTERLOWTHRESH[]      = "RX_FILTERLOWTHRESH";
10890 +static const char pszRX0_FLOWTHRESH[]          = "RX0_FLOWTHRESH";
10891 +static const char pszRX_UNICAST_SET[]          = "RX_UNICAST_SET";
10892 +static const char pszRX_UNICAST_CLEAR[]        = "RX_UNICAST_CLEAR";
10893 +static const char pszMdioConnect[]             = "MdioConnect";
10894 +static const char pszMacAddr[]                 = "MacAddr";
10895 +static const char pszTick[]                    = "Tick";
10896 +
10897 +/********************************************************************
10898 +**
10899 +**  MULTICAST
10900 +**
10901 +********************************************************************/
10902 +
10903 +static const char pszRX_MULTICAST[]            = "RX_MULTICAST";
10904 +static const char pszRX_MULTI_ALL[]            = "RX_MULTI_ALL";
10905 +static const char pszRX_MULTI_SINGLE[]         = "RX_MULTI_SINGLE";
10906 +
10907 +/*
10908 +static const char* pszGFHN = "GFHN";
10909 +*/
10910 +
10911 +static const CONTROL_KEY KeyCpmac[] =
10912 +   {
10913 +     {""                           , enCpmacStart},
10914 +     {pszStats0                    , enStats0},
10915 +     {pszStats1                    , enStats1},
10916 +     {pszStats2                    , enStats2},
10917 +     {pszStats3                    , enStats3},
10918 +     {pszStats4                    , enStats4},
10919 +     {pszStatsClear                , enStatsClear},
10920 +     {pszStatsDump                 , enStatsDump},
10921 +     {pszRX_PASS_CRC               , enRX_PASS_CRC},
10922 +     {pszRX_QOS_EN                 , enRX_QOS_EN},
10923 +     {pszRX_NO_CHAIN               , enRX_NO_CHAIN},
10924 +     {pszRX_CMF_EN                 , enRX_CMF_EN},
10925 +     {pszRX_CSF_EN                 , enRX_CSF_EN},
10926 +     {pszRX_CEF_EN                 , enRX_CEF_EN},
10927 +     {pszRX_CAF_EN                 , enRX_CAF_EN},
10928 +     {pszRX_PROM_CH                , enRX_PROM_CH},
10929 +     {pszRX_BROAD_EN               , enRX_BROAD_EN},
10930 +     {pszRX_BROAD_CH               , enRX_BROAD_CH},
10931 +     {pszRX_MULT_EN                , enRX_MULT_EN},
10932 +     {pszRX_MULT_CH                , enRX_MULT_CH},
10933 +
10934 +     {pszTX_PTYPE                  , enTX_PTYPE},
10935 +     {pszTX_PACE                   , enTX_PACE},
10936 +     {pszMII_EN                    , enMII_EN},
10937 +     {pszTX_FLOW_EN                , enTX_FLOW_EN},
10938 +     {pszRX_FLOW_EN                , enRX_FLOW_EN},
10939 +     {pszCTRL_LOOPBACK             , enCTRL_LOOPBACK},
10940 +     {pszRX_MAXLEN                 , enRX_MAXLEN},
10941 +     {pszRX_FILTERLOWTHRESH        , enRX_FILTERLOWTHRESH},
10942 +     {pszRX0_FLOWTHRESH            , enRX0_FLOWTHRESH},
10943 +     {pszRX_UNICAST_SET            , enRX_UNICAST_SET},
10944 +     {pszRX_UNICAST_CLEAR          , enRX_UNICAST_CLEAR},
10945 +     {pszMdioConnect               , enMdioConnect},
10946 +     {pszRX_MULTICAST              , enRX_MULTICAST},
10947 +     {pszRX_MULTI_ALL              , enRX_MULTI_ALL},
10948 +     {pszRX_MULTI_SINGLE           , enRX_MULTI_SINGLE},
10949 +     {pszTick                      , enTick},
10950 +     {pszVersion                   , enVersion},
10951 +     {""                           , enCpmacEnd}
10952 +   };
10953 +
10954 +const char hcCpuFrequency[]       = "CpuFreq";
10955 +const char hcCpmacFrequency[]     = "CpmacFrequency";
10956 +const char hcMdioBusFrequency[]   = "MdioBusFrequency";
10957 +const char hcMdioClockFrequency[] = "MdioClockFrequency";
10958 +const char hcCpmacBase[]          = "CpmacBase";
10959 +const char hcPhyNum[]             = "PhyNum";
10960 +const char hcSize[]               = "size";
10961 +const char hcCpmacSize[]          = "CpmacSize";
10962 +const char hcPhyAccess[]          = "PhyAccess";
10963 +const char hcLinked[]             = "Linked";
10964 +const char hcFullDuplex[]         = "FullDuplex";
10965 +const char hcMdixMask[]           = "MdixMask";
10966 +const char hcMdioMdixSwitch[]     = "MdixSet";
10967 +#endif
10968 diff -urN linux.old/drivers/net/avalanche_cpmac/Makefile linux.dev/drivers/net/avalanche_cpmac/Makefile
10969 --- linux.old/drivers/net/avalanche_cpmac/Makefile      1970-01-01 01:00:00.000000000 +0100
10970 +++ linux.dev/drivers/net/avalanche_cpmac/Makefile      2005-07-12 02:48:42.175574000 +0200
10971 @@ -0,0 +1,26 @@
10972 +# File: drivers/net/avalanche_cpmac/Makefile
10973 +#
10974 +# Makefile for the Linux network (CPMAC) device drivers.
10975 +#
10976 +
10977 +O_TARGET := avalanche_cpmac.o
10978 +
10979 +
10980 +list-multi := avalanche_cpmac.o
10981 +obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) := avalanche_cpmac.o
10982 +
10983 +avalanche_cpmac-objs += cpmac.o            cpmacHalLx.o       hcpmac.o \
10984 +                                     psp_config_build.o psp_config_mgr.o            \
10985 +                                     psp_config_parse.o psp_config_util.o
10986 +
10987 +
10988 +include $(TOPDIR)/Rules.make
10989 +
10990 +
10991 +avalanche_cpmac.o:        $(avalanche_cpmac-objs)
10992 +       $(LD) -r -o $@ $(avalanche_cpmac-objs)
10993 +
10994 +
10995 +
10996 +clean:
10997 +       rm -f core *.o *.a *.s
10998 diff -urN linux.old/drivers/net/avalanche_cpmac/mdio_reg.h linux.dev/drivers/net/avalanche_cpmac/mdio_reg.h
10999 --- linux.old/drivers/net/avalanche_cpmac/mdio_reg.h    1970-01-01 01:00:00.000000000 +0100
11000 +++ linux.dev/drivers/net/avalanche_cpmac/mdio_reg.h    2005-07-12 02:48:42.176573000 +0200
11001 @@ -0,0 +1,121 @@
11002 +/****************************************************************************
11003 +**      TNETD53xx Software Support
11004 +**      Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
11005 +**
11006 +**      FILE: mdio_reg.h   Register definitions for the VBUS MII module
11007 +**
11008 +**      DESCRIPTION:
11009 +**              This include file contains register definitions for the
11010 +**              VBUS MII module.
11011 +**
11012 +**      HISTORY:
11013 +**              27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
11014 +**              01Apr02 Michael Hanrahan Modified to include all regs. in spec
11015 +**              03Apr02 Michael Hanrahan Updated to Version 0.6 of spec
11016 +**              05Apr02 Michael Hanrahan Moved Phy Mode values into here
11017 +**              30Apr02 Michael Hanrahan Updated to Version 0.8 of spec
11018 +**              30Apr02 Michael Hanrahan Updated to recommended format
11019 +**              10May02 Michael Hanrahan Updated to Version 0.9 of spec
11020 +*****************************************************************************/
11021 +#ifndef _INC_MDIO_REG
11022 +#define _INC_MDIO_REG
11023 +
11024 +/***************************************************************************
11025 +**
11026 +**         M D I O  M E M O R Y  M A P
11027 +**
11028 +***************************************************************************/
11029 +
11030 +
11031 +#define pMDIO_VER(base)                 ((volatile bit32u *)(base+0x00))
11032 +#define pMDIO_CONTROL(base)             ((volatile bit32u *)(base+0x04))
11033 +#define pMDIO_ALIVE(base)               ((volatile bit32u *)(base+0x08))
11034 +#define pMDIO_LINK(base)                ((volatile bit32u *)(base+0x0C))
11035 +#define pMDIO_LINKINTRAW(base)          ((volatile bit32u *)(base+0x10))
11036 +#define pMDIO_LINKINTMASKED(base)       ((volatile bit32u *)(base+0x14))
11037 +#define pMDIO_USERINTRAW(base)          ((volatile bit32u *)(base+0x20))
11038 +#define pMDIO_USERINTMASKED(base)       ((volatile bit32u *)(base+0x24))
11039 +#define pMDIO_USERINTMASKED_SET(base)   ((volatile bit32u *)(base+0x28))
11040 +#define pMDIO_USERINTMASKED_CLR(base)   ((volatile bit32u *)(base+0x2C))
11041 +#define pMDIO_USERACCESS(base, channel) ((volatile bit32u *)(base+(0x80+(channel*8))))
11042 +#define pMDIO_USERPHYSEL(base, channel) ((volatile bit32u *)(base+(0x84+(channel*8))))
11043 +
11044 +
11045 +/***************************************************************************
11046 +**
11047 +**         M D I O  R E G I S T E R  A C C E S S  M A C R O S
11048 +**
11049 +***************************************************************************/
11050 +
11051 +
11052 +#define MDIO_ALIVE(base)                    (*(pMDIO_ALIVE(base)))
11053 +#define MDIO_CONTROL(base)                  (*(pMDIO_CONTROL(base)))
11054 +#define         MDIO_CONTROL_IDLE                 (1 << 31)
11055 +#define         MDIO_CONTROL_ENABLE               (1 << 30)
11056 +#define         MDIO_CONTROL_PREAMBLE             (1 << 20)
11057 +#define         MDIO_CONTROL_FAULT                (1 << 19)
11058 +#define         MDIO_CONTROL_FAULT_DETECT_ENABLE  (1 << 18)
11059 +#define         MDIO_CONTROL_INT_TEST_ENABLE      (1 << 17)
11060 +#define         MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F << 8)
11061 +#define         MDIO_CONTROL_CLKDIV               (0xFF)
11062 +#define MDIO_LINK(base)                     (*(pMDIO_LINK(base)))
11063 +#define MDIO_LINKINTRAW(base)               (*(pMDIO_LINKINTRAW(base)))
11064 +#define MDIO_LINKINTMASKED(base)            (*(pMDIO_LINKINTMASKED(base)))
11065 +#define MDIO_USERINTRAW(base)               (*(pMDIO_USERINTRAW(base)))
11066 +#define MDIO_USERINTMASKED(base)            (*(pMDIO_USERINTMASKED(base)))
11067 +#define MDIO_USERINTMASKED_CLR(base)        (*(pMDIO_USERINTMASKED_CLR(base)))
11068 +#define MDIO_USERINTMASKED_SET(base)        (*(pMDIO_USERINTMASKED_SET(base)))
11069 +#define MDIO_USERINTRAW(base)               (*(pMDIO_USERINTRAW(base)))
11070 +#define MDIO_USERACCESS(base, channel)      (*(pMDIO_USERACCESS(base, channel)))
11071 +#define         MDIO_USERACCESS_GO     (1 << 31)
11072 +#define         MDIO_USERACCESS_WRITE  (1 << 30)
11073 +#define         MDIO_USERACCESS_READ   (0 << 30)
11074 +#define         MDIO_USERACCESS_ACK    (1 << 29)
11075 +#define         MDIO_USERACCESS_REGADR (0x1F << 21)
11076 +#define         MDIO_USERACCESS_PHYADR (0x1F << 16)
11077 +#define         MDIO_USERACCESS_DATA   (0xFFFF)
11078 +#define MDIO_USERPHYSEL(base, channel)      (*(pMDIO_USERPHYSEL(base, channel)))
11079 +#define         MDIO_USERPHYSEL_LINKSEL         (1 << 7)
11080 +#define         MDIO_USERPHYSEL_LINKINT_ENABLE  (1 << 6)
11081 +#define         MDIO_USERPHYSEL_PHYADR_MON      (0x1F)
11082 +#define MDIO_VER(base)                      (*(pMDIO_VER(base)))
11083 +#define         MDIO_VER_MODID         (0xFFFF << 16)
11084 +#define         MDIO_VER_REVMAJ        (0xFF   << 8)
11085 +#define         MDIO_VER_REVMIN        (0xFF)
11086 +
11087 +
11088 +
11089 +
11090 +/****************************************************************************/
11091 +/*                                                                          */
11092 +/*         P H Y   R E G I S T E R  D E F I N I T I O N S                   */
11093 +/*                                                                          */
11094 +/****************************************************************************/
11095 +
11096 +
11097 +#define PHY_CONTROL_REG       0
11098 +  #define PHY_RESET           (1<<15)
11099 +  #define PHY_LOOP            (1<<14)
11100 +  #define PHY_100             (1<<13)
11101 +  #define AUTO_NEGOTIATE_EN   (1<<12)
11102 +  #define PHY_PDOWN           (1<<11)
11103 +  #define PHY_ISOLATE         (1<<10)
11104 +  #define RENEGOTIATE         (1<<9)
11105 +  #define PHY_FD              (1<<8)
11106 +
11107 +#define PHY_STATUS_REG        1
11108 +  #define NWAY_COMPLETE       (1<<5)
11109 +  #define NWAY_CAPABLE        (1<<3)
11110 +  #define PHY_LINKED          (1<<2)
11111 +
11112 +#define NWAY_ADVERTIZE_REG    4
11113 +#define NWAY_REMADVERTISE_REG 5
11114 +  #define NWAY_FD100          (1<<8)
11115 +  #define NWAY_HD100          (1<<7)
11116 +  #define NWAY_FD10           (1<<6)
11117 +  #define NWAY_HD10           (1<<5)
11118 +  #define NWAY_SEL            (1<<0)
11119 +  #define NWAY_AUTO           (1<<0)
11120 +
11121 +
11122 +#endif _INC_MDIO_REG
11123 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_build.c linux.dev/drivers/net/avalanche_cpmac/psp_config_build.c
11124 --- linux.old/drivers/net/avalanche_cpmac/psp_config_build.c    1970-01-01 01:00:00.000000000 +0100
11125 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_build.c    2005-07-12 02:48:42.176573000 +0200
11126 @@ -0,0 +1,335 @@
11127 +/******************************************************************************
11128 + * FILE PURPOSE:    PSP Config Manager - Configuration Build Source
11129 + ******************************************************************************
11130 + * FILE NAME:       psp_config_build.c
11131 + *
11132 + * DESCRIPTION:     Configuration Build API Implementation
11133 + *
11134 + * REVISION HISTORY:
11135 + * 27 Nov 02 - PSP TII
11136 + *
11137 + * (C) Copyright 2002, Texas Instruments, Inc
11138 + *******************************************************************************/
11139 +
11140 +#ifdef INCLUDE_FFS
11141 +#include "ffs.h"
11142 +#endif /* INCLUDE_FFS */
11143 +
11144 +#include "psp_config_mgr.h"
11145 +#include "psp_config_build.h"
11146 +#include "psp_config_util.h"
11147 +
11148 +#define MAX_DEVICE_NAME_LEN     16
11149 +#define MAX_DEVICE_STR_LEN      512
11150 +
11151 +#ifndef NULL
11152 +#define NULL (char *)0
11153 +#endif
11154 +
11155 +#include <asm/ar7/sangam.h>
11156 +#include <linux/slab.h>
11157 +#include <linux/config.h>
11158 +
11159 +
11160 +#define os_malloc(size) kmalloc(size, GFP_KERNEL)
11161 +
11162 +int psp_run_enumerator(void)
11163 +{
11164 +    return(0);
11165 +}
11166 +
11167 +#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
11168 +
11169 +static int auto_detect_cpmac_phy(void)
11170 +{
11171 +
11172 +#define SELECT_INT_PHY_MAC 0
11173 +#define SELECT_EXT_PHY_MAC 1
11174 +
11175 +    volatile unsigned long *reset_cntl = AVALANCHE_RESET_CONTROL_BASE, *mdio_cntl  = ((int)AVALANCHE_MDIO_BASE + 0x4);
11176 +    unsigned int j= 0, detected_phy_map = 0, auto_select = SELECT_INT_PHY_MAC;
11177 +
11178 +    *reset_cntl |= (1 << AVALANCHE_MDIO_RESET_BIT) | (1 << AVALANCHE_LOW_CPMAC_RESET_BIT) | (1 << AVALANCHE_HIGH_CPMAC_RESET_BIT) | (1 << AVALANCHE_LOW_EPHY_RESET_BIT);
11179 +    *mdio_cntl   = (1 << 30) | ((CONFIG_AR7_SYS_FREQUENCY * 1000)/2200);
11180 +
11181 +    for(j=0;j < 300000; j++)
11182 +    {
11183 +        if(j%100000) continue;
11184 +
11185 +        detected_phy_map = *(mdio_cntl + 1);
11186 +        if(detected_phy_map)
11187 +        {
11188 +            detected_phy_map &= ~AVALANCHE_LOW_CPMAC_PHY_MASK;
11189 +
11190 +            if(detected_phy_map && !(detected_phy_map & (detected_phy_map - 1)))
11191 +            {
11192 +                auto_select = SELECT_EXT_PHY_MAC;
11193 +                break;
11194 +            }
11195 +        }
11196 +    }
11197 +
11198 +    return(auto_select);
11199 +
11200 +}
11201 +
11202 +#endif
11203 +
11204 +
11205 +#ifndef AVALANCHE_LOW_CPMAC_MDIX_MASK
11206 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
11207 +#endif
11208 +
11209 +void psp_load_default_static_cfg(void)
11210 +{
11211 +    char s2[100],  s3[100];
11212 +    char s4[2000], s6[2000];
11213 +    int threshold = 20;
11214 +    char *tx_threshold_ptr = prom_getenv("threshold");
11215 +
11216 +    if(tx_threshold_ptr)
11217 +      threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
11218 +
11219 +    /* Static configuration if options.conf not present */
11220 +    sprintf(s3,"cpmdio(id=mii, base=%u, reset_bit=%d)", AVALANCHE_MDIO_BASE, 22);
11221 +    sprintf(s2, "reset( id=[ResetRegister], base=%u)", AVALANCHE_RESET_CONTROL_BASE);
11222 +
11223 +    sprintf(s4, "cpmac(id=[cpmac], unit=0, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MdixMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_LOW_CPMAC_BASE, AVALANCHE_LOW_CPMAC_RESET_BIT, AVALANCHE_LOW_CPMAC_PHY_MASK, AVALANCHE_LOW_CPMAC_MDIX_MASK, AVALANCHE_LOW_CPMAC_INT,threshold,threshold,threshold);
11224 +
11225 +    sprintf(s6, "cpmac(id=[cpmac], unit=1, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_HIGH_CPMAC_BASE, AVALANCHE_HIGH_CPMAC_RESET_BIT, AVALANCHE_HIGH_CPMAC_PHY_MASK, AVALANCHE_HIGH_CPMAC_INT,threshold,threshold,threshold);
11226 +
11227 +    psp_config_add("reset", s2, psp_config_strlen(s2), en_compile);
11228 +
11229 +
11230 +#if defined (CONFIG_AVALANCHE_LOW_CPMAC)
11231 +
11232 +    psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11233 +    psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
11234 +
11235 +#endif
11236 +
11237 +
11238 +#if defined (CONFIG_AVALANCHE_HIGH_CPMAC)
11239 +
11240 +    psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11241 +    psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
11242 +
11243 +#endif
11244 +
11245 +#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
11246 +    {
11247 +        char *phy_sel_ptr = prom_getenv("mac_phy_sel");
11248 +        int   phy_sel = SELECT_EXT_PHY_MAC;
11249 +        char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
11250 +
11251 +        if(phy_sel_ptr && (0 == strcmp(phy_sel_ptr, "int")))
11252 +        {
11253 +            phy_sel = SELECT_INT_PHY_MAC;
11254 +        }
11255 +
11256 +        //if(phy_sel == auto_detect_cpmac_phy())
11257 +        if(!mac_port || (0 != strcmp(mac_port, "0")))
11258 +        {
11259 +            printk("Using the MAC with external PHY\n");
11260 +            psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11261 +            psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
11262 +        }
11263 +        else
11264 +        {
11265 +            printk("Using the MAC with internal PHY\n");
11266 +            psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11267 +            psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
11268 +        }
11269 +    }
11270 +
11271 +#endif
11272 +
11273 +}
11274 +
11275 +char* psp_conf_read_file(char *p_file_name)
11276 +{
11277 +#ifdef INCLUDE_FFS
11278 +
11279 +    char        *p_file_data = NULL;
11280 +    unsigned int file_size;
11281 +    FFS_FILE    *p_file = NULL;
11282 +
11283 +    if(p_file_name == NULL)
11284 +    {
11285 +        return (NULL);
11286 +    }
11287 +
11288 +    if(!(p_file = ffs_fopen(p_file_name, "r")))
11289 +    {
11290 +        return(NULL);
11291 +    }
11292 +
11293 +    file_size = p_file->_AvailableBytes;
11294 +
11295 +    p_file_data = os_malloc(file_size + 1);
11296 +
11297 +    if(ffs_fread(p_file_data, file_size, 1, p_file) == 0)
11298 +    {
11299 +        kfree(p_file_data);
11300 +        return(NULL);
11301 +    }
11302 +
11303 +    ffs_fclose(p_file);
11304 +
11305 +    p_file_data[file_size] = '\0';
11306 +
11307 +    return(p_file_data);
11308 +
11309 +#else /* NO FFS */
11310 +    return(NULL);
11311 +#endif /* INCLUDE_FFS */
11312 +}
11313 +
11314 +int psp_conf_get_line(char *p_in_data, char **next_line)
11315 +{
11316 +    char *p       = p_in_data;
11317 +
11318 +    while(*p && *p++ != '\n')
11319 +    {
11320 +
11321 +    }
11322 +
11323 +    *next_line = p;
11324 +
11325 +    return(p - 1 - p_in_data);
11326 +}
11327 +
11328 +
11329 +int psp_conf_is_data_line(char *line)
11330 +{
11331 +    int ret_val = 1;
11332 +
11333 +    if(*line == '\0' || *line == '\n' || *line == '#')
11334 +        ret_val = 0;
11335 +
11336 +    return(ret_val);
11337 +}
11338 +
11339 +int psp_conf_get_key_size(char *data)
11340 +{
11341 +    char *p = data;
11342 +
11343 +    while(*p && *p != '\n' && *p != '(' && *p != ' ')
11344 +        p++;
11345 +
11346 +    return(p - data);
11347 +}
11348 +
11349 +char* psp_conf_eat_white_spaces(char *p)
11350 +{
11351 +    while(*p && *p != '\n' && *p == ' ')
11352 +        p++;
11353 +
11354 +    return (p);
11355 +}
11356 +
11357 +int psp_build_from_opt_conf(void)
11358 +{
11359 +    char *data       = NULL;
11360 +    char *data_hold  = NULL;
11361 +    char *next_line  = NULL;
11362 +    int  line_size   = 0;
11363 +
11364 +    if((data = psp_conf_read_file("/etc/options.conf")) == NULL)
11365 +        return(-1);
11366 +
11367 +    data_hold = data;
11368 +
11369 +    while((line_size=psp_conf_get_line(data, &next_line)) != -1)
11370 +    {
11371 +
11372 +        char *name = NULL;
11373 +        int  name_size;
11374 +
11375 +    data = psp_conf_eat_white_spaces(data);
11376 +
11377 +        if(psp_conf_is_data_line(data))
11378 +        {
11379 +            data[line_size] = '\0';
11380 +
11381 +            name_size = psp_conf_get_key_size(data);
11382 +
11383 +            if(name_size > 0)
11384 +            {
11385 +                name = (char *) os_malloc(name_size + 1);
11386 +                if(name == NULL) break;
11387 +
11388 +                psp_config_memcpy(name, data, name_size);
11389 +                name[name_size] = '\0';
11390 +
11391 +                psp_config_add(name, data, line_size, en_opt_conf);
11392 +
11393 +                kfree(name);
11394 +            }
11395 +
11396 +            data[line_size] = '\n';
11397 +        }
11398 +
11399 +        data = next_line;
11400 +    }
11401 +
11402 +    kfree(data_hold);
11403 +    return (0);
11404 +}
11405 +
11406 +
11407 +int psp_write_conf_file(char *p_write_file, char * dev_cfg_string)
11408 +{
11409 +#ifdef INCLUDE_FFS
11410 +    int bytes_written=0;
11411 +        FFS_FILE *file_ptr=NULL;
11412 +
11413 +    /*
11414 +     * NOTE: In current implementation of FFS in ADAM2 if the file exists beforehand, it
11415 +     * can't be opened for write.
11416 +     */
11417 +        if(!(file_ptr=ffs_fopen(p_write_file, "w"))) {
11418 +        return(-1);
11419 +        }
11420 +
11421 +    /* Write into the file "output.con" the character string */
11422 +    /* write a \n before a writing a line */
11423 +    if(!(bytes_written = ffs_fwrite("\n", 1, sizeof(char), file_ptr))) {
11424 +        return (-1);
11425 +    }
11426 +
11427 +    if(!(bytes_written = ffs_fwrite(dev_cfg_string, psp_config_strlen(dev_cfg_string), sizeof(char), file_ptr))) {
11428 +        return (-1);
11429 +    }
11430 +    ffs_fclose(file_ptr);
11431 +    return (bytes_written+1);
11432 +#else /* NO FFS */
11433 +    return(-1);
11434 +#endif /* INCLUDE_FFS */
11435 +}
11436 +
11437 +void build_psp_config(void)
11438 +{
11439 +
11440 +    /* initialize the repository. */
11441 +    psp_config_init();
11442 +
11443 +#ifdef INCLUDE_FFS
11444 +    ffs_init();
11445 +#endif /* INCLUDE_FFS */
11446 +
11447 +    /* read the configuration from the options.conf to override default ones */
11448 +    psp_build_from_opt_conf();
11449 +
11450 +    /* read the configuration which were not over ridden in options.conf */
11451 +    psp_load_default_static_cfg();
11452 +
11453 +    /* let the vlynq be enumerated. Enumerator will add cfg info
11454 +       of the discovered device instances to the repository.*/
11455 +    psp_run_enumerator();
11456 +
11457 +    /* dump the repository*/
11458 +    dump_device_cfg_pool();
11459 +
11460 +}
11461 +
11462 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_build.h linux.dev/drivers/net/avalanche_cpmac/psp_config_build.h
11463 --- linux.old/drivers/net/avalanche_cpmac/psp_config_build.h    1970-01-01 01:00:00.000000000 +0100
11464 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_build.h    2005-07-12 02:48:42.176573000 +0200
11465 @@ -0,0 +1,138 @@
11466 +/******************************************************************************
11467 + * FILE PURPOSE:    PSP Config Manager - Configuration Build Header
11468 + ******************************************************************************
11469 + * FILE NAME:       psp_config_build.h
11470 + *
11471 + * DESCRIPTION:     Configuration Build API's.
11472 + *
11473 + * REVISION HISTORY:
11474 + * 27 Nov 02 - PSP TII
11475 + *
11476 + * (C) Copyright 2002, Texas Instruments, Inc
11477 + *******************************************************************************/
11478 +
11479 +#ifndef __PSP_CONF_BUILD_H__
11480 +#define __PSP_CONF_BUILD_H__
11481 +
11482 +/*------------------------------------------------------------------------------
11483 + * Name: psp_conf_read_file
11484 + *
11485 + * Parameters:
11486 + *         in: p_file_name - the name of the file to read from.
11487 + *
11488 + * Description:
11489 + *     Reads the entire file in one shot. This function opens  the
11490 + *     file, determines the size of the data to be read, allocates
11491 + *     the required memory, NULL terminates the data and closes the
11492 + *     file.
11493 + *
11494 + *     It is responsibily of the callee to free the memory after it is
11495 + *     done with that data.
11496 + *
11497 + *
11498 + * Returns:
11499 + *     A NULL pointer, if failed to read the data otherwise, a valid
11500 + *     pointer referring to the data read from the file.
11501 + *
11502 + * Example:
11503 + *
11504 + *     psp_conf_read_file("/etc/options.conf");
11505 + *---------------------------------------------------------------------------*/
11506 + char *psp_conf_read_file(char *p_file_name);
11507 +
11508 + /*----------------------------------------------------------------------------
11509 +  * Function : psp_conf_write_file
11510 +  *
11511 +  * Parameters:
11512 +  *         in: p_file_name - the file to which data is to be written.
11513 +  *         in: data        - the NULL terminated data string.
11514 +  *
11515 +  * Description:
11516 +  *     Write the indicated data into the file. This function opens the file,
11517 +  *     appends the data to end of the file, closes the file.
11518 +  *
11519 +  * Returns:
11520 +  *
11521 +  *     The number of bytes on success.
11522 +  *     0 on failure.
11523 +  *
11524 +  * Example:
11525 +  *
11526 +  *     psp_conf_write_file("/etc/outcon.conf", data);
11527 +  *--------------------------------------------------------------------------*/
11528 + int   psp_conf_write_file(char *p_file_name, char *data);
11529 +
11530 + /*----------------------------------------------------------------------------
11531 +  * Function: psp_conf_get_line
11532 +  *
11533 +  * Parameters:
11534 +  *         in: data      - the data from which the line is to identified.
11535 +  *        out: next_line - the pointer to start of the next line.
11536 +  *
11537 +  * Description:
11538 +  *     Expects the data to be '\n' separated segments and data is NULL
11539 +  *     terminated. Parses the given data for '\n' or '\0'. Provides a pointer
11540 +  *     to the start of next line in the next_line.
11541 +  *
11542 +  * Returns:
11543 +  *     -1 on error.
11544 +  *      0 or more to indicate the number of bytes in the line starting at
11545 +  *      data.
11546 +  *--------------------------------------------------------------------------*/
11547 + int psp_get_conf_line(char *p_in_data, char **next_line);
11548 +
11549 + /*----------------------------------------------------------------------------
11550 +  * Function: psp_conf_is_data_line
11551 +  *
11552 +  * Parameters:
11553 +  *         in: line - the array of bytes.
11554 +  *
11555 +  * Description:
11556 +  *     Tests the first byte in the array for '\0' or '\n' or '#'. Lines
11557 +  *     starting with these characters are not considered data.
11558 +  *
11559 +  * Returns:
11560 +  *     1 if the line has data.
11561 +  *     0 otherwise.
11562 +  *
11563 +  *--------------------------------------------------------------------------*/
11564 + int psp_conf_is_data_line(char *line);
11565 +
11566 + /*----------------------------------------------------------------------------
11567 +  * Function: psp_conf_eat_white_spaces
11568 +  *
11569 +  * Parameters:
11570 +  *         in: line - the array of bytes.
11571 +  *
11572 +  * Description:
11573 +  *     Eats white spaces at the begining of the line while looking out for
11574 +  *     '\0' or '\n' or ' '.
11575 +  *
11576 +  * Returns:
11577 +  *     Pointer to the begining of the non white space character.
11578 +  *     NULL if '\0' or '\n' is found.
11579 +  *
11580 +  *--------------------------------------------------------------------------*/
11581 +  char *psp_conf_eat_white_spaces(char *line);
11582 +
11583 +  /*---------------------------------------------------------------------------
11584 +   * Function: psp_conf_get_key_size
11585 +   *
11586 +   * Parameters:
11587 +   *         in: line - the array of bytes.
11588 +   *
11589 +   * Description:
11590 +   *     Identifies the size of the 'key' in array formatted as
11591 +   *     key(id=[key1]....). This function also checks out for '\0' and '\n'.
11592 +   *
11593 +   * Returns:
11594 +   *     On success, The number of bytes that forms the key.
11595 +   *     0 otherwise.
11596 +   *
11597 +   *-------------------------------------------------------------------------*/
11598 +  int psp_conf_get_key_size(char *line);
11599 +
11600 +
11601 +
11602 +#endif /* __PSP_CONF_BUILD_H__ */
11603 +
11604 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.c linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.c
11605 --- linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.c      1970-01-01 01:00:00.000000000 +0100
11606 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.c      2005-07-12 02:48:42.177573000 +0200
11607 @@ -0,0 +1,464 @@
11608 +/******************************************************************************
11609 + * FILE PURPOSE:    PSP Config Manager Source
11610 + ******************************************************************************
11611 + * FILE NAME:       psp_config_mgr.c
11612 + *
11613 + * DESCRIPTION:
11614 + *
11615 + * Manages configuration information. The repository is managed on the basis of
11616 + * <key, info> pair. It is possible to have multiple occurrence of the same key.
11617 + * Multiple occurences of the same keys are referred to as 'instances'.
11618 + * 'instances' are assigned in the order of configuration arrival. The first
11619 + * config for a 'key' added to the repository would be treated as instance 0 and
11620 + * next config to arrive for the same key would be treated as instance '1' and
11621 + * so on.
11622 + *
11623 + * Info is retrieved from the repository based on the 'key' and 'instance' value.
11624 + *
11625 + * No assumption is made about the format of the information that is put in the
11626 + * repository. The only requirement is that 'key' should be NULL terminated
11627 + * string.
11628 + *
11629 + * REVISION HISTORY:
11630 + * 27 Nov 02 - PSP TII
11631 + *
11632 + * (C) Copyright 2002, Texas Instruments, Inc
11633 + *******************************************************************************/
11634 +
11635 +//#include <stdio.h>
11636 +//#include <stdlib.h>
11637 +#include "psp_config_mgr.h"
11638 +#include "psp_config_util.h"
11639 +
11640 +#include <linux/slab.h>
11641 +
11642 +/*-----------------------------------------------------------
11643 +  Implemented elsewhere
11644 + -----------------------------------------------------------*/
11645 +extern int sys_read_options_conf(void);
11646 +extern int sys_write_options_conf(char *cfg_info);
11647 +extern int sys_load_default_static_cfg(void);
11648 +extern int sys_run_enumerator(void);
11649 +
11650 +#define os_malloc(size) kmalloc(size, GFP_KERNEL)
11651 +
11652 +/*---------------------------------------------------------
11653 + * Data structures.
11654 + *--------------------------------------------------------*/
11655 +struct device_cfg_data;
11656 +
11657 +typedef struct device_instance_cfg_data
11658 +{
11659 +    struct device_instance_cfg_data       *next;
11660 +    char                                  locale[100];
11661 +    unsigned int                          data_size;
11662 +    char                                  *data;
11663 +
11664 +} DEV_INSTANCE_CFG_DATA_T;
11665 +
11666 +struct device_cfg_collection;
11667 +
11668 +typedef struct device_cfg_collection
11669 +{
11670 +    struct device_cfg_collection *next;
11671 +    char                         *device_name;
11672 +    CFG_TYPE_T                   cfg_type;
11673 +    int                          count;
11674 +    DEV_INSTANCE_CFG_DATA_T      *dev_inst_list_begin;
11675 +    DEV_INSTANCE_CFG_DATA_T      *dev_inst_list_end;
11676 +} DEVICE_CFG_T;
11677 +
11678 +
11679 +typedef struct device_cfg_list
11680 +{
11681 +    DEVICE_CFG_T   *device_cfg_begin;
11682 +    int            count;
11683 +} DEVICE_CFG_LIST_T;
11684 +
11685 +/*-----------------------------------------------------------------------------
11686 + * Functions used locally with in the file.
11687 + *---------------------------------------------------------------------------*/
11688 +static void p_init_device_cfg_list(void);
11689 +static int  p_add_instance_cfg_data(DEVICE_CFG_T            *p_dev_cfg,
11690 +                                    DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data);
11691 +static DEVICE_CFG_T* p_create_dev_cfg(char *device_name);
11692 +static DEVICE_CFG_T* p_get_dev_cfg(char *device_name);
11693 +static int p_set_device_cfg_type(DEVICE_CFG_T     *p_dev_cfg,
11694 +                                 CFG_TYPE_T       cfg_type);
11695 +
11696 +/* PSP Config manager debug */
11697 +#define PSP_CFG_MGR_DEBUG 0
11698 +
11699 +#define dbgPrint if (PSP_CFG_MGR_DEBUG) printk
11700 +
11701 +/*-----------------------------------------------------------------------------
11702 + * The repository.
11703 + *---------------------------------------------------------------------------*/
11704 +static DEVICE_CFG_LIST_T g_device_cfg_list;
11705 +
11706 +/*---------------------------------------------
11707 + * Initialize the device collection pool.
11708 + *--------------------------------------------*/
11709 +void p_init_device_cfg_list(void)
11710 +{
11711 +    g_device_cfg_list.count = 0;
11712 +    g_device_cfg_list.device_cfg_begin = NULL;
11713 +}
11714 +
11715 +/*----------------------------------------------------------------------
11716 + * Add the device cfg into the device linked list.
11717 + *---------------------------------------------------------------------*/
11718 +int p_add_dev_cfg_to_list(DEVICE_CFG_LIST_T *p_dev_list,
11719 +                          DEVICE_CFG_T      *p_dev_cfg)
11720 +{
11721 +    if(p_dev_list->count != 0)
11722 +        p_dev_cfg->next            = p_dev_list->device_cfg_begin;
11723 +
11724 +    p_dev_list->device_cfg_begin   = p_dev_cfg;
11725 +
11726 +    p_dev_list->count++;
11727 +
11728 +    return (0);
11729 +}
11730 +
11731 +/*------------------------------------------------------------------
11732 + * Add the cfg data into the cfg data linked list of the collection.
11733 + *------------------------------------------------------------------*/
11734 +int p_add_instance_cfg_data(DEVICE_CFG_T                 *p_dev_cfg,
11735 +                            DEV_INSTANCE_CFG_DATA_T      *p_dev_inst_data)
11736 +{
11737 +    if(p_dev_cfg->count == 0)
11738 +        p_dev_cfg->dev_inst_list_begin     = p_dev_inst_data;
11739 +    else
11740 +        p_dev_cfg->dev_inst_list_end->next = p_dev_inst_data;
11741 +
11742 +    p_dev_cfg->dev_inst_list_end           = p_dev_inst_data;
11743 +
11744 +    p_dev_cfg->count++;
11745 +
11746 +    return (0);
11747 +}
11748 +
11749 +/*-----------------------------------------------------------------------------
11750 + * Create the device cfg.
11751 + *---------------------------------------------------------------------------*/
11752 +DEVICE_CFG_T *p_create_dev_cfg(char *device_name)
11753 +{
11754 +    DEVICE_CFG_T *p_dev_cfg = NULL;
11755 +
11756 +    if((p_dev_cfg = os_malloc(sizeof(DEVICE_CFG_T))) == NULL)
11757 +    {
11758 +        dbgPrint("Failed to allocate memory for DEVICE_CFG_T.\n");
11759 +    }
11760 +    else if((p_dev_cfg->device_name = os_malloc(psp_config_strlen(device_name) + 1))==NULL)
11761 +    {
11762 +        dbgPrint("Failed to allocate memory for device name.\n");
11763 +    }
11764 +    else
11765 +    {
11766 +        psp_config_strcpy(p_dev_cfg->device_name, device_name);
11767 +        p_dev_cfg->cfg_type = en_raw;
11768 +        p_dev_cfg->count = 0;
11769 +        p_dev_cfg->dev_inst_list_begin = NULL;
11770 +        p_dev_cfg->dev_inst_list_end   = NULL;
11771 +        p_dev_cfg->next                = NULL;
11772 +    }
11773 +
11774 +    return(p_dev_cfg);
11775 +}
11776 +
11777 +/*------------------------------------------------------------------------------
11778 + * Get the device cfg collection.
11779 + *-----------------------------------------------------------------------------*/
11780 +DEVICE_CFG_T *p_get_dev_cfg(char *device_name)
11781 +{
11782 +    int count               = 0;
11783 +    DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
11784 +
11785 +    for(count=0; count < g_device_cfg_list.count; count++)
11786 +    {
11787 +        if(psp_config_strcmp(device_name, p_dev_cfg->device_name) == 0)
11788 +        {
11789 +            break;
11790 +        }
11791 +
11792 +        p_dev_cfg = p_dev_cfg->next;
11793 +    }
11794 +
11795 +    return(p_dev_cfg);
11796 +}
11797 +
11798 +/*-------------------------------------------------------------------------
11799 + * Gets the name for the static cfg type. Utility function. Debug purposes.
11800 + *-------------------------------------------------------------------------*/
11801 +char *p_get_cfg_type_name_for_en(CFG_TYPE_T  cfg_type)
11802 +{
11803 +    static char raw_str      [] = "still raw";
11804 +    static char compile_str  [] = "configured at compile time";
11805 +    static char optconf_str  [] = "configured by options.conf";
11806 +    static char vlynq_str    [] = "configured by VLYNQ";
11807 +    static char no_static_str[] = "no static configuration";
11808 +
11809 +    if(cfg_type == en_raw)
11810 +        return (raw_str);
11811 +    else if(cfg_type == en_compile)
11812 +        return (compile_str);
11813 +    else if(cfg_type == en_opt_conf)
11814 +        return (optconf_str);
11815 +    else if(cfg_type == en_vlynq)
11816 +        return (vlynq_str);
11817 +    else
11818 +        return (no_static_str);
11819 +
11820 +}
11821 +
11822 +/*-----------------------------------------------------------------------------
11823 + * Sets the static cfg status of the device collection.
11824 + *
11825 + * If the collection is en_virgin then, the collection is assigned to cfg_type.
11826 + * If the cfg_type is en_vlynq then, the old cfg_type is retained.
11827 + * en_compile and en_opt_conf are mutually exclusive. One of these can be
11828 + * accomodated.
11829 + *
11830 + *---------------------------------------------------------------------------*/
11831 +int p_set_device_cfg_type(DEVICE_CFG_T    *p_dev_cfg,
11832 +                          CFG_TYPE_T      cfg_type)
11833 +{
11834 +    int ret_val = 0;
11835 +
11836 +    if(p_dev_cfg->cfg_type == en_raw)
11837 +        p_dev_cfg->cfg_type = cfg_type;
11838 +    else if((cfg_type == en_vlynq) || (p_dev_cfg->cfg_type == cfg_type))
11839 +        ;
11840 +    else
11841 +    {
11842 +        dbgPrint("Device %s has been %s which overrides %s.\n",
11843 +                  p_dev_cfg->device_name,
11844 +                  p_get_cfg_type_name_for_en(p_dev_cfg->cfg_type),
11845 +                  p_get_cfg_type_name_for_en(cfg_type));
11846 +        ret_val = -1;
11847 +    }
11848 +
11849 +    return(ret_val);
11850 +}
11851 +
11852 +/*------------------------------------------------------------------------
11853 + * Add the config str into the repository. The cfg type indicates
11854 + * whether the device has been configured statically, from options.conf or
11855 + * by vlynq enumeration.
11856 + *------------------------------------------------------------------------*/
11857 +int psp_config_add(char *key, void *p_cfg_str, unsigned int cfg_len,
11858 +                   CFG_TYPE_T cfg_type)
11859 +{
11860 +    int                     ret_val           = -1;
11861 +    DEVICE_CFG_T            *p_dev_cfg        = NULL;
11862 +    DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data  = NULL;
11863 +
11864 +    if(p_cfg_str == NULL || key == NULL)
11865 +    {
11866 +        dbgPrint("Null input pointer(s).\n");
11867 +    }
11868 +    /* check if there exist a dev_cfg for the given key, if not,
11869 +       then create one and add it to the device list. */
11870 +    else if(((p_dev_cfg = p_get_dev_cfg(key)) == NULL) &&
11871 +            (((p_dev_cfg = p_create_dev_cfg(key)) == NULL) ||
11872 +               p_add_dev_cfg_to_list(&g_device_cfg_list, p_dev_cfg) != 0))
11873 +    {
11874 +        dbgPrint("Failed to allocate mem or add dev cfg for %s.\n", key);
11875 +    }
11876 +    /* make sure that we can add this cfg type to the repository */
11877 +    else if(p_set_device_cfg_type(p_dev_cfg, cfg_type) == -1)
11878 +    {
11879 +        dbgPrint("Ignoring \"%s\" for device \"%s\".\n",
11880 +                  p_get_cfg_type_name_for_en(cfg_type),
11881 +                  p_dev_cfg->device_name);
11882 +    }
11883 +    else if((p_dev_inst_data = os_malloc(sizeof(DEV_INSTANCE_CFG_DATA_T)))== NULL)
11884 +    {
11885 +        dbgPrint("Failed to allocate memory for DEV_INSTANCE_CFG_DATA_T.\n");
11886 +    }
11887 +    else if((p_dev_inst_data->data = os_malloc(cfg_len) + 1) == NULL)
11888 +    {
11889 +        dbgPrint("Failed to allocate memory for the config data.\n");
11890 +    }
11891 +    else
11892 +    {
11893 +        p_dev_inst_data->next = NULL;
11894 +
11895 +        if(cfg_type == en_opt_conf || cfg_type == en_compile)
11896 +            psp_config_strcpy(p_dev_inst_data->locale, "dev on chip ");
11897 +        else if(cfg_type == en_vlynq)
11898 +            psp_config_strcpy(p_dev_inst_data->locale, "dev on vlynq");
11899 +        else
11900 +            psp_config_strcpy(p_dev_inst_data->locale, "dev locale ?");
11901 +
11902 +        psp_config_memcpy(p_dev_inst_data->data, p_cfg_str, cfg_len);
11903 +        p_dev_inst_data->data_size = cfg_len;
11904 +        *(p_dev_inst_data->data + cfg_len) = '\0';
11905 +
11906 +        ret_val = p_add_instance_cfg_data(p_dev_cfg, p_dev_inst_data);
11907 +    }
11908 +
11909 +    return(ret_val);
11910 +}
11911 +
11912 +/*-------------------------------------------------------------
11913 + * Get the total number of device instances in the repository
11914 + *------------------------------------------------------------*/
11915 +int psp_config_get_num_keys(void)
11916 +{
11917 +    return(g_device_cfg_list.count);
11918 +}
11919 +
11920 +
11921 +/*--------------------------------------------------------------------
11922 + * Get the device configuration info from the repository.
11923 + *-------------------------------------------------------------------*/
11924 +int psp_config_get(char *key, int instance, char **cfg_data_out)
11925 +{
11926 +    int ret_val             = -1;
11927 +    DEVICE_CFG_T *p_dev_cfg = NULL;
11928 +    *cfg_data_out           = NULL;
11929 +
11930 +    if(key == NULL && cfg_data_out == NULL)
11931 +    {
11932 +        dbgPrint("Key has a NULL value.\n");
11933 +    }
11934 +    else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11935 +    {
11936 +        dbgPrint("cfg information for %s could not be found.\n", key);
11937 +    }
11938 +    else if(p_dev_cfg->count)
11939 +    {
11940 +         DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data =
11941 +                                  p_dev_cfg->dev_inst_list_begin;
11942 +         int index = 0;
11943 +         for(index = 0;
11944 +             index != instance && index < p_dev_cfg->count;
11945 +             index++)
11946 +         {
11947 +             p_dev_inst_data = p_dev_inst_data->next;
11948 +         }
11949 +
11950 +         if(p_dev_inst_data != NULL && p_dev_inst_data->data != NULL)
11951 +         {
11952 +             *cfg_data_out = p_dev_inst_data->data;
11953 +             ret_val = p_dev_inst_data->data_size;
11954 +         }
11955 +    }
11956 +
11957 +    return (ret_val);
11958 +}
11959 +
11960 +/*----------------------------------------------------------------
11961 + * Returns the number of instances found in the repository for the
11962 + * specified key.
11963 + *---------------------------------------------------------------*/
11964 +int psp_config_get_num_instances(char *key)
11965 +{
11966 +    int ret_val             = 0;
11967 +    DEVICE_CFG_T *p_dev_cfg = NULL;
11968 +
11969 +    if(key == NULL)
11970 +    {
11971 +        dbgPrint("Key has a NULL value.\n");
11972 +    }
11973 +    else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11974 +    {
11975 +        dbgPrint("cfg information for %s could not be found.\n", key);
11976 +    }
11977 +    else
11978 +    {
11979 +        ret_val = p_dev_cfg->count;
11980 +    }
11981 +
11982 +    return (ret_val);
11983 +}
11984 +
11985 +/*------------------------------------------------------------------
11986 + * Dump the configuration repository.
11987 + * Caution: DO NOT USE THIS FOR ANY NON NBU specified config format.
11988 + *-----------------------------------------------------------------*/
11989 +void psp_config_print(char *key)
11990 +{
11991 +    DEVICE_CFG_T *p_dev_cfg = NULL;
11992 +
11993 +    if(key == NULL)
11994 +    {
11995 +        dbgPrint("Key has a NULL value.\n");
11996 +    }
11997 +    else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11998 +    {
11999 +        dbgPrint("cfg information for %s could not be found.\n", key);
12000 +    }
12001 +    else if(p_dev_cfg && p_dev_cfg->count)
12002 +    {
12003 +        DEV_INSTANCE_CFG_DATA_T   *p_dev_inst_data;
12004 +
12005 +        p_dev_inst_data = p_dev_cfg->dev_inst_list_begin;
12006 +
12007 +        do
12008 +        {
12009 +            dbgPrint("%s : %s\n", p_dev_inst_data->locale,
12010 +                      p_dev_inst_data->data);
12011 +            p_dev_inst_data = p_dev_inst_data->next;
12012 +
12013 +        } while(p_dev_inst_data);
12014 +    }
12015 +    else
12016 +    {
12017 +        dbgPrint("Nothing was found for %s.\n", key);
12018 +    }
12019 +}
12020 +
12021 +void dump_device_cfg_pool(void)
12022 +{
12023 +    DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
12024 +
12025 +    if(p_dev_cfg != NULL && g_device_cfg_list.count)
12026 +    {
12027 +        int index=0;
12028 +
12029 +        for(index=0; index < g_device_cfg_list.count; index++)
12030 +        {
12031 +            psp_config_print(p_dev_cfg->device_name);
12032 +            p_dev_cfg = p_dev_cfg->next;
12033 +        }
12034 +    }
12035 +    else
12036 +    {
12037 +        dbgPrint("repository is empty.\n");
12038 +    }
12039 +}
12040 +
12041 +void psp_config_init(void)
12042 +{
12043 +    p_init_device_cfg_list();
12044 +}
12045 +
12046 +void psp_config_cleanup()
12047 +{
12048 +    int dev_count              = 0;
12049 +    int inst_count             = 0;
12050 +    DEVICE_CFG_T            *p = g_device_cfg_list.device_cfg_begin;
12051 +    DEV_INSTANCE_CFG_DATA_T *q = NULL;
12052 +
12053 +    for(dev_count = 0; dev_count < g_device_cfg_list.count; dev_count++)
12054 +    {
12055 +        DEVICE_CFG_T            *p_temp = NULL;
12056 +        if(p) q = p->dev_inst_list_begin;
12057 +
12058 +        for(inst_count = 0; inst_count < p->count && q != NULL; inst_count++)
12059 +        {
12060 +            DEV_INSTANCE_CFG_DATA_T *q_temp = q;
12061 +            q_temp = q->next;
12062 +            kfree(q->data);
12063 +            kfree(q);
12064 +            q = q_temp;
12065 +        }
12066 +
12067 +        p_temp = p->next;
12068 +        kfree(p);
12069 +        p = p_temp;
12070 +    }
12071 +}
12072 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.h linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.h
12073 --- linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.h      1970-01-01 01:00:00.000000000 +0100
12074 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.h      2005-07-12 02:48:42.177573000 +0200
12075 @@ -0,0 +1,110 @@
12076 +/******************************************************************************
12077 + * FILE PURPOSE:    PSP Config Manager Header
12078 + ******************************************************************************
12079 + * FILE NAME:       psp_config_mgr.h
12080 + *
12081 + * DESCRIPTION:     Storing and retrieving the configuration based on key
12082 + * A set of APIs to be used by one and sundry (including drivers and enumerator) to build
12083 + * and read cfg information of the devices for an avalanche SOC.
12084 + *
12085 + * This set of APIs isolates the configuration management from the world and provides simple
12086 + * access convinience.
12087 + *
12088 + * Device in this set refers to the peripherals that can be found on the SOC or on VLYNQ.
12089 + * The configuration is stored in the form of string and drivers can use these APIs to get
12090 + * a particular parameter value.
12091 + *
12092 + * The memory allocation for the pass back parameters is done by the caller.
12093 + *
12094 + * 0 is returned for SUCCESS or TRUE.
12095 + *  -1 is returned for FAILURE or FALSE.
12096 + *
12097 + * REVISION HISTORY:
12098 + * 27 Nov 02 - PSP TII
12099 + *
12100 + * (C) Copyright 2002, Texas Instruments, Inc
12101 + *******************************************************************************/
12102 +
12103 +#ifndef __PSP_CONFIG_MGR_H__
12104 +#define __PSP_CONFIG_MGR_H__
12105 +
12106 +typedef enum cfg_type
12107 +{
12108 +    en_raw     = 0,
12109 +    en_compile,
12110 +    en_opt_conf,
12111 +    en_vlynq
12112 +} CFG_TYPE_T;
12113 +
12114 +/* Build psp configuration */
12115 +void build_psp_config(void);
12116 +
12117 +/********************************************************
12118 + * Access Operations.
12119 + ********************************************************/
12120 +
12121 +/*-------------------------------------------------------------------------
12122 +   initializes the configuration repository.
12123 + -------------------------------------------------------------------------*/
12124 +void  psp_config_init(void);
12125 +
12126 +/*--------------------------------------------------------------------------
12127 +   Adds the configuration information into the repository. 'key' is required
12128 +   to be NULL terminated string. 'cfg_ptr' points to the configuration data.
12129 +   'cfg_len' is the length of the data pointed to by 'cfg_ptr' in bytes.
12130 +   'cfg_type' indicates the type of config information.
12131 +
12132 +   psp_config_mgr copies the 'cfg_len' bytes of data pointed to by 'cfg_ptr'
12133 +   into its internal repository.
12134 +
12135 +   Returns: 0 on success, -1 on failure.
12136 +  -------------------------------------------------------------------------*/
12137 +int   psp_config_add(char *key, void *cfg_ptr,
12138 +                     unsigned int cfg_len, CFG_TYPE_T cfg_type);
12139 +
12140 +
12141 +/* --------------------------------------------------------------------------
12142 +   Passes back, in "*cfg_out_val" a pointer to the config data in the repository
12143 +   for the specified 'key' and 'instance'. It returns the size of the config
12144 +   info
12145 +
12146 +   psp_config_mgr passes back a pointer in '*cfg_out_val' which refers to
12147 +   some location in its internal repository. It is strongly recommended that
12148 +   if the user intends to modify the contents of the config info for reasons
12149 +   whatsoever, then, user should allocate memory of size returned by this
12150 +   routine and copy the contents from '*cfg_out_val'.
12151 +
12152 +   Any, modification carried out on the repository would lead to un-expected
12153 +   results.
12154 +
12155 +   Returns: 0 or more for the size of config info, -1 on error.
12156 +  --------------------------------------------------------------------------*/
12157 +int   psp_config_get(char *key, int instance, char **cfg_out_val);
12158 +
12159 +
12160 +/*--------------------------------------------------------------------------
12161 +   Get the number of keys that have been added in the repository so far.
12162 +
12163 +   Returns: 0 or more for the num of keys, -1 on error.
12164 +  -------------------------------------------------------------------------*/
12165 +int   psp_config_get_num_keys(void);
12166 +
12167 +
12168 +/*--------------------------------------------------------------------------
12169 +   Get the number of instances that are present in the repository for the
12170 +   given 'key'.
12171 +
12172 +   Returns: 0 or more for the num of instances, -1 on error.
12173 +  -------------------------------------------------------------------------*/
12174 +int   psp_config_get_num_instances(char *key);
12175 +
12176 +
12177 +/*--------------------------------------------------------------------------
12178 +   Prints the config data for all instances associated with the specified
12179 +   'key'.
12180 +  -------------------------------------------------------------------------*/
12181 +void  psp_config_print(char *key);
12182 +
12183 +void  dump_device_cfg_pool(void);
12184 +
12185 +#endif /* __PSP_CONFIG_MGR_H__ */
12186 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_parse.c linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.c
12187 --- linux.old/drivers/net/avalanche_cpmac/psp_config_parse.c    1970-01-01 01:00:00.000000000 +0100
12188 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.c    2005-07-12 02:48:42.178573000 +0200
12189 @@ -0,0 +1,362 @@
12190 +/******************************************************************************
12191 + * FILE PURPOSE:    PSP Config Manager - Parse API Source
12192 + ******************************************************************************
12193 + * FILE NAME:       psp_config_parse.c
12194 + *
12195 + * DESCRIPTION:     These APIs should be used only for scanvenging parameters which
12196 + *                  are stored in the following format.
12197 + *
12198 + *                  str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12199 + *
12200 + * REVISION HISTORY:
12201 + * 27 Nov 02 - PSP TII
12202 + *
12203 + * (C) Copyright 2002, Texas Instruments, Inc
12204 + *******************************************************************************/
12205 +
12206 +//#include <stdio.h>
12207 +#include <linux/stddef.h>
12208 +
12209 +/*--------------------------------------------------
12210 + * MACROS.
12211 + *-------------------------------------------------*/
12212 +#define my_isdigit(c) (c >= '0' && c <= '9')
12213 +#define my_isoct(c)   (c >= '0' && c <= '7')
12214 +#define my_xtod(c)    ((c) <= '9' ? (c) - '0' : (c) - 'a' +  10)
12215 +#define my_ifupper(c)    (c >= 'A' && c <= 'F')
12216 +#define XTOD(c)       ((c) - 'A' + 10)
12217 +#define my_ishex(c)   ((c >= 'a' && c <='f') || (c >= 'A' && c<='F') || my_isdigit(c) )
12218 +
12219 +/*---------------------------------------------------
12220 + * Local Functions.
12221 + *--------------------------------------------------*/
12222 +static int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
12223 +                                 char end_delimiter, int pair_flag,
12224 +                                 char **p_out_str);
12225 +static int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
12226 +                                char end_delimiter, unsigned long *out_val);
12227 +
12228 +/*---------------------------------------------------
12229 + * Return pointer to first instance of the char.
12230 + *--------------------------------------------------*/
12231 +static char* psp_config_strchr(char *str, char chr)
12232 +{
12233 +    while(*str)
12234 +    {
12235 +        if(*str == chr)
12236 +            break;
12237 +        str++;
12238 +    }
12239 +
12240 +    return((*str) ? str : NULL);
12241 +}
12242 +
12243 +/*------------------------------------------------------------------------
12244 + * Convert the string upto delimiter to unsigned long.
12245 + *-----------------------------------------------------------------------*/
12246 +unsigned long my_atoul(char *p, char end_delimiter, unsigned long *out_val)
12247 +{
12248 +    unsigned long n;
12249 +    int c;
12250 +
12251 +    /* check the for null input */
12252 +    if (!p)
12253 +        return -1;
12254 +
12255 +    c = *p;
12256 +
12257 +    /* pass through the leading spaces */
12258 +    if (!my_isdigit(c))
12259 +    {
12260 +        while ( c == ' ')
12261 +            c = *++p;
12262 +
12263 +    }
12264 +
12265 +    if (c == '0')
12266 +    {
12267 +        if(*(p + 1) == 'x' || *(p+1) == 'X' )
12268 +        {
12269 +            /* string is in hex format */
12270 +
12271 +            p += 2;
12272 +            c = *p;
12273 +
12274 +            if(my_ishex(c))
12275 +            {
12276 +               if(my_ifupper(c))
12277 +                   n = XTOD(c);
12278 +               else
12279 +                       n = my_xtod(c);
12280 +            }
12281 +            else
12282 +                return -1; /* invalid hex string format */
12283 +
12284 +            while ((c = *++p) && my_ishex(c))
12285 +            {
12286 +                n *= 16;
12287 +                if(my_ifupper(c))
12288 +                   n += XTOD(c);
12289 +                else
12290 +                       n += my_xtod(c);
12291 +            }
12292 +         }
12293 +        else
12294 +        {
12295 +            /* string is in octal format */
12296 +
12297 +            if( my_isoct(c) )
12298 +            n = c - '0';
12299 +            else
12300 +                return -1; /* invalid octal string format */
12301 +
12302 +            while ((c = *++p) && my_isoct(c))
12303 +            {
12304 +                n *= 8;
12305 +                n += c - '0';
12306 +            }
12307 +        }
12308 +
12309 +    }
12310 +    else
12311 +    {
12312 +        /* string is in decimal format */
12313 +
12314 +        if( my_isdigit(c) )
12315 +            n = c - '0';
12316 +        else
12317 +            return -1; /* invalid decimal string format */
12318 +
12319 +        while ((c = *++p) && my_isdigit(c))
12320 +        {
12321 +            n *= 10;
12322 +            n += c - '0';
12323 +        }
12324 +    }
12325 +
12326 +    /* move through the trailing spaces */
12327 +    while(*p == ' ')
12328 +        p++;
12329 +
12330 +    if(*p == end_delimiter)
12331 +       {
12332 +           *out_val = n;
12333 +           return 0;
12334 +       }
12335 +
12336 +    else
12337 +        return -1; /* invalid string format */
12338 +}
12339 +
12340 +/*---------------------------------------------------------------------------------
12341 + * Gets the substring de-limited by the 'begin_delimiter' and 'end_delimiter'.
12342 + * and returns the size of the substring.
12343 + *
12344 + * Parses the NULL terminated p_in_str for a character array delimited by
12345 + * begin_delimiter and end_delimiter, passes back the pointer to the character
12346 + * array in ' *p_out_str '. The passed pointer ' *p_out_str ' should point to
12347 + * the location next (byte) to the begin_delimiter. The function routine returns
12348 + * the number of characters excluding the begin_delimiter and end_delimiter,
12349 + * found in the array delimited by the said delimiters.
12350 + *
12351 + * If the pair_flag is set to 1, then, number of begin_delimiter and end_delimiter
12352 + * found in the parsing should match (equal) and this routine passes back the
12353 + * pointer to the character array, starting at a location next (byte) to the
12354 + * first begin_delimiter,  inclusive of all intermediate matching delimiter
12355 + * characters found between outer delimiters. If the pair flag is set and if
12356 + * begin_delimiter and end_delimiter happens to be same, then error (-1) is
12357 + * returned.
12358 + *
12359 + * Return: 0 or more to indicate the size of the substring, -1 on error.
12360 + *-------------------------------------------------------------------------------*/
12361 +int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
12362 +                          char end_delimiter, int pair_flag,
12363 +                          char **p_out_str)
12364 +{
12365 +    int cnt,pos;
12366 +
12367 +    if(pair_flag  && begin_delimiter == end_delimiter)
12368 +        return -1;
12369 +
12370 +    if((p_in_str = psp_config_strchr(p_in_str, begin_delimiter)) == 0)
12371 +        return -1; /* no start delimiter found */
12372 +
12373 +    p_in_str++;
12374 +    *p_out_str = p_in_str;
12375 +
12376 +    for(pos = 0,cnt =1; cnt && p_in_str[pos] ; pos++)
12377 +    {
12378 +        if(p_in_str[pos] == end_delimiter)
12379 +        {
12380 +            if(pair_flag == 0)
12381 +                return pos;
12382 +
12383 +            cnt--;
12384 +        }
12385 +        else if(p_in_str[pos] == begin_delimiter)
12386 +            cnt++;
12387 +        else
12388 +            ; /* We do nothing */
12389 +
12390 +    }
12391 +
12392 +    if( cnt == 0)
12393 +        return pos - 1;
12394 +    else
12395 +        return -1; /* no corresponding end delimiter found */
12396 +}
12397 +
12398 +/*--------------------------------------------------------------------------
12399 + * Parses the NULL terminated p_in_str for unsigned long value delimited by
12400 + * begin_delimiter and end_delimiter, passes back the found in ' *out_val '.
12401 + * The function routine returns 0 on success and returns -1 on failure.
12402 + * The first instance of the de-limiter should be accounted for the parsing.
12403 + *
12404 + * The base for unsigned value would 10, octal and hex. The value passed back
12405 + * would be of the base 10. Spaces at the begining of the byte array are valid
12406 + * and should be ingnored in the calculation of the value. Space character in
12407 + * the middle of the byte array or any character other than the valid ones
12408 + * (based on base type) should return error. The octal value begins with '0',
12409 + * the hex value begins with "0x" or "0X", the base value can begin with
12410 + * '1' to '9'.
12411 + *
12412 + * Returns: 0 on success, -1 on failure.
12413 + *-------------------------------------------------------------------------*/
12414 +int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
12415 +                         char end_delimiter, unsigned long *out_val)
12416 +{
12417 +    char *start;
12418 +    unsigned long num;
12419 +
12420 +    num = p_get_substr_from_str(p_in_str, begin_delimiter, end_delimiter,
12421 +                                0, &start);
12422 +
12423 +    if(num == (unsigned long)-1)
12424 +        return -1;
12425 +
12426 +    return my_atoul(start,end_delimiter,out_val);
12427 +}
12428 +
12429 +/*--------------------------------------------------------------------------
12430 + * Finds the first occurrence of the substring p_find_str in the string
12431 + * p_in_str.
12432 + *-------------------------------------------------------------------------*/
12433 +char *my_strstr(char *p_in_str, const char *p_find_str)
12434 +{
12435 +    char *p = (char *)p_find_str;
12436 +    char *ret = NULL;
12437 +
12438 +    while(*p_in_str)
12439 +    {
12440 +        if(!(*p))
12441 +            return (ret);
12442 +        else if(*p_in_str == *p)
12443 +        {
12444 +            if(!ret) ret = p_in_str;
12445 +            p++;
12446 +            p_in_str++;
12447 +        }
12448 +        else if(ret)
12449 +        {
12450 +            p = (char *)p_find_str;
12451 +            p_in_str = ret + 1;
12452 +            ret = NULL;
12453 +        }
12454 +        else
12455 +            p_in_str++;
12456 +    }
12457 +
12458 +    if(*p_in_str != *p) ret = NULL;
12459 +
12460 +    return (ret);
12461 +
12462 +}
12463 +
12464 +/*------------------------------------------------------------------------------
12465 + * Gets the value of the config param in the unsigned int format. The value is
12466 + * stored in the following format in the string.
12467 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12468 + *-----------------------------------------------------------------------------*/
12469 +int psp_config_get_param_uint(char *p_in_str, const char *param, unsigned int *out_val)
12470 +{
12471 +    int   ret_val = -1;
12472 +    char *p_strstr;
12473 +
12474 +    if(!p_in_str || !param || !out_val)
12475 +    {
12476 +        ;
12477 +    }
12478 +    else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
12479 +    {
12480 +        ;
12481 +    }
12482 +    else if(p_get_u_int_from_str(p_strstr, '=', ',', (unsigned long *)out_val) == 0)
12483 +    {
12484 +        ret_val = 0;
12485 +    }
12486 +    else if(p_get_u_int_from_str(p_strstr, '=', ']', (unsigned long*)out_val) == 0)
12487 +    {
12488 +        ret_val = 0;
12489 +    }
12490 +    else if(p_get_u_int_from_str(p_strstr, '=', ')', (unsigned long*)out_val) == 0)
12491 +    {
12492 +        ret_val = 0;
12493 +    }
12494 +    else
12495 +    {
12496 +        /* we failed */
12497 +    }
12498 +
12499 +    return (ret_val);
12500 +}
12501 +
12502 +/*------------------------------------------------------------------------------
12503 + * Gets the value of the config param in the Non NULL terminated format. The value
12504 + * is stored in the following format in the string.
12505 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12506 + *-----------------------------------------------------------------------------*/
12507 +int psp_config_get_param_string(char *p_in_str, const char *param, char **out_val)
12508 +{
12509 +    int ret_val = -1;
12510 +    char *p_strstr;
12511 +
12512 +    if(!p_in_str || !param || !(out_val))
12513 +        ;
12514 +    else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
12515 +    {
12516 +        ;
12517 +    }
12518 +    else if((ret_val = p_get_substr_from_str(p_strstr, '[', ']', 1, out_val)) == -1)
12519 +    {
12520 +        ;
12521 +    }
12522 +    else
12523 +    {
12524 +        ; /* we got the value */
12525 +    }
12526 +
12527 +    return (ret_val);
12528 +}
12529 +
12530 +#ifdef PSP_CONFIG_MGR_DEBUG_TEST
12531 +main()
12532 +{
12533 +    unsigned long num =999;
12534 +    int ret = 0;
12535 +    char *val1 = NULL;
12536 +    char val[30];
12537 +    char str1[] = "cpmac(id=[cpmac], k0=[a1=[a2=[test], a3=2], k1=100, k2=[k3=300, k4=200], k7=722)";
12538 +
12539 +    psp_config_get_param_uint(str1, "k7", &num);
12540 +    printf("%u.\n", num);
12541 +    ret = psp_config_get_param_string(str1, "a1", &val1);
12542 +    if(ret >= 0) { printf("%d.\n", ret); strncpy(val, val1, ret); val[ret] = '\0';}
12543 +
12544 +    printf("val = \"%s\", and size = %d \n", val, ret);
12545 +
12546 +    if(val[ret]) ; else printf("jeee.\n");
12547 +}
12548 +#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
12549 +
12550 +
12551 +
12552 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_parse.h linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.h
12553 --- linux.old/drivers/net/avalanche_cpmac/psp_config_parse.h    1970-01-01 01:00:00.000000000 +0100
12554 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.h    2005-07-12 02:48:42.178573000 +0200
12555 @@ -0,0 +1,32 @@
12556 +/******************************************************************************
12557 + * FILE PURPOSE:    PSP Config Manager - Parse API Header
12558 + ******************************************************************************
12559 + * FILE NAME:       psp_config_parse.h
12560 + *
12561 + * DESCRIPTION:     Parsing for params from string available in the NBU format.
12562 + *                  These APIs should be used only for scanvenging parameters which
12563 + *                  are stored in the following format.
12564 + *
12565 + *                  str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12566 + *
12567 + * REVISION HISTORY:
12568 + * 27 Nov 02 - PSP TII
12569 + *
12570 + * (C) Copyright 2002, Texas Instruments, Inc
12571 + *******************************************************************************/
12572 +
12573 +#ifndef __PSP_CONFIG_PARSER_H__
12574 +#define __PSP_CONFIG_PARSER_H__
12575 +
12576 +/*------------------------------------------------------------------
12577 + * These APIs should be used only for scanvenging parameters which
12578 + * are stored in the following format.
12579 + *
12580 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12581 + *-----------------------------------------------------------------*/
12582 +int psp_config_get_param_uint(char *p_in_str, const char *param,
12583 +                              unsigned int *out_val);
12584 +int psp_config_get_param_string(char *p_in_str, const char *param,
12585 +                                char **out_val);
12586 +
12587 +#endif /* __PSP_CONFIG_PARSER_H__ */
12588 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_util.c linux.dev/drivers/net/avalanche_cpmac/psp_config_util.c
12589 --- linux.old/drivers/net/avalanche_cpmac/psp_config_util.c     1970-01-01 01:00:00.000000000 +0100
12590 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_util.c     2005-07-12 02:48:42.178573000 +0200
12591 @@ -0,0 +1,106 @@
12592 +/******************************************************************************
12593 + * FILE PURPOSE:    PSP Config Manager - Utilities API Source
12594 + ******************************************************************************
12595 + * FILE NAME:       psp_config_util.c
12596 + *
12597 + * DESCRIPTION:     These APIs provide the standard "C" string interfaces.
12598 + *                  Provided here to reduce dependencies on the standard libraries
12599 + *                  and for cases where psp_config would required to run before
12600 + *                  the whole system is loaded or outside the scope of the OS.
12601 + *
12602 + * REVISION HISTORY:
12603 + * 27 Nov 02 - PSP TII
12604 + *
12605 + * (C) Copyright 2002, Texas Instruments, Inc
12606 + *******************************************************************************/
12607 +
12608 +//#include <stdio.h>
12609 +#include "psp_config_util.h"
12610 +#include <linux/stddef.h>
12611 +
12612 +/*---------------------------------------------
12613 + * strlen.
12614 + *-------------------------------------------*/
12615 +int psp_config_strlen(char *p)
12616 +{
12617 +    char *p_orig = p;
12618 +    while(*p)
12619 +        p++;
12620 +    return(p - p_orig);
12621 +}
12622 +
12623 +/*--------------------------------------------
12624 + * strcmp.
12625 + *-------------------------------------------*/
12626 +int psp_config_strcmp(char *s1, char *s2)
12627 +{
12628 +    while(*s1 && *s2)
12629 +    {
12630 +        if(*s1 != *s2)
12631 +            break;
12632 +        s1++;
12633 +        s2++;
12634 +    }
12635 +
12636 +    return(*s1 - *s2);
12637 +}
12638 +
12639 +/*--------------------------------------------
12640 + * strcpy.
12641 + *------------------------------------------*/
12642 +char* psp_config_strcpy(char *dest, char *src)
12643 +{
12644 +    char *dest_orig = dest;
12645 +
12646 +    while(*src)
12647 +    {
12648 +        *dest++ = *src++;
12649 +    }
12650 +
12651 +    *dest = '\0';
12652 +
12653 +    return(dest_orig);
12654 +}
12655 +
12656 +/*----------------------------------------------
12657 + * psp_config_memcpy.
12658 + *--------------------------------------------*/
12659 +void* psp_config_memcpy(void* dest, void* src, unsigned int n)
12660 +{
12661 +    void *dest_orig = dest;
12662 +
12663 +    while(n)
12664 +    {
12665 +        *(char *)dest++ = *(char *)src++;
12666 +        n--;
12667 +    }
12668 +
12669 +    return (dest_orig);
12670 +}
12671 +
12672 +/*---------------------------------------------------
12673 + * Return pointer to first instance of the char.
12674 + *--------------------------------------------------*/
12675 +char* psp_config_strchr(char *str, char chr)
12676 +{
12677 +    while(*str)
12678 +    {
12679 +        if(*str == chr)
12680 +            break;
12681 +        str++;
12682 +    }
12683 +
12684 +    return((*str) ? str : NULL);
12685 +}
12686 +
12687 +#ifdef PSP_CONFIG_MGR_DEBUG_TEST
12688 +
12689 +int main( )
12690 +{
12691 +    char s[] = "hello             ";
12692 +    printf("%d.\n", psp_config_strlen("hello\n"));
12693 +    printf("%d.\n", psp_config_strcmp("hells", "hellq"));
12694 +    printf("%s %s.\n", psp_config_strcpy(s + 6, "test1"), s);
12695 +}
12696 +
12697 +#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
12698 diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_util.h linux.dev/drivers/net/avalanche_cpmac/psp_config_util.h
12699 --- linux.old/drivers/net/avalanche_cpmac/psp_config_util.h     1970-01-01 01:00:00.000000000 +0100
12700 +++ linux.dev/drivers/net/avalanche_cpmac/psp_config_util.h     2005-07-12 02:48:42.179573000 +0200
12701 @@ -0,0 +1,26 @@
12702 +/******************************************************************************
12703 + * FILE PURPOSE:    PSP Config Manager - Utilities API Header
12704 + ******************************************************************************
12705 + * FILE NAME:       psp_config_util.h
12706 + *
12707 + * DESCRIPTION:     These APIs provide the standard "C" string interfaces.
12708 + *                  Provided here to reduce dependencies on the standard libraries
12709 + *                  and for cases where psp_config would required to run before
12710 + *                  the whole system is loaded or outside the scope of the OS.
12711 + *
12712 + * REVISION HISTORY:
12713 + * 27 Nov 02 - PSP TII
12714 + *
12715 + * (C) Copyright 2002, Texas Instruments, Inc
12716 + *******************************************************************************/
12717 +
12718 +#ifndef __PSP_CONFIG_UTIL_H__
12719 +#define __PSP_CONFIG_UTIL_H__
12720 +
12721 +extern int   psp_config_strlen(char*);
12722 +extern int   psp_config_strcmp(char*, char*);
12723 +extern char* psp_config_strcpy(char*, char*);
12724 +extern void* psp_config_memcpy(void*, void*, unsigned int n);
12725 +extern char* psp_config_strchr(char*, char);
12726 +
12727 +#endif /* __PSP_CONFIG_UTIL_H__ */
12728 diff -urN linux.old/drivers/net/avalanche_cpmac/readme.txt linux.dev/drivers/net/avalanche_cpmac/readme.txt
12729 --- linux.old/drivers/net/avalanche_cpmac/readme.txt    1970-01-01 01:00:00.000000000 +0100
12730 +++ linux.dev/drivers/net/avalanche_cpmac/readme.txt    2005-07-12 02:48:42.179573000 +0200
12731 @@ -0,0 +1,545 @@
12732 +23 August 2004      CPMAC 1.7.8 (NSP Performance Team Release)
12733 +
12734 +CC Labels: REL_20040823_HALdallas_cpmac_01.07.08
12735 +
12736 +New features:  Key "MacAddr" can now be used to set the Mac Address after Open.
12737 +
12738 + unsigned char MacAddr[6];
12739 +
12740 +  // Set Mac Address to "00.B0.D0.10.80.C1"
12741 +  MacAddr[0] = 0x00;
12742 +  MacAddr[1] = 0xB0;
12743 +  MacAddr[2] = 0xD0;
12744 +  MacAddr[3] = 0x10;
12745 +  MacAddr[4] = 0x80;
12746 +  MacAddr[5] = 0xC1;
12747 +
12748 +  HalFunc->Control(HalDev, "MacAddr", hcSet, &MacAddr);
12749 +
12750 +Bug fixes: in Send(), Threshold is not checked if Tx Ints are re-enabled.
12751 +
12752 +Modules affected:  hcpmac.c, hcpmac.h, cppi_cpmac.c
12753 +
12754 +22 June 2004          CPMAC 1.7.6 (NSP Performance Team Release)
12755 +
12756 +CC Labels: REL_20040622_HALdallas_cpmac_01.07.06
12757 +
12758 +New features:  Key "TxIntDisable" used to disable Tx Interrupts. If it is set, then Tx Interrupts will be processed on Send() controlled by Tx ServiceMax Setting.
12759 +
12760 + int On = 1;
12761 + HalFunc->Control(HalDev, "TxIntDisable", "Set", &On);
12762 +
12763 +Bug fixes: NTR
12764 +
12765 +10 June 2004          CPMAC 1.7.5 (external release)
12766 +
12767 +CC Labels: REL_20040610_HALdallas_cpmac_01.07.05
12768 +
12769 +New features:  NTR
12770 +
12771 +Bug fixes: Fixed an issue with calculation for the multicast hash.
12772 +
12773 +27 May 2004          CPSAR 1.7.4, CPMAC 1.7.4 (external release)
12774 +
12775 +CC Labels: REL_20040527_HALdallas_cpsar_01.07.04
12776 +           REL_20040527_HALdallas_cpmac_01.07.04
12777 +
12778 +New features:  NTR
12779 +
12780 +Bug fixes: A flaw was fixed in the critical sectioning of the CPPI file, affecting both
12781 +           the MAC and the SAR releases.  This flaw was detected on Titan PSP 4.7 BFT2.
12782 +
12783 +05 May 2004          CPSAR 1.7.3, CPMAC 1.7.3 (external release)
12784 +
12785 +CC Labels: REL_20040505_HALdallas_cpsar_01.07.03
12786 +                REL_20040505_HALdallas_cpmac_01.07.03
12787 +
12788 +New features:  NTR
12789 +
12790 +Bug fixes: 1) Firmware has been updated to fix a problem with Host OAM mode operation.
12791 +               2) Cache macros have been fixed.
12792 +
12793 +Notes:  This release contains all performance enhancements currently available for CPHAL 1.x.
12794 +
12795 +19 April 2004          CPSAR 1.7.2, CPMAC 1.7.2 (external release)
12796 +
12797 +CC Labels: REL_20040419_HALdallas_cpsar_01.07.02
12798 +                REL_20040419_HALdallas_cpmac_01.07.02
12799 +
12800 +New features:  NTR
12801 +
12802 +Bug fixes: Fixes merge problem in 1.7.1.
12803 +
12804 +Notes:  This is a branch release which contains only a subset of the performance improvements.
12805 +            The remaining performance improvements are stiill being qualified at this time.
12806 +
12807 +1 April 2004          CPSAR 1.7.1, CPMAC 1.7.1 (external release)
12808 +
12809 +NOTICE: DO NOT USE 1.7.1.  It has a known problem (see 1.7.2 notes)
12810 +
12811 +CC Labels: REL_20040401_HALdallas_cpsar_01.07.01
12812 +                REL_20040401_HALdallas_cpmac_01.07.01
12813 +
12814 +New features:  Performance improvement in CPPI layer, affecting both CPSAR and CPMAC.
12815 +
12816 +Bug fixes: NTR
12817 +
12818 +17 Februrary 2004    CPSAR 1.7.0 (external release)
12819 +
12820 +CC Labels: REL_20040217_HALdallas_cpsar_01.07.00
12821 +
12822 +New features:  Added support for "TxFlush" feature.  This allows the upper
12823 +               layer to flush all or part of a given Tx queue for a given
12824 +               channel.  This is to be used during call setup for a voice
12825 +               connection.
12826 +
12827 +30 January 2004      CPMAC 1.7.0 (external release)
12828 +
12829 +CC Labels: REL_20040130_HALdallas_cpmac_01.07.00
12830 +
12831 +Bug fixes:    CPMDIO - When in manual negotiate mode and linked, dropping link would move into NWAY state rather than manual state.
12832 +              CPMDIO - Extraneous debug message corrected
12833 +New features: CPMDIO - Support for AutoMdix usage added.
12834 +
12835 +25 September 2003      CPSAR 1.6.6 (external release)
12836 +
12837 +CC Labels: REL_20030925_HALdallas_cpsar_01.06.06
12838 +
12839 +Bug fixes:   PDSP firmware has been updated to fix the OAM padding problem.  It previously
12840 +             wrote pad bytes into a reserved field of the OAM cell.  There is a small
12841 +             change to the CPSAR configuration code which corresponds to the PDSP spec
12842 +             change.
12843 +
12844 +New features: NTR
12845 +
12846 +09 September 2003      CPMAC 1.6.6 (external release)
12847 +
12848 +CC Labels: REL_20030909_HALdallas_cpmac_01.06.06
12849 +
12850 +Bug fixes:   CPMAC : When _CPMDIO_NOPHY is set, Cpmac COntrol is set to Full Duplex
12851 +             Bridge loopback test does not show a problem using 1.6.5 if packet rate is
12852 +             below 50,000 pbs. Now testing with a 100% send from Ixia.
12853 +
12854 +New features: NTR
12855 +
12856 +05 August 2003         CPHAL 1.6.5 (external release)
12857 +
12858 +CC Labels: REL_20030805_HALdallas_cpmac_01.06.05
12859 +
12860 +Bug fixes: NTR
12861 +
12862 +New features:  CPMAC : Added support for CPMAC modules that do not have a Phy connected.
12863 +               The CPMAC is informed of this by the MdioConnect option
12864 +               _CPMDIO_NOPHY. This is the only driver change needed to
12865 +               receive and transmit packets through the Marvel switch.
12866 +               Note  In this mode Link status will reported linked at 100/FD to
12867 +               PhyNum 0xFFFFFFFF.
12868 +
12869 +               ALL:  Cleaned up some Vlynq support logic.
12870 +
12871 +16 July 2003         CPSAR 1.6.3 (external release), no CPMAC release
12872 +
12873 +CC Labels: REL_20030716_HALdallas_cpsar_01.06.03
12874 +
12875 +Bug fixes: 1) Changed default value of CPCS_UU from 0x5aa5 to 0.  The old default value caused
12876 +              problems with Cisco routers.
12877 +
12878 +New features:  NTR
12879 +
12880 +Known issues not addressed in this release: NTR.
12881 +
12882 +01 July 2003         CPHAL 1.6.2 (external release)
12883 +
12884 +CC Labels: REL_20030701_HALdallas_cpmac_01.06.02
12885 +           REL_20030701_HALdallas_cpsar_01.06.02
12886 +
12887 +Bug fixes: 1) A previous firmware upgrade caused firmware OAM loopback cells to only work on every other
12888 +              command.  This has been fixed in the new firmware version (0.47).
12889 +           2) Problem with PTI values changing on transparent mode packets has been resolved.
12890 +           3) Previously, successful firmware OAM loopback cells waited 5 seconds before notifying the
12891 +              OS of success, rather that notifying immediately.  This has been resolved in firmware.
12892 +           4) PITS #148 (MAC and SAR), #149 (MAC) have been fixed.
12893 +
12894 +New features: 1) AAL5 HAL now capable of receiving unknown VCI/VPI cells on a single transparent channel.
12895 +                 See updated HAL document (AAL5 appendix) for implementation details.
12896 +              2) AAL5 HAL now allows OS to modify the OAM loopback timeout window.  Previously, failed
12897 +                 OAM loopback attempts timed out after a nominal 5 seconds (based on the SAR frequency
12898 +                 provided by the OS).  Now, the default is 5 seconds, but the OS may change the
12899 +                 value via halControl() to any integer number of milliseconds.  See updated HAL document
12900 +                 (AAL5 appendix) for implementation details.
12901 +              3) MAC (cpmdio): added loopback to Istate.  Used for debug.
12902 +
12903 +Known issues not addressed in this release: NTR.
12904 +
12905 +09 June 2003         CPSAR 1.6.1 (external release), CPMAC 1.6.1 (internal release - no functional change)
12906 +
12907 +Note: This is the same set of fixes being applied to 1.6.0 that were applied to 1.5.3.  The only difference
12908 +      between 1.6.1 and 1.5.4 is that 1.6.1 has the TurboDSL fix.
12909 +
12910 +CC Labels: REL_20030609_HALdallas_cpmac_01.06.01
12911 +           REL_20030609_HALdallas_cpsar_01.06.01
12912 +
12913 +Bug fixes: 1) Bug in OamLoopbackConfig fixed.
12914 +           2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
12915 +              presence of OAM traffic when operating at or near line rate.
12916 +
12917 +New features: NTR.
12918 +
12919 +09 June 2003         CPSAR 1.5.4 (external release), CPMAC 1.5.4 (internal release - no functional change)
12920 +
12921 +Note:  This is a branch release from 1.5.3.  This does not contain anything from 1.6.0.  The CPMAC is
12922 +only being labeled to keep the release flow consistent.
12923 +
12924 +CC Labels: REL_20030609_HALdallas_cpmac_01.05.04
12925 +           REL_20030609_HALdallas_cpsar_01.05.04
12926 +
12927 +Bug fixes: 1) Bug in OamLoopbackConfig fixed.
12928 +           2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
12929 +              presence of OAM traffic when operating at or near line rate.
12930 +
12931 +New features: NTR.
12932 +
12933 +30 May 2003         CPSAR 1.6.0 (external release), CPMAC 1.6.0 (internal release - no functional change)
12934 +
12935 +CC Labels: REL_20030530_HALdallas_cpmac_01.06.00
12936 +           REL_20030530_HALdallas_cpsar_01.06.00
12937 +
12938 +Bug fixes: 1) TurboDSL issue has been fixed with a software workaround in TxInt.  This workaround
12939 +              has been verified under Adam2 ONLY at this point.  Testing remains to be done on
12940 +              Linux and VxWorks.
12941 +
12942 +New features: NTR.
12943 +
12944 +Known issues not addressed in this release: NTR.
12945 +
12946 +30 May 2003         CPSAR 1.5.3 (external release), CPMAC 1.5.3 (internal release - no functional change)
12947 +
12948 +CC Labels: REL_20030530_HALdallas_cpmac_01.05.03
12949 +           REL_20030530_HALdallas_cpsar_01.05.03
12950 +
12951 +Bug fixes: NTR.
12952 +
12953 +New features: 1) AAL5 Send() has been modified to accept an ATM Header either in the first
12954 +                 fragment by itself, or in the first fragment directly in front of payload data.
12955 +                 The API() does not change.
12956 +              2) Documentation updates throughout, reflected in latest version of CPHAL user's
12957 +                 guide.
12958 +              3) AAL5 MaxFrags default value is now 46.  This is based upon the default AAL5
12959 +                 RxBufSize of 1518 (MaxFrags = (65568/1518) + 2).  IF THE OS CHOOSES A SMALLER
12960 +                 RxBufSize, IT MUST INCREASE THE VALUE OF MaxFrags ACCORDINGLY.  This is done
12961 +                 via halControl(), prior to Open().
12962 +
12963 +Known issues not addressed in this release:
12964 +              1) The Linux SAR driver is seeing an issue in which it cannot
12965 +                 reliably send traffic simultaneously on both the high and
12966 +                 low priority queues of a single AAL5 channel. (TurboDSL)
12967 +
12968 +23 May 2003         CPHAL 1.5.2 (external release)
12969 +
12970 +CC Labels: REL_20030523_HALdallas_cpmac_01.05.02
12971 +           REL_20030523_HALdallas_cpsar_01.05.02
12972 +
12973 +Bug fixes: 1) PITS #138: CPMAC flooding issue resolved.
12974 +           2) PITS #142: OS may now set "MaxFrags" via Control().  This controls the
12975 +              maximum number of fragments expected by the CPHAL.  The default value is 2 for
12976 +              CPMAC and 1028 for AAL5.  If the OS chooses a RxBufSize that will cause more
12977 +              fragments than the defaults, the OS must set "MaxFrags" to a correct value
12978 +              ((maximum packet length / RxBufSize) + 2).
12979 +           3) PITS #143: Fixed.
12980 +           4) Firmware OAM bug fixed. (new firmware release in this version)
12981 +
12982 +New features: NTR.
12983 +
12984 +Known issues not addressed in this release:
12985 +              1) The Linux SAR driver is seeing an issue in which it cannot
12986 +                 reliably send traffic simultaneously on both the high and
12987 +                 low priority queues of a single AAL5 channel. (TurboDSL)
12988 +
12989 +14 May 2003         CPHAL 1.5.1 (external release)
12990 +
12991 +CC Labels: REL_20030514_HALdallas_cpmac_01.05.01
12992 +           REL_20030514_HALdallas_cpsar_01.05.01
12993 +
12994 +Bug fixes:    1) PITS 132 - (CPMAC) Frames < 60 bytes and split into
12995 +                             multi-fragments.
12996 +              2) BCIL MR PSP00000353 - (CPMAC) PhyDev not free'd on halClose()
12997 +              3) PITS 113 - OsSetup bug in ChannelSetup fixed.
12998 +              4) Fixed AAL5 to check return values of InitTcb/InitRcb.
12999 +              5) Fixed Shutdown to properly free resources in the case of a Close
13000 +                 mode 1 followed by Shutdown.  Previously, buffer and descriptor
13001 +                 resources were left unfreed in this case.
13002 +
13003 +New features: 1) AAL5 Send() modified to be capable of accepting ATM header as first four
13004 +                 bytes of first fragment.  This allows the OS to "override" the
13005 +                 default ATM header which is constructed from preconfigured channel
13006 +                 parameters.
13007 +              2) AAL5 Receive() modified to be capable of passing the received ATM header (4 bytes, no HEC)
13008 +                 in the first fragment (by itself).  It also passes up the OS an indication
13009 +                 of what the received packet type was.  For Host OAM and transparent mode
13010 +                 packets, the ATM header is passed in this manner, and for other types of packets
13011 +                 (AAL5, NULL AAL) no ATM header is passed currently.
13012 +
13013 +Known issues not addressed in this release:
13014 +              1) The Linux SAR driver is seeing an issue in which it cannot
13015 +                 reliably send traffic simultaneously on both the high and
13016 +                 low priority queues of a single AAL5 channel.
13017 +
13018 +30 April 2003         CPHAL 1.5.0 (external release)
13019 +
13020 +CC Labels: REL_20030430_HALdallas_cpmac_01.05.00
13021 +           REL_20030430_HALdallas_cpsar_01.05.00
13022 +
13023 +Bug fixes:   1) Fixed AAL5 bug that rendered the low priority queue
13024 +                unusable.
13025 +             2) Fixed a bug in AAL5's Oam Rate calculations.
13026 +             3) Fixed use of "DeviceCPID" key in AAL5's halControl().
13027 +             4) Fixed RxReturn logic in HAL.  The HAL now can handle
13028 +                failing MallocRxBuffer calls when multiple fragments
13029 +                are being used.
13030 +
13031 +New features: 1) AAL5 Stats now available on a per queue basis.
13032 +              2) AAL5 adds two new keys to halControl() for "Set" actions:
13033 +                 RxVc_OamCh and RxVp_OamCh.
13034 +              3) Shutdown() has been modified for both AAL5 and CPMAC to
13035 +                 call Close() if the module is still in the Open state.
13036 +              4) CPMAC adds the following access keys to halControl():
13037 +                 hcPhyAccess,hcPhyNum,hcCpmacBase,hcSize,and hcCpmacSize.
13038 +              5) CPHAL no longer requests an extra 15 bytes on data buffer
13039 +                 mallocs.
13040 +
13041 +Known issues not addressed in this release:
13042 +              1) The Linux SAR driver is seeing an issue in which it cannot
13043 +                 reliably send traffic simultaneously on both the high and
13044 +                 low priority queues of a single AAL5 channel.
13045 +
13046 +21 April 2003         CPHAL 1.4.1 (external release)
13047 +
13048 +CC Labels: REL_20030421_HALdallas_cpmac_01.04.01
13049 +           REL_20030421_HALdallas_cpsar_01.04.01
13050 +
13051 +Bug fixes:   1) Fixed OAM logic in SAR portion of CPHAL.
13052 +
13053 +New features: 1) OAM loopback counters exposed through halControl.
13054 +              2) Host OAM Send() can now use a single channel to send
13055 +                 OAM cells on unlimited number of VP's/VC's.
13056 +              3) CPHAL now requests "SarFreq" through osControl.
13057 +              4) CPHAL now calculates all OAM function rates based on
13058 +                 "SarFreq"; function OamRateConfig removed for API.
13059 +              5) New OAM function OamLoopbackConfig, used for configuring
13060 +                 loopback functions in firmware OAM mode.
13061 +
13062 +Known issues not addressed in this release:  Bug fix 1) in release 1.4
13063 +             (see below) does not work properly for multiple fragments.
13064 +
13065 +10 April 2003         CPHAL 1.4 (external release)
13066 +
13067 +CC Labels: REL_20030410_HALdallas_cpmac_01.04.00
13068 +           REL_20030410_HALdallas_cpsar_01.04.00
13069 +
13070 +This release is for SAR and MAC.
13071 +
13072 +  Bug fixes: 1) Implemented logic in HAL to re-request buffer mallocs
13073 +                in the case of MallocRxBuffer failing.  The HAL now maintains
13074 +                a NeedsBuffer queue of all RCB's that are without buffers.
13075 +                On interrupts, or on Send(), the HAL checks to see if any
13076 +                RCB's are on the queue, and if so, calls MallocRxBuffer
13077 +                to attempt to get a new buffer and return the RCB to
13078 +                circulation.
13079 +             2) SAR now properly returns all error codes from halOpen and
13080 +                halChannelSetup.
13081 +
13082 +  New features: NTR
13083 +
13084 +  Known issues not addressed in this release: NTR
13085 +
13086 +08 April 2003         CPHAL 1.3.1 (internal release - SAR only)
13087 +
13088 +  CC Labels: REL_20030408_HALdallas_cpsar_01.03.01
13089 +
13090 +  This is a SAR only release.  The current CPMAC release is still 1.3.
13091 +
13092 +  Bug fixes: 1) PDSP State RAM / Scratchpad RAM is now completely cleared after reset.
13093 +                This resolves a stability issue.
13094 +
13095 +  New features: 1) OamMode is now a parameter in halControl().  Both "Set" and "Get"
13096 +                   actions are available.  The value may be "0" (Host OAM), or "1"
13097 +                   (Firmware OAM).
13098 +
13099 +  Known issues not addressed in this release:
13100 +             1) Appropriate action for HAL in the case of MallocRxBuffer failing.  We
13101 +                are investigating whether the HAL should implement a needs buffer
13102 +                queue.
13103 +
13104 +04 April 2003         CPHAL 1.3 (external release)
13105 +
13106 +  CC Labels: REL_20030404_HALdallas_cpmac_01.03.00
13107 +             REL_20030404_HALdallas_cpsar_01.03.00
13108 +             REL_20030404_HALdallas_cpaal5_01.03.00
13109 +             REL_20030404_HALdallas_cpaal2_01.03.00
13110 +
13111 +  This release requires no changes for the ethernet end driver.  The changes necessary
13112 +  for the sar driver (firmware file name changes) have already been implemented.
13113 +
13114 +  Bug fixes: 1) RxReturn now returns an error if MallocRxBuffer fails.  On RxReturn error, the driver should
13115 +                call RxReturn again at a later time (when the malloc may succeed) in order for the CPHAL
13116 +                to maintain a full complement of Rx buffers.  We recommend holding off making this driver
13117 +                change until we verify that this condition occurs.
13118 +
13119 +  New features: 1) Removed benign compiler warnings.
13120 +                2) PITS 122: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=122
13121 +                3) Cpsar label (above) now is applied to everything
13122 +                   beneath /cpsar.
13123 +                4) PITS 14: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=14
13124 +                   Transferred to MR PSP 00000089.
13125 +                5) PITS 120: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=120
13126 +
13127 +  Known issues not addressed in this release:
13128 +             1) PITS 102 (as relating to OamMode configuration):
13129 +                http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=102
13130 +                Future release will make OamMode configurable
13131 +                through halControl(), not on per channel basis.
13132 +
13133 +20 March 2003         CPHAL 1.2.1 (internal release)
13134 +
13135 +  CC Labels: REL_20030320_HALdallas_cpmac_01.02.01
13136 +             REL_20030320_HALdallas_cpsar_01.02.01
13137 +             REL_20030320_HALdallas_cpaal5_01.02.01
13138 +             REL_20030320_HALdallas_cpaal2_01.02.01
13139 +
13140 +  Bug fixes: 1. Fixed modification of buffer pointer following
13141 +                MallocRxBuffer in cppi.c.
13142 +             2. Removed extra firmware files from /cpsar.
13143 +
13144 +  New features: NTR.
13145 +
13146 +  Known issues not addressed in this release: NTR.
13147 +
13148 +07 March 2003         CPHAL 1.2 (external release)
13149 +
13150 +  CPMAC/CPSAR feature complete release.  SAR added
13151 +  several features including full OAM support and various
13152 +  other features and bug fixes to address PITS 99-106, and
13153 +  114.  CPMAC cleaned up details raised by India PSP
13154 +  team.
13155 +
13156 +29 January 2003       CPHAL RC 3.01a (external release)
13157 +
13158 +  Corrects non-static functions to be static in cppi.c.
13159 +
13160 +09 Janurary 2003      CPHAL RC 3.01 (external release)
13161 +
13162 +  PITS 88: Fixed MDIO re-connection problem (hcpmac.c)
13163 +  PITS 90: Corrected Rx Buffer Pointer modification (cppi.c)
13164 +
13165 +  Corrected error in cpremap.c
13166 +
13167 +20 December 2002      CPHAL RC 3 (external release)
13168 +
13169 +  Statistics support via halControl().  See Appendix A of guide.
13170 +  Fixed errors in ChannelTeardown/ChannelSetup CPHAL logic.
13171 +  Added multicast support as requested.
13172 +  Several new OS string functions added to OS_FUNCTIONS.
13173 +  "DebugLevel" configuration parameter changed to "Debug".
13174 +  "Stats0" changed to "StatsDump" for CPMAC.
13175 +
13176 +13 December 2002      CPHAL RC 2.03 (internal release)
13177 +
13178 +  Performance improvements.
13179 +  More debug statements implemented (esp AAL5).
13180 +  Updated makefile with "make debug" option.
13181 +  Hbridge performance: [debug library] 15774 tps (53% line rate)
13182 +                   [non-debug library] 13700 tps (46%)
13183 +
13184 +10 December 2002      CPHAL Release Candidate 2.02 (internal release)
13185 +
13186 + Much of the configuration code internal to CPMAC and AAL5 has been made common.
13187 + [os]Receive API had been modified to remove OsReceiveInfo.  This information is now
13188 +   available as third member of the FRAGLIST structure, on a per buffer basis.
13189 + Successfully tested multi-fragment support on CPMAC, using 32 byte buffers.
13190 + Code is now Emerald compliant - all buffer descriptors now aligned to cache-line
13191 +   boundaries.
13192 +
13193 +2 December 2002      CPHAL Release Candidate 2.01
13194 +
13195 + Updates to comments in hcpmac.c, cpmdio.c, hcpmac.h
13196 + Nested comment in hcpmac.c in RC2 can cause compile errors.
13197 +
13198 +25 November 2002      CPHAL Release Candidate 2
13199 +
13200 +Project Items not completed for RC2
13201 +#6  Ship as Library -  Once under CC. Moved to RC3
13202 +#8  Under Clearcase -  Moved to RC3
13203 +#25 Emerald compliant - Moved to RC3
13204 +#26 Statistics support - Moved to RC3 (some support in RC2)
13205 +#36 Debug scheme implemented - Moved to RC3 (some support in RC2)
13206 +
13207 +8 November 2002       CPHAL Release Candidate 1
13208 +
13209 +Notes:
13210 +
13211 +Project Items not completed for RC1
13212 +
13213 +#8  Under Clearcase -  Clearcase server failure this week. Moved to RC2
13214 +#6  Ship as Library -  Once under CC. Moved to RC2
13215 +#13 Verify Datatypes. Moved to RC2
13216 +#14 Review APIs.  Moved to RC2
13217 +
13218 +APIs under review for RC2
13219 +
13220 +halIsr()
13221 +hslRxReturn()
13222 +halSend()
13223 +osSendComplete()
13224 +osReceive()
13225 +
13226 +
13227 +CPMAC Build Instructions
13228 +
13229 +Compile the file 'hcpmac.c'.
13230 +
13231 +
13232 +AAL5 Build Instructions
13233 +
13234 +The AAL5 build is composed of the source files aal5sar.c and cpsar.c.
13235 +Refer to the provided makefile for an example of compiling these files
13236 +into a library.
13237 +
13238 +Example CPHAL Code
13239 +
13240 +CPMAC:
13241 +
13242 +Example CPMAC code is provided in the file hbridge.c.
13243 +This program is provided simply as an example of using the CPHAL API.
13244 +It is not intended to be compiled and executed in your environment.
13245 +
13246 +AAL5:
13247 +
13248 +Example AAL5 code is provided in the file loopback.c.  This program
13249 +is provided simply as an example of using the CPHAL API.  It is not
13250 +intended to be compiled and executed in your environment.
13251 +
13252 +
13253 +Performance Baseline
13254 +
13255 +
13256 +Cpmac
13257 +
13258 +RC1: hbridge.bin, running with IXIA cpahl_1.cfg.
13259 +     This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13260 +     MIPS core 4Kc.
13261 +
13262 +RC2: hbridge.bin, running with IXIA cpahl_1.cfg.
13263 +     This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13264 +     MIPS core 4Ke.
13265 +     CPHAL now includes Emerald support, but this has been disabled by using 'cache -wt' to emulate 4Kc.
13266 +
13267 +RC3: hbridge.bin, running with IXIA cpahl_1.cfg.
13268 +     This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13269 +     MIPS core 4Ke.
13270 +     Running as Emerald processor.
13271 +
13272 +Release  Total Receive Rate    Throughput Setting
13273 +
13274 +RC1             11300                 38%
13275 +RC2              9524                 32%
13276 +RC3             15190                 51%
13277 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
13278 --- linux.old/drivers/net/Config.in     2005-07-12 03:20:45.726149872 +0200
13279 +++ linux.dev/drivers/net/Config.in     2005-07-12 02:48:42.180573000 +0200
13280 @@ -25,6 +25,24 @@
13281  comment 'Ethernet (10 or 100Mbit)'
13282  bool 'Ethernet (10 or 100Mbit)' CONFIG_NET_ETHERNET
13283  if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
13284 +   if [ "$CONFIG_MIPS_TITAN" = "y" -o "$CONFIG_AR7" = "y" ]; then
13285 +        tristate '  Texas Instruments Avalanche CPMAC support' CONFIG_MIPS_AVALANCHE_CPMAC
13286 +   fi
13287 +   if [ "$CONFIG_MIPS_AVALANCHE_CPMAC" != "n" ]; then
13288 +     if [ "$CONFIG_AR7WRD" = "y" -o "$CONFIG_AR7VWI" = "y" -o "$CONFIG_AR7VW" = "y" ]; then
13289 +        define_bool  CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC y
13290 +         define_int CONFIG_MIPS_CPMAC_PORTS 1
13291 +        if [ "$CONFIG_MIPS_AVALANCHE_MARVELL" = "y" ]; then
13292 +             define_bool CONFIG_AVALANCHE_LOW_CPMAC  n
13293 +             define_bool CONFIG_AVALANCHE_HIGH_CPMAC y
13294 +        else
13295 +             define_bool CONFIG_AVALANCHE_CPMAC_AUTO y
13296 +             define_bool CONFIG_AVALANCHE_LOW_CPMAC n
13297 +             define_bool CONFIG_AVALANCHE_HIGH_CPMAC n
13298 +       fi
13299 +     fi
13300 +   fi
13301 +
13302     if [ "$CONFIG_ARM" = "y" ]; then
13303        dep_bool '  ARM EBSA110 AM79C961A support' CONFIG_ARM_AM79C961A $CONFIG_ARCH_EBSA110
13304        tristate '  Cirrus Logic CS8900A support' CONFIG_ARM_CIRRUS
13305 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
13306 --- linux.old/drivers/net/Makefile      2005-07-12 03:20:45.726149872 +0200
13307 +++ linux.dev/drivers/net/Makefile      2005-07-12 02:48:42.181573000 +0200
13308 @@ -56,6 +56,16 @@
13309  subdir-$(CONFIG_BONDING) += bonding
13310
13311  #
13312 +# Texas Instruments AVALANCHE CPMAC  driver
13313 +#
13314 +
13315 +subdir-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac
13316 +#obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac/avalanche_cpmac.o
13317 +ifeq ($(CONFIG_MIPS_AVALANCHE_CPMAC),y)
13318 +  obj-y += avalanche_cpmac/avalanche_cpmac.o
13319 +endif
13320 +
13321 +#
13322  # link order important here
13323  #
13324  obj-$(CONFIG_PLIP) += plip.o