Moved initialization of NATSEMI Ethernet controller to board_eth_init()
[oweals/u-boot.git] / nand_spl / nand_boot.c
1 /*
2  * (C) Copyright 2006-2008
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20
21 #include <common.h>
22 #include <nand.h>
23 #include <asm/io.h>
24
25 #define CFG_NAND_READ_DELAY \
26         { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
27
28 static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
29
30 extern void board_nand_init(struct nand_chip *nand);
31
32 #if (CFG_NAND_PAGE_SIZE <= 512)
33 /*
34  * NAND command for small page NAND devices (512)
35  */
36 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
37 {
38         struct nand_chip *this = mtd->priv;
39         int page_addr = page + block * CFG_NAND_PAGE_COUNT;
40
41         if (this->dev_ready)
42                 while (!this->dev_ready(mtd))
43                         ;
44         else
45                 CFG_NAND_READ_DELAY;
46
47         /* Begin command latch cycle */
48         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
49         /* Set ALE and clear CLE to start address cycle */
50         /* Column address */
51         this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
52         this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */
53         this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */
54 #ifdef CFG_NAND_4_ADDR_CYCLE
55         /* One more address cycle for devices > 32MiB */
56         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
57 #endif
58         /* Latch in address */
59         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60
61         /*
62          * Wait a while for the data to be ready
63          */
64         if (this->dev_ready)
65                 while (!this->dev_ready(mtd))
66                         ;
67         else
68                 CFG_NAND_READ_DELAY;
69
70         return 0;
71 }
72 #else
73 /*
74  * NAND command for large page NAND devices (2k)
75  */
76 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
77 {
78         struct nand_chip *this = mtd->priv;
79         int page_addr = page + block * CFG_NAND_PAGE_COUNT;
80
81         if (this->dev_ready)
82                 while (!this->dev_ready(mtd))
83                         ;
84         else
85                 CFG_NAND_READ_DELAY;
86
87         /* Emulate NAND_CMD_READOOB */
88         if (cmd == NAND_CMD_READOOB) {
89                 offs += CFG_NAND_PAGE_SIZE;
90                 cmd = NAND_CMD_READ0;
91         }
92
93         /* Begin command latch cycle */
94         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
95         /* Set ALE and clear CLE to start address cycle */
96         /* Column address */
97         this->cmd_ctrl(mtd, offs & 0xff,
98                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
99         this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
100         /* Row address */
101         this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
102         this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
103 #ifdef CFG_NAND_5_ADDR_CYCLE
104         /* One more address cycle for devices > 128MiB */
105         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */
106 #endif
107         /* Latch in address */
108         this->cmd_ctrl(mtd, NAND_CMD_READSTART,
109                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
110         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
111
112         /*
113          * Wait a while for the data to be ready
114          */
115         if (this->dev_ready)
116                 while (!this->dev_ready(mtd))
117                         ;
118         else
119                 CFG_NAND_READ_DELAY;
120
121         return 0;
122 }
123 #endif
124
125 static int nand_is_bad_block(struct mtd_info *mtd, int block)
126 {
127         struct nand_chip *this = mtd->priv;
128
129         nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
130
131         /*
132          * Read one byte
133          */
134         if (readb(this->IO_ADDR_R) != 0xff)
135                 return 1;
136
137         return 0;
138 }
139
140 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
141 {
142         struct nand_chip *this = mtd->priv;
143         u_char *ecc_calc;
144         u_char *ecc_code;
145         u_char *oob_data;
146         int i;
147         int eccsize = CFG_NAND_ECCSIZE;
148         int eccbytes = CFG_NAND_ECCBYTES;
149         int eccsteps = CFG_NAND_ECCSTEPS;
150         uint8_t *p = dst;
151         int stat;
152
153         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
154
155         /* No malloc available for now, just use some temporary locations
156          * in SDRAM
157          */
158         ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
159         ecc_code = ecc_calc + 0x100;
160         oob_data = ecc_calc + 0x200;
161
162         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
163                 this->ecc.hwctl(mtd, NAND_ECC_READ);
164                 this->read_buf(mtd, p, eccsize);
165                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
166         }
167         this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
168
169         /* Pick the ECC bytes out of the oob data */
170         for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
171                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
172
173         eccsteps = CFG_NAND_ECCSTEPS;
174         p = dst;
175
176         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
177                 /* No chance to do something with the possible error message
178                  * from correct_data(). We just hope that all possible errors
179                  * are corrected by this routine.
180                  */
181                 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
182         }
183
184         return 0;
185 }
186
187 static int nand_load(struct mtd_info *mtd, unsigned int offs,
188                      unsigned int uboot_size, uchar *dst)
189 {
190         unsigned int block, lastblock;
191         unsigned int page;
192
193         /*
194          * offs has to be aligned to a page address!
195          */
196         block = offs / CFG_NAND_BLOCK_SIZE;
197         lastblock = (offs + uboot_size - 1) / CFG_NAND_BLOCK_SIZE;
198         page = (offs % CFG_NAND_BLOCK_SIZE) / CFG_NAND_PAGE_SIZE;
199
200         while (block <= lastblock) {
201                 if (!nand_is_bad_block(mtd, block)) {
202                         /*
203                          * Skip bad blocks
204                          */
205                         while (page < CFG_NAND_PAGE_COUNT) {
206                                 nand_read_page(mtd, block, page, dst);
207                                 dst += CFG_NAND_PAGE_SIZE;
208                                 page++;
209                         }
210
211                         page = 0;
212                 } else {
213                         lastblock++;
214                 }
215
216                 block++;
217         }
218
219         return 0;
220 }
221
222 /*
223  * The main entry for NAND booting. It's necessary that SDRAM is already
224  * configured and available since this code loads the main U-Boot image
225  * from NAND into SDRAM and starts it from there.
226  */
227 void nand_boot(void)
228 {
229         struct nand_chip nand_chip;
230         nand_info_t nand_info;
231         int ret;
232         __attribute__((noreturn)) void (*uboot)(void);
233
234         /*
235          * Init board specific nand support
236          */
237         nand_info.priv = &nand_chip;
238         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CFG_NAND_BASE;
239         nand_chip.dev_ready = NULL;     /* preset to NULL */
240         board_nand_init(&nand_chip);
241
242         if (nand_chip.select_chip)
243                 nand_chip.select_chip(&nand_info, 0);
244
245         /*
246          * Load U-Boot image from NAND into RAM
247          */
248         ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
249                         (uchar *)CFG_NAND_U_BOOT_DST);
250
251         if (nand_chip.select_chip)
252                 nand_chip.select_chip(&nand_info, -1);
253
254         /*
255          * Jump to U-Boot image
256          */
257         uboot = (void *)CFG_NAND_U_BOOT_START;
258         (*uboot)();
259 }