3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 static void wait_init_complete(void)
34 mfsdram(SDRAM_MCSTAT, val);
35 } while (!(val & 0x80000000));
38 long int initdram(int board_type)
41 * Reset the DDR-SDRAM controller.
43 mtsdr(SDR0_SRST, (0x80000000 >> 10));
44 mtsdr(SDR0_SRST, 0x00000000);
47 * These values are cloned from a running NOR booting
48 * Canyonlands with SPD-DDR2 detection and calibration
49 * enabled. This will only work for the same memory
50 * configuration as used here:
52 * Crucial CT6464AC53E.4FE - 512MB SO-DIMM
55 mtsdram(SDRAM_MCOPT2, 0x00000000);
56 mtsdram(SDRAM_MCOPT1, 0x05322000);
57 mtsdram(SDRAM_MODT0, 0x01000000);
58 mtsdram(SDRAM_CODT, 0x00800021);
59 mtsdram(SDRAM_WRDTR, 0x82000823);
60 mtsdram(SDRAM_CLKTR, 0x40000000);
61 mtsdram(SDRAM_MB0CF, 0x00000201);
62 mtsdram(SDRAM_RTR, 0x06180000);
63 mtsdram(SDRAM_SDTR1, 0x80201000);
64 mtsdram(SDRAM_SDTR2, 0x42103243);
65 mtsdram(SDRAM_SDTR3, 0x0A0D0D1A);
66 mtsdram(SDRAM_MMODE, 0x00000632);
67 mtsdram(SDRAM_MEMODE, 0x00000040);
68 mtsdram(SDRAM_INITPLR0, 0xB5380000);
69 mtsdram(SDRAM_INITPLR1, 0x82100400);
70 mtsdram(SDRAM_INITPLR2, 0x80820000);
71 mtsdram(SDRAM_INITPLR3, 0x80830000);
72 mtsdram(SDRAM_INITPLR4, 0x80810040);
73 mtsdram(SDRAM_INITPLR5, 0x80800532);
74 mtsdram(SDRAM_INITPLR6, 0x82100400);
75 mtsdram(SDRAM_INITPLR7, 0x8A080000);
76 mtsdram(SDRAM_INITPLR8, 0x8A080000);
77 mtsdram(SDRAM_INITPLR9, 0x8A080000);
78 mtsdram(SDRAM_INITPLR10, 0x8A080000);
79 mtsdram(SDRAM_INITPLR11, 0x80000432);
80 mtsdram(SDRAM_INITPLR12, 0x808103C0);
81 mtsdram(SDRAM_INITPLR13, 0x80810040);
82 mtsdram(SDRAM_INITPLR14, 0x00000000);
83 mtsdram(SDRAM_INITPLR15, 0x00000000);
85 mtsdram(SDRAM_MCOPT2, 0x28000000);
89 mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */
91 mtsdram(SDRAM_RDCC, 0x40000000);
92 mtsdram(SDRAM_RQDC, 0x80000038);
93 mtsdram(SDRAM_RFDC, 0x00000257);
95 return CFG_MBYTES_SDRAM << 20;