2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
5 * Joe Hershberger <joe.hershberger@ni.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #if defined(CONFIG_FPGA_ZYNQPL)
16 extern struct xilinx_fpga_op zynq_op;
17 # define FPGA_ZYNQPL_OPS &zynq_op
19 # define FPGA_ZYNQPL_OPS NULL
22 #define XILINX_ZYNQ_7010 0x2
23 #define XILINX_ZYNQ_7015 0x1b
24 #define XILINX_ZYNQ_7020 0x7
25 #define XILINX_ZYNQ_7030 0xc
26 #define XILINX_ZYNQ_7045 0x11
27 #define XILINX_ZYNQ_7100 0x16
29 /* Device Image Sizes */
30 #define XILINX_XC7Z010_SIZE 16669920/8
31 #define XILINX_XC7Z015_SIZE 28085344/8
32 #define XILINX_XC7Z020_SIZE 32364512/8
33 #define XILINX_XC7Z030_SIZE 47839328/8
34 #define XILINX_XC7Z045_SIZE 106571232/8
35 #define XILINX_XC7Z100_SIZE 139330784/8
37 /* Descriptor Macros */
38 #define XILINX_XC7Z010_DESC(cookie) \
39 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
42 #define XILINX_XC7Z015_DESC(cookie) \
43 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
46 #define XILINX_XC7Z020_DESC(cookie) \
47 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
50 #define XILINX_XC7Z030_DESC(cookie) \
51 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
54 #define XILINX_XC7Z045_DESC(cookie) \
55 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
58 #define XILINX_XC7Z100_DESC(cookie) \
59 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
62 #endif /* _ZYNQPL_H_ */