1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
7 #include <linux/types.h>
12 /* Descriptor flags */
13 #define IDXD_OP_FLAG_FENCE 0x0001
14 #define IDXD_OP_FLAG_BOF 0x0002
15 #define IDXD_OP_FLAG_CRAV 0x0004
16 #define IDXD_OP_FLAG_RCR 0x0008
17 #define IDXD_OP_FLAG_RCI 0x0010
18 #define IDXD_OP_FLAG_CRSTS 0x0020
19 #define IDXD_OP_FLAG_CR 0x0080
20 #define IDXD_OP_FLAG_CC 0x0100
21 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200
22 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400
23 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800
24 #define IDXD_OP_FLAG_CR_TCS 0x1000
25 #define IDXD_OP_FLAG_STORD 0x2000
26 #define IDXD_OP_FLAG_DRDBK 0x4000
27 #define IDXD_OP_FLAG_DSTS 0x8000
41 DSA_OPCODE_CRCGEN = 0x10,
47 DSA_OPCODE_CFLUSH = 0x20,
50 /* Completion record status */
51 enum dsa_completion_status {
54 DSA_COMP_SUCCESS_PRED,
55 DSA_COMP_PAGE_FAULT_NOBOF,
56 DSA_COMP_PAGE_FAULT_IR,
58 DSA_COMP_BATCH_PAGE_FAULT,
59 DSA_COMP_DR_OFFSET_NOINC,
60 DSA_COMP_DR_OFFSET_ERANGE,
62 DSA_COMP_BAD_OPCODE = 0x10,
63 DSA_COMP_INVALID_FLAGS,
64 DSA_COMP_NOZERO_RESERVE,
66 DSA_COMP_DESC_CNT_ERANGE,
68 DSA_COMP_OVERLAP_BUFFERS,
70 DSA_COMP_DESCLIST_ALIGN,
71 DSA_COMP_INT_HANDLE_INVAL,
76 DSA_COMP_TRAFFIC_CLASS_CONF,
80 DSA_COMP_TRANSLATION_FAIL,
83 #define DSA_COMP_STATUS_MASK 0x7f
84 #define DSA_COMP_STATUS_WRITE 0x80
92 uint64_t completion_addr;
97 uint64_t desc_list_addr;
101 uint64_t rdback_addr2;
103 uint64_t comp_pattern;
112 uint8_t expected_res;
115 uint32_t max_delta_size;
117 uint32_t delta_rec_size;
125 /* DIF check or strip */
127 uint8_t src_dif_flags;
129 uint8_t dif_chk_flags;
130 uint8_t dif_chk_res2[5];
131 uint32_t chk_ref_tag_seed;
132 uint16_t chk_app_tag_mask;
133 uint16_t chk_app_tag_seed;
138 uint8_t dest_dif_flag;
139 uint8_t dif_ins_flags;
140 uint8_t dif_ins_res2[13];
141 uint32_t ins_ref_tag_seed;
142 uint16_t ins_app_tag_mask;
143 uint16_t ins_app_tag_seed;
147 uint8_t src_upd_flags;
148 uint8_t upd_dest_flags;
149 uint8_t dif_upd_flags;
150 uint8_t dif_upd_res[5];
151 uint32_t src_ref_tag_seed;
152 uint16_t src_app_tag_mask;
153 uint16_t src_app_tag_seed;
154 uint32_t dest_ref_tag_seed;
155 uint16_t dest_app_tag_mask;
156 uint16_t dest_app_tag_seed;
159 uint8_t op_specific[24];
161 } __attribute__((packed));
163 struct dsa_raw_desc {
165 } __attribute__((packed));
168 * The status field will be modified by hardware, therefore it should be
169 * volatile and prevent the compiler from optimize the read.
171 struct dsa_completion_record {
172 volatile uint8_t status;
178 uint32_t bytes_completed;
181 uint16_t delta_rec_size;
184 /* DIF check & strip */
186 uint32_t dif_chk_ref_tag;
187 uint16_t dif_chk_app_tag_mask;
188 uint16_t dif_chk_app_tag;
193 uint64_t dif_ins_res;
194 uint32_t dif_ins_ref_tag;
195 uint16_t dif_ins_app_tag_mask;
196 uint16_t dif_ins_app_tag;
201 uint32_t dif_upd_src_ref_tag;
202 uint16_t dif_upd_src_app_tag_mask;
203 uint16_t dif_upd_src_app_tag;
204 uint32_t dif_upd_dest_ref_tag;
205 uint16_t dif_upd_dest_app_tag_mask;
206 uint16_t dif_upd_dest_app_tag;
209 uint8_t op_specific[16];
211 } __attribute__((packed));
213 struct dsa_raw_completion_record {
215 } __attribute__((packed));