Linux-libre 5.7.3-gnu
[librecmc/linux-libre.git] / include / uapi / linux / idxd.h
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #ifndef _USR_IDXD_H_
4 #define _USR_IDXD_H_
5
6 #ifdef __KERNEL__
7 #include <linux/types.h>
8 #else
9 #include <stdint.h>
10 #endif
11
12 /* Descriptor flags */
13 #define IDXD_OP_FLAG_FENCE      0x0001
14 #define IDXD_OP_FLAG_BOF        0x0002
15 #define IDXD_OP_FLAG_CRAV       0x0004
16 #define IDXD_OP_FLAG_RCR        0x0008
17 #define IDXD_OP_FLAG_RCI        0x0010
18 #define IDXD_OP_FLAG_CRSTS      0x0020
19 #define IDXD_OP_FLAG_CR         0x0080
20 #define IDXD_OP_FLAG_CC         0x0100
21 #define IDXD_OP_FLAG_ADDR1_TCS  0x0200
22 #define IDXD_OP_FLAG_ADDR2_TCS  0x0400
23 #define IDXD_OP_FLAG_ADDR3_TCS  0x0800
24 #define IDXD_OP_FLAG_CR_TCS     0x1000
25 #define IDXD_OP_FLAG_STORD      0x2000
26 #define IDXD_OP_FLAG_DRDBK      0x4000
27 #define IDXD_OP_FLAG_DSTS       0x8000
28
29 /* Opcode */
30 enum dsa_opcode {
31         DSA_OPCODE_NOOP = 0,
32         DSA_OPCODE_BATCH,
33         DSA_OPCODE_DRAIN,
34         DSA_OPCODE_MEMMOVE,
35         DSA_OPCODE_MEMFILL,
36         DSA_OPCODE_COMPARE,
37         DSA_OPCODE_COMPVAL,
38         DSA_OPCODE_CR_DELTA,
39         DSA_OPCODE_AP_DELTA,
40         DSA_OPCODE_DUALCAST,
41         DSA_OPCODE_CRCGEN = 0x10,
42         DSA_OPCODE_COPY_CRC,
43         DSA_OPCODE_DIF_CHECK,
44         DSA_OPCODE_DIF_INS,
45         DSA_OPCODE_DIF_STRP,
46         DSA_OPCODE_DIF_UPDT,
47         DSA_OPCODE_CFLUSH = 0x20,
48 };
49
50 /* Completion record status */
51 enum dsa_completion_status {
52         DSA_COMP_NONE = 0,
53         DSA_COMP_SUCCESS,
54         DSA_COMP_SUCCESS_PRED,
55         DSA_COMP_PAGE_FAULT_NOBOF,
56         DSA_COMP_PAGE_FAULT_IR,
57         DSA_COMP_BATCH_FAIL,
58         DSA_COMP_BATCH_PAGE_FAULT,
59         DSA_COMP_DR_OFFSET_NOINC,
60         DSA_COMP_DR_OFFSET_ERANGE,
61         DSA_COMP_DIF_ERR,
62         DSA_COMP_BAD_OPCODE = 0x10,
63         DSA_COMP_INVALID_FLAGS,
64         DSA_COMP_NOZERO_RESERVE,
65         DSA_COMP_XFER_ERANGE,
66         DSA_COMP_DESC_CNT_ERANGE,
67         DSA_COMP_DR_ERANGE,
68         DSA_COMP_OVERLAP_BUFFERS,
69         DSA_COMP_DCAST_ERR,
70         DSA_COMP_DESCLIST_ALIGN,
71         DSA_COMP_INT_HANDLE_INVAL,
72         DSA_COMP_CRA_XLAT,
73         DSA_COMP_CRA_ALIGN,
74         DSA_COMP_ADDR_ALIGN,
75         DSA_COMP_PRIV_BAD,
76         DSA_COMP_TRAFFIC_CLASS_CONF,
77         DSA_COMP_PFAULT_RDBA,
78         DSA_COMP_HW_ERR1,
79         DSA_COMP_HW_ERR_DRB,
80         DSA_COMP_TRANSLATION_FAIL,
81 };
82
83 #define DSA_COMP_STATUS_MASK            0x7f
84 #define DSA_COMP_STATUS_WRITE           0x80
85
86 struct dsa_hw_desc {
87         uint32_t        pasid:20;
88         uint32_t        rsvd:11;
89         uint32_t        priv:1;
90         uint32_t        flags:24;
91         uint32_t        opcode:8;
92         uint64_t        completion_addr;
93         union {
94                 uint64_t        src_addr;
95                 uint64_t        rdback_addr;
96                 uint64_t        pattern;
97                 uint64_t        desc_list_addr;
98         };
99         union {
100                 uint64_t        dst_addr;
101                 uint64_t        rdback_addr2;
102                 uint64_t        src2_addr;
103                 uint64_t        comp_pattern;
104         };
105         union {
106                 uint32_t        xfer_size;
107                 uint32_t        desc_count;
108         };
109         uint16_t        int_handle;
110         uint16_t        rsvd1;
111         union {
112                 uint8_t         expected_res;
113                 struct {
114                         uint64_t        delta_addr;
115                         uint32_t        max_delta_size;
116                 };
117                 uint32_t        delta_rec_size;
118                 uint64_t        dest2;
119                 /* CRC */
120                 struct {
121                         uint32_t        crc_seed;
122                         uint32_t        crc_rsvd;
123                         uint64_t        seed_addr;
124                 };
125                 /* DIF check or strip */
126                 struct {
127                         uint8_t         src_dif_flags;
128                         uint8_t         dif_chk_res;
129                         uint8_t         dif_chk_flags;
130                         uint8_t         dif_chk_res2[5];
131                         uint32_t        chk_ref_tag_seed;
132                         uint16_t        chk_app_tag_mask;
133                         uint16_t        chk_app_tag_seed;
134                 };
135                 /* DIF insert */
136                 struct {
137                         uint8_t         dif_ins_res;
138                         uint8_t         dest_dif_flag;
139                         uint8_t         dif_ins_flags;
140                         uint8_t         dif_ins_res2[13];
141                         uint32_t        ins_ref_tag_seed;
142                         uint16_t        ins_app_tag_mask;
143                         uint16_t        ins_app_tag_seed;
144                 };
145                 /* DIF update */
146                 struct {
147                         uint8_t         src_upd_flags;
148                         uint8_t         upd_dest_flags;
149                         uint8_t         dif_upd_flags;
150                         uint8_t         dif_upd_res[5];
151                         uint32_t        src_ref_tag_seed;
152                         uint16_t        src_app_tag_mask;
153                         uint16_t        src_app_tag_seed;
154                         uint32_t        dest_ref_tag_seed;
155                         uint16_t        dest_app_tag_mask;
156                         uint16_t        dest_app_tag_seed;
157                 };
158
159                 uint8_t         op_specific[24];
160         };
161 } __attribute__((packed));
162
163 struct dsa_raw_desc {
164         uint64_t        field[8];
165 } __attribute__((packed));
166
167 /*
168  * The status field will be modified by hardware, therefore it should be
169  * volatile and prevent the compiler from optimize the read.
170  */
171 struct dsa_completion_record {
172         volatile uint8_t        status;
173         union {
174                 uint8_t         result;
175                 uint8_t         dif_status;
176         };
177         uint16_t                rsvd;
178         uint32_t                bytes_completed;
179         uint64_t                fault_addr;
180         union {
181                 uint16_t        delta_rec_size;
182                 uint16_t        crc_val;
183
184                 /* DIF check & strip */
185                 struct {
186                         uint32_t        dif_chk_ref_tag;
187                         uint16_t        dif_chk_app_tag_mask;
188                         uint16_t        dif_chk_app_tag;
189                 };
190
191                 /* DIF insert */
192                 struct {
193                         uint64_t        dif_ins_res;
194                         uint32_t        dif_ins_ref_tag;
195                         uint16_t        dif_ins_app_tag_mask;
196                         uint16_t        dif_ins_app_tag;
197                 };
198
199                 /* DIF update */
200                 struct {
201                         uint32_t        dif_upd_src_ref_tag;
202                         uint16_t        dif_upd_src_app_tag_mask;
203                         uint16_t        dif_upd_src_app_tag;
204                         uint32_t        dif_upd_dest_ref_tag;
205                         uint16_t        dif_upd_dest_app_tag_mask;
206                         uint16_t        dif_upd_dest_app_tag;
207                 };
208
209                 uint8_t         op_specific[16];
210         };
211 } __attribute__((packed));
212
213 struct dsa_raw_completion_record {
214         uint64_t        field[4];
215 } __attribute__((packed));
216
217 #endif