2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * This file contains all the macros and symbols which define
26 * a PowerPC assembly language environment.
28 #ifndef __PPC_ASM_TMPL__
29 #define __PPC_ASM_TMPL__
31 /***************************************************************************
33 * These definitions simplify the ugly declarations necessary for GOT
36 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
38 * Uses r14 to access the GOT
42 .section ".got2","aw"; \
51 0: .long .LCTOC1-1f ; \
57 #define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
59 #define GOT(NAME) .L_ ## NAME (r14)
62 /***************************************************************************
99 #if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
101 /* Some special registers */
103 #define ICR 148 /* Interrupt Cause Register (37-44) */
105 #define COUNTA 150 /* Breakpoint Counter (37-44) */
106 #define COUNTB 151 /* Breakpoint Counter (37-44) */
107 #define LCTRL1 156 /* Load/Store Support (37-40) */
108 #define LCTRL2 157 /* Load/Store Support (37-41) */
111 #endif /* CONFIG_8xx, CONFIG_MPC824X */
113 #if defined(CONFIG_8xx)
115 /* Registers in the processor's internal memory map that we use.
117 #define SYPCR 0x00000004
118 #define BR0 0x00000100
119 #define OR0 0x00000104
120 #define BR1 0x00000108
121 #define OR1 0x0000010c
122 #define BR2 0x00000110
123 #define OR2 0x00000114
124 #define BR3 0x00000118
125 #define OR3 0x0000011c
126 #define BR4 0x00000120
127 #define OR4 0x00000124
129 #define MAR 0x00000164
130 #define MCR 0x00000168
131 #define MAMR 0x00000170
132 #define MBMR 0x00000174
133 #define MSTAT 0x00000178
134 #define MPTPR 0x0000017a
135 #define MDR 0x0000017c
137 #define TBSCR 0x00000200
138 #define TBREFF0 0x00000204
140 #define PLPRCR 0x00000284
142 #elif defined(CONFIG_8260)
146 #define HID0_IFEM (1<<7)
148 #define HID0_ICE_BITPOS 16
149 #define HID0_DCE_BITPOS 17
151 #define IM_REGBASE 0x10000
152 #define IM_SYPCR (IM_REGBASE+0x0004)
153 #define IM_SWSR (IM_REGBASE+0x000e)
154 #define IM_BR0 (IM_REGBASE+0x0100)
155 #define IM_OR0 (IM_REGBASE+0x0104)
156 #define IM_BR1 (IM_REGBASE+0x0108)
157 #define IM_OR1 (IM_REGBASE+0x010c)
158 #define IM_BR2 (IM_REGBASE+0x0110)
159 #define IM_OR2 (IM_REGBASE+0x0114)
160 #define IM_MPTPR (IM_REGBASE+0x0184)
161 #define IM_PSDMR (IM_REGBASE+0x0190)
162 #define IM_PSRT (IM_REGBASE+0x019c)
163 #define IM_IMMR (IM_REGBASE+0x01a8)
164 #define IM_SCCR (IM_REGBASE+0x0c80)
175 * Macros for storing registers into and loading registers from
178 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
179 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
180 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
181 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
182 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
183 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
184 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
185 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
186 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
187 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
190 * GCC sometimes accesses words at negative offsets from the stack
191 * pointer, although the SysV ABI says it shouldn't. To cope with
192 * this, we leave this much untouched space on the stack on exception
195 #define STACK_UNDERHEAD 64
198 * Exception entry code. This code runs with address translation
199 * turned off, i.e. using physical addresses.
200 * We assume sprg3 has the physical address of the current
201 * task's thread_struct.
203 #define EXCEPTION_PROLOG \
207 subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
208 stw r20,_CCR(r21); /* save registers */ \
209 stw r22,GPR22(r21); \
210 stw r23,GPR23(r21); \
212 stw r20,GPR20(r21); \
214 stw r22,GPR21(r21); \
216 stw r20,_LINK(r21); \
227 mr r1,r21; /* set new kernel sp */ \
230 * Note: code which follows this uses cr0.eq (set if from kernel),
231 * r21, r22 (SRR0), and r23 (SRR1).
235 * Critical exception entry code. This is just like the other exception
236 * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
238 #define CRITICAL_EXCEPTION_PROLOG \
242 subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
243 stw r20,_CCR(r21); /* save registers */ \
244 stw r22,GPR22(r21); \
245 stw r23,GPR23(r21); \
247 stw r20,GPR20(r21); \
249 stw r22,GPR21(r21); \
251 stw r20,_LINK(r21); \
256 mfspr r22,990; /* SRR2 */ \
257 mfspr r23,991; /* SRR3 */ \
262 mr r1,r21; /* set new kernel sp */ \
265 * Note: code which follows this uses cr0.eq (set if from kernel),
266 * r21, r22 (SRR2), and r23 (SRR3).
272 * The data words for `hdlr' and `int_return' are initialized with
273 * OFFSET values only; they must be relocated first before they can
276 #define STD_EXCEPTION(n, label, hdlr) \
280 lwz r3,GOT(transfer_to_handler); \
282 addi r3,r1,STACK_FRAME_OVERHEAD; \
284 rlwimi r20,r23,0,25,25; \
287 .long hdlr - _start + EXC_OFF_SYS_RESET; \
288 .long int_return - _start + EXC_OFF_SYS_RESET
291 #define CRIT_EXCEPTION(n, label, hdlr) \
294 CRITICAL_EXCEPTION_PROLOG; \
295 lwz r3,GOT(transfer_to_handler); \
297 addi r3,r1,STACK_FRAME_OVERHEAD; \
299 rlwimi r20,r23,0,25,25; \
302 .long hdlr - _start + EXC_OFF_SYS_RESET; \
303 .long crit_return - _start + EXC_OFF_SYS_RESET
305 #endif /* __PPC_ASM_TMPL__ */