2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
27 # define CONFIG_PCMCIA_SLOT_A
28 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
29 # define CONFIG_PCMCIA_SLOT_A
31 # error "PCMCIA Slot not configured"
34 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
36 /* Make sure exactly one slot is defined - we support only one for now */
37 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
38 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
40 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
41 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
44 #ifndef PCMCIA_SOCKETS_NO
45 #define PCMCIA_SOCKETS_NO 1
47 #ifndef PCMCIA_MEM_WIN_NO
48 #define PCMCIA_MEM_WIN_NO 4
50 #define PCMCIA_IO_WIN_NO 2
52 /* define _slot_ to be able to optimize macros */
53 #ifdef CONFIG_PCMCIA_SLOT_A
55 # define PCMCIA_SLOT_MSG "slot A"
56 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
59 # define PCMCIA_SLOT_MSG "slot B"
60 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
64 * The TQM850L hardware has two pins swapped! Grrrrgh!
67 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
68 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
70 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
71 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
75 * This structure is used to address each window in the PCMCIA controller.
77 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
78 * after pcmcia_win_t[n]...
87 * Definitions for PCMCIA control registers to operate in IDE mode
89 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
90 * to be done later (depending on CPU clock)
94 * Base: 0xFE100000 CS1
100 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
101 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
109 * Base: 0xFE100080 CS1
112 * Common Memory Space
115 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
116 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
124 * Base: 0xFE100100 CS2
127 * Common Memory Space
130 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
131 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
141 #define CONFIG_SYS_PCMCIA_PBR3 0
142 #define CONFIG_SYS_PCMCIA_POR3 0
145 * Base: 0xFE100C00 CS1
148 * Common Memory Space
151 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
152 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
160 * Base: 0xFE100C80 CS1
163 * Common Memory Space
166 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
167 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
175 * Base: 0xFE100D00 CS2
178 * Common Memory Space
181 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
182 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
192 #define CONFIG_SYS_PCMCIA_PBR7 0
193 #define CONFIG_SYS_PCMCIA_POR7 0
195 /**********************************************************************/
200 #define CISTPL_NULL 0x00
201 #define CISTPL_DEVICE 0x01
202 #define CISTPL_LONGLINK_CB 0x02
203 #define CISTPL_INDIRECT 0x03
204 #define CISTPL_CONFIG_CB 0x04
205 #define CISTPL_CFTABLE_ENTRY_CB 0x05
206 #define CISTPL_LONGLINK_MFC 0x06
207 #define CISTPL_BAR 0x07
208 #define CISTPL_PWR_MGMNT 0x08
209 #define CISTPL_EXTDEVICE 0x09
210 #define CISTPL_CHECKSUM 0x10
211 #define CISTPL_LONGLINK_A 0x11
212 #define CISTPL_LONGLINK_C 0x12
213 #define CISTPL_LINKTARGET 0x13
214 #define CISTPL_NO_LINK 0x14
215 #define CISTPL_VERS_1 0x15
216 #define CISTPL_ALTSTR 0x16
217 #define CISTPL_DEVICE_A 0x17
218 #define CISTPL_JEDEC_C 0x18
219 #define CISTPL_JEDEC_A 0x19
220 #define CISTPL_CONFIG 0x1a
221 #define CISTPL_CFTABLE_ENTRY 0x1b
222 #define CISTPL_DEVICE_OC 0x1c
223 #define CISTPL_DEVICE_OA 0x1d
224 #define CISTPL_DEVICE_GEO 0x1e
225 #define CISTPL_DEVICE_GEO_A 0x1f
226 #define CISTPL_MANFID 0x20
227 #define CISTPL_FUNCID 0x21
228 #define CISTPL_FUNCE 0x22
229 #define CISTPL_SWIL 0x23
230 #define CISTPL_END 0xff
233 * CIS Function ID codes
235 #define CISTPL_FUNCID_MULTI 0x00
236 #define CISTPL_FUNCID_MEMORY 0x01
237 #define CISTPL_FUNCID_SERIAL 0x02
238 #define CISTPL_FUNCID_PARALLEL 0x03
239 #define CISTPL_FUNCID_FIXED 0x04
240 #define CISTPL_FUNCID_VIDEO 0x05
241 #define CISTPL_FUNCID_NETWORK 0x06
242 #define CISTPL_FUNCID_AIMS 0x07
243 #define CISTPL_FUNCID_SCSI 0x08
246 * Fixed Disk FUNCE codes
248 #define CISTPL_IDE_INTERFACE 0x01
250 #define CISTPL_FUNCE_IDE_IFACE 0x01
251 #define CISTPL_FUNCE_IDE_MASTER 0x02
252 #define CISTPL_FUNCE_IDE_SLAVE 0x03
254 /* First feature byte */
255 #define CISTPL_IDE_SILICON 0x04
256 #define CISTPL_IDE_UNIQUE 0x08
257 #define CISTPL_IDE_DUAL 0x10
259 /* Second feature byte */
260 #define CISTPL_IDE_HAS_SLEEP 0x01
261 #define CISTPL_IDE_HAS_STANDBY 0x02
262 #define CISTPL_IDE_HAS_IDLE 0x04
263 #define CISTPL_IDE_LOW_POWER 0x08
264 #define CISTPL_IDE_REG_INHIBIT 0x10
265 #define CISTPL_IDE_HAS_INDEX 0x20
266 #define CISTPL_IDE_IOIS16 0x40
271 extern u_int *pcmcia_pgcrx[];
272 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
275 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
276 extern int check_ide_device(int slot);
279 #endif /* _PCMCIA_H */