1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #define PCI_CFG_SPACE_SIZE 256
14 #define PCI_CFG_SPACE_EXP_SIZE 4096
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
20 #define PCI_STD_HEADER_SIZEOF 64
21 #define PCI_VENDOR_ID 0x00 /* 16 bits */
22 #define PCI_DEVICE_ID 0x02 /* 16 bits */
23 #define PCI_COMMAND 0x04 /* 16 bits */
24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
35 #define PCI_STATUS 0x06 /* 16 bits */
36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42 #define PCI_STATUS_DEVSEL_FAST 0x000
43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
44 #define PCI_STATUS_DEVSEL_SLOW 0x400
45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
53 #define PCI_REVISION_ID 0x08 /* Revision ID */
54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55 #define PCI_CLASS_DEVICE 0x0a /* Device class */
56 #define PCI_CLASS_CODE 0x0b /* Device class code */
57 #define PCI_CLASS_CODE_TOO_OLD 0x00
58 #define PCI_CLASS_CODE_STORAGE 0x01
59 #define PCI_CLASS_CODE_NETWORK 0x02
60 #define PCI_CLASS_CODE_DISPLAY 0x03
61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04
62 #define PCI_CLASS_CODE_MEMORY 0x05
63 #define PCI_CLASS_CODE_BRIDGE 0x06
64 #define PCI_CLASS_CODE_COMM 0x07
65 #define PCI_CLASS_CODE_PERIPHERAL 0x08
66 #define PCI_CLASS_CODE_INPUT 0x09
67 #define PCI_CLASS_CODE_DOCKING 0x0A
68 #define PCI_CLASS_CODE_PROCESSOR 0x0B
69 #define PCI_CLASS_CODE_SERIAL 0x0C
70 #define PCI_CLASS_CODE_WIRELESS 0x0D
71 #define PCI_CLASS_CODE_I2O 0x0E
72 #define PCI_CLASS_CODE_SATELLITE 0x0F
73 #define PCI_CLASS_CODE_CRYPTO 0x10
74 #define PCI_CLASS_CODE_DATA 0x11
75 /* Base Class 0x12 - 0xFE is reserved */
76 #define PCI_CLASS_CODE_OTHER 0xFF
78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
185 #define PCI_HEADER_TYPE_NORMAL 0
186 #define PCI_HEADER_TYPE_BRIDGE 1
187 #define PCI_HEADER_TYPE_CARDBUS 2
189 #define PCI_BIST 0x0f /* 8 bits */
190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
216 /* bit 1 is reserved if address_space = 1 */
218 /* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
219 #define pci_offset_to_barnum(offset) \
220 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
222 /* Header type 0 (normal devices) */
223 #define PCI_CARDBUS_CIS 0x28
224 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
225 #define PCI_SUBSYSTEM_ID 0x2e
226 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
227 #define PCI_ROM_ADDRESS_ENABLE 0x01
228 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
230 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
232 /* 0x35-0x3b are reserved */
233 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
234 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
235 #define PCI_MIN_GNT 0x3e /* 8 bits */
236 #define PCI_MAX_LAT 0x3f /* 8 bits */
238 #define PCI_INTERRUPT_LINE_DISABLE 0xff
240 /* Header type 1 (PCI-to-PCI bridges) */
241 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
242 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
243 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
244 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
245 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
246 #define PCI_IO_LIMIT 0x1d
247 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
248 #define PCI_IO_RANGE_TYPE_16 0x00
249 #define PCI_IO_RANGE_TYPE_32 0x01
250 #define PCI_IO_RANGE_MASK ~0x0f
251 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
252 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
253 #define PCI_MEMORY_LIMIT 0x22
254 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
255 #define PCI_MEMORY_RANGE_MASK ~0x0f
256 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
257 #define PCI_PREF_MEMORY_LIMIT 0x26
258 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
259 #define PCI_PREF_RANGE_TYPE_32 0x00
260 #define PCI_PREF_RANGE_TYPE_64 0x01
261 #define PCI_PREF_RANGE_MASK ~0x0f
262 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
263 #define PCI_PREF_LIMIT_UPPER32 0x2c
264 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
265 #define PCI_IO_LIMIT_UPPER16 0x32
266 /* 0x34 same as for htype 0 */
267 /* 0x35-0x3b is reserved */
268 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
269 /* 0x3c-0x3d are same as for htype 0 */
270 #define PCI_BRIDGE_CONTROL 0x3e
271 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
272 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
273 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
274 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
275 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
276 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
277 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
279 /* Header type 2 (CardBus bridges) */
280 #define PCI_CB_CAPABILITY_LIST 0x14
282 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
283 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
284 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
285 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
286 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
287 #define PCI_CB_MEMORY_BASE_0 0x1c
288 #define PCI_CB_MEMORY_LIMIT_0 0x20
289 #define PCI_CB_MEMORY_BASE_1 0x24
290 #define PCI_CB_MEMORY_LIMIT_1 0x28
291 #define PCI_CB_IO_BASE_0 0x2c
292 #define PCI_CB_IO_BASE_0_HI 0x2e
293 #define PCI_CB_IO_LIMIT_0 0x30
294 #define PCI_CB_IO_LIMIT_0_HI 0x32
295 #define PCI_CB_IO_BASE_1 0x34
296 #define PCI_CB_IO_BASE_1_HI 0x36
297 #define PCI_CB_IO_LIMIT_1 0x38
298 #define PCI_CB_IO_LIMIT_1_HI 0x3a
299 #define PCI_CB_IO_RANGE_MASK ~0x03
300 /* 0x3c-0x3d are same as for htype 0 */
301 #define PCI_CB_BRIDGE_CONTROL 0x3e
302 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
303 #define PCI_CB_BRIDGE_CTL_SERR 0x02
304 #define PCI_CB_BRIDGE_CTL_ISA 0x04
305 #define PCI_CB_BRIDGE_CTL_VGA 0x08
306 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
307 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
308 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
309 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
310 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
311 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
312 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
313 #define PCI_CB_SUBSYSTEM_ID 0x42
314 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
315 /* 0x48-0x7f reserved */
317 /* Capability lists */
319 #define PCI_CAP_LIST_ID 0 /* Capability ID */
320 #define PCI_CAP_ID_PM 0x01 /* Power Management */
321 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
322 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
323 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
324 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
325 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
326 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
327 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
328 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
329 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
330 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
331 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
332 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
333 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
334 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
335 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
336 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
337 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
338 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
339 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
340 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA
341 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
342 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
343 #define PCI_CAP_SIZEOF 4
345 /* Power Management Registers */
347 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
348 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
349 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
350 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
351 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
352 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
353 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
354 #define PCI_PM_CTRL 4 /* PM control and status register */
355 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
356 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
357 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
358 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
359 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
360 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
361 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
362 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
363 #define PCI_PM_DATA_REGISTER 7 /* (??) */
364 #define PCI_PM_SIZEOF 8
368 #define PCI_AGP_VERSION 2 /* BCD version number */
369 #define PCI_AGP_RFU 3 /* Rest of capability flags */
370 #define PCI_AGP_STATUS 4 /* Status register */
371 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
372 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
373 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
374 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
375 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
376 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
377 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
378 #define PCI_AGP_COMMAND 8 /* Control register */
379 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
380 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
381 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
382 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
383 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
384 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
385 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
386 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
387 #define PCI_AGP_SIZEOF 12
389 /* PCI-X registers */
391 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
392 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
393 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
394 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
395 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
398 /* Slot Identification */
400 #define PCI_SID_ESR 2 /* Expansion Slot Register */
401 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
402 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
403 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
405 /* Message Signalled Interrupts registers */
407 #define PCI_MSI_FLAGS 2 /* Various flags */
408 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
409 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
410 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
411 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
412 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
413 #define PCI_MSI_RFU 3 /* Rest of capability flags */
414 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
415 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
416 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
417 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
419 #define PCI_MAX_PCI_DEVICES 32
420 #define PCI_MAX_PCI_FUNCTIONS 8
422 #define PCI_FIND_CAP_TTL 0x48
423 #define CAP_START_POS 0x40
425 /* Extended Capabilities (PCI-X 2.0 and Express) */
426 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
427 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
428 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
430 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
431 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
432 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
433 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
434 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
435 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
436 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
437 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
438 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
439 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
440 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
441 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
442 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
443 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
444 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
445 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
446 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
447 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
448 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
449 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
450 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
451 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
452 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
453 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
454 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
455 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
456 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
457 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
458 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
459 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
460 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
462 /* Enhanced Allocation Registers */
463 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
464 #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
465 #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
466 #define PCI_EA_ES 0x00000007 /* Entry Size */
467 #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
468 /* Base, MaxOffset registers */
469 /* bit 0 is reserved */
470 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
471 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
473 /* PCI Express capabilities */
474 #define PCI_EXP_DEVCAP 4 /* Device capabilities */
475 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
476 #define PCI_EXP_DEVCTL 8 /* Device Control */
477 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
479 /* Include the ID list */
485 #ifdef CONFIG_SYS_PCI_64BIT
486 typedef u64 pci_addr_t;
487 typedef u64 pci_size_t;
489 typedef u32 pci_addr_t;
490 typedef u32 pci_size_t;
494 pci_addr_t bus_start; /* Start on the bus */
495 phys_addr_t phys_start; /* Start in physical address space */
496 pci_size_t size; /* Size */
497 unsigned long flags; /* Resource flags */
499 pci_addr_t bus_lower;
502 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
503 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
504 #define PCI_REGION_TYPE 0x00000001
505 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
507 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
508 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
510 static inline void pci_set_region(struct pci_region *reg,
511 pci_addr_t bus_start,
512 phys_addr_t phys_start,
514 unsigned long flags) {
515 reg->bus_start = bus_start;
516 reg->phys_start = phys_start;
521 typedef int pci_dev_t;
523 #define PCI_BUS(d) (((d) >> 16) & 0xff)
526 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
527 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
528 * Please see the Linux header include/uapi/linux/pci.h for more details.
529 * This is relevant for the following macros:
530 * PCI_DEV, PCI_FUNC, PCI_DEVFN
531 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
532 * the remark from above (input d in bits 15-8 instead of 7-0.
534 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
535 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
536 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
538 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
539 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
540 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
541 #define PCI_VENDEV(v, d) (((v) << 16) | (d))
542 #define PCI_ANY_ID (~0)
544 struct pci_device_id {
545 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
546 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
547 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
548 unsigned long driver_data; /* Data private to the driver */
551 struct pci_controller;
553 struct pci_config_table {
554 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
555 unsigned int class; /* Class ID, or PCI_ANY_ID */
556 unsigned int bus; /* Bus number, or PCI_ANY_ID */
557 unsigned int dev; /* Device number, or PCI_ANY_ID */
558 unsigned int func; /* Function number, or PCI_ANY_ID */
560 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
561 struct pci_config_table *);
562 unsigned long priv[3];
565 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
566 struct pci_config_table *);
567 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
568 struct pci_config_table *);
570 #define MAX_PCI_REGIONS 7
572 #define INDIRECT_TYPE_NO_PCIE_LINK 1
575 * Structure of a PCI controller (host bridge)
577 * With driver model this is dev_get_uclass_priv(bus)
579 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
580 * relocated. Normally if PCI is used before relocation, this happens
581 * before relocation also. Some platforms set up static configuration in
582 * TPL/SPL to reduce code size and boot time, since these phases only know
583 * about a small subset of PCI devices. This is normally false.
585 struct pci_controller {
588 struct udevice *ctlr;
589 bool skip_auto_config_until_reloc;
591 struct pci_controller *next;
597 volatile unsigned int *cfg_addr;
598 volatile unsigned char *cfg_data;
603 * TODO(sjg@chromium.org): With driver model we use struct
604 * pci_controller for both the controller and any bridge devices
605 * attached to it. But there is only one region list and it is in the
606 * top-level controller.
608 * This could be changed so that struct pci_controller is only used
609 * for PCI controllers and a separate UCLASS (or perhaps
610 * UCLASS_PCI_GENERIC) is used for bridges.
612 struct pci_region regions[MAX_PCI_REGIONS];
615 struct pci_config_table *config_table;
617 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
618 #ifndef CONFIG_DM_PCI
619 /* Low-level architecture-dependent routines */
620 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
621 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
622 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
623 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
624 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
625 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
628 /* Used by auto config */
629 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
631 #ifndef CONFIG_DM_PCI
638 #ifndef CONFIG_DM_PCI
639 static inline void pci_set_ops(struct pci_controller *hose,
640 int (*read_byte)(struct pci_controller*,
641 pci_dev_t, int where, u8 *),
642 int (*read_word)(struct pci_controller*,
643 pci_dev_t, int where, u16 *),
644 int (*read_dword)(struct pci_controller*,
645 pci_dev_t, int where, u32 *),
646 int (*write_byte)(struct pci_controller*,
647 pci_dev_t, int where, u8),
648 int (*write_word)(struct pci_controller*,
649 pci_dev_t, int where, u16),
650 int (*write_dword)(struct pci_controller*,
651 pci_dev_t, int where, u32)) {
652 hose->read_byte = read_byte;
653 hose->read_word = read_word;
654 hose->read_dword = read_dword;
655 hose->write_byte = write_byte;
656 hose->write_word = write_word;
657 hose->write_dword = write_dword;
661 #ifdef CONFIG_PCI_INDIRECT_BRIDGE
662 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
665 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
666 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
667 pci_addr_t addr, unsigned long flags);
668 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
669 phys_addr_t addr, unsigned long flags);
671 #define pci_phys_to_bus(dev, addr, flags) \
672 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
673 #define pci_bus_to_phys(dev, addr, flags) \
674 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
676 #define pci_virt_to_bus(dev, addr, flags) \
677 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
678 (virt_to_phys(addr)), (flags))
679 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
680 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
684 #define pci_phys_to_mem(dev, addr) \
685 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
686 #define pci_mem_to_phys(dev, addr) \
687 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
688 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
689 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
691 #define pci_virt_to_mem(dev, addr) \
692 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
693 #define pci_mem_to_virt(dev, addr, len, map_flags) \
694 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
695 #define pci_virt_to_io(dev, addr) \
696 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
697 #define pci_io_to_virt(dev, addr, len, map_flags) \
698 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
700 /* For driver model these are defined in macros in pci_compat.c */
701 extern int pci_hose_read_config_byte(struct pci_controller *hose,
702 pci_dev_t dev, int where, u8 *val);
703 extern int pci_hose_read_config_word(struct pci_controller *hose,
704 pci_dev_t dev, int where, u16 *val);
705 extern int pci_hose_read_config_dword(struct pci_controller *hose,
706 pci_dev_t dev, int where, u32 *val);
707 extern int pci_hose_write_config_byte(struct pci_controller *hose,
708 pci_dev_t dev, int where, u8 val);
709 extern int pci_hose_write_config_word(struct pci_controller *hose,
710 pci_dev_t dev, int where, u16 val);
711 extern int pci_hose_write_config_dword(struct pci_controller *hose,
712 pci_dev_t dev, int where, u32 val);
715 #ifndef CONFIG_DM_PCI
716 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
717 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
718 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
719 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
720 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
721 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
724 void pciauto_region_init(struct pci_region *res);
725 void pciauto_region_align(struct pci_region *res, pci_size_t size);
726 void pciauto_config_init(struct pci_controller *hose);
729 * pciauto_region_allocate() - Allocate resources from a PCI resource region
731 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
732 * false, the result will be guaranteed to fit in 32 bits.
734 * @res: PCI region to allocate from
735 * @size: Amount of bytes to allocate
736 * @bar: Returns the PCI bus address of the allocated resource
737 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
738 * @return 0 if successful, -1 on failure
740 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
741 pci_addr_t *bar, bool supports_64bit);
743 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
744 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
745 pci_dev_t dev, int where, u8 *val);
746 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
747 pci_dev_t dev, int where, u16 *val);
748 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
749 pci_dev_t dev, int where, u8 val);
750 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
751 pci_dev_t dev, int where, u16 val);
753 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
754 extern void pci_register_hose(struct pci_controller* hose);
755 extern struct pci_controller* pci_bus_to_hose(int bus);
756 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
757 extern struct pci_controller *pci_get_hose_head(void);
759 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
760 extern int pci_hose_scan(struct pci_controller *hose);
761 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
763 extern void pciauto_setup_device(struct pci_controller *hose,
764 pci_dev_t dev, int bars_num,
765 struct pci_region *mem,
766 struct pci_region *prefetch,
767 struct pci_region *io);
768 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
769 pci_dev_t dev, int sub_bus);
770 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
771 pci_dev_t dev, int sub_bus);
772 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
774 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
775 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
776 pci_dev_t pci_find_class(unsigned int find_class, int index);
778 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
780 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
782 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
785 int pci_find_next_ext_capability(struct pci_controller *hose,
786 pci_dev_t dev, int start, int cap);
787 int pci_hose_find_ext_capability(struct pci_controller *hose,
788 pci_dev_t dev, int cap);
790 #ifdef CONFIG_PCI_FIXUP_DEV
791 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
792 unsigned short vendor,
793 unsigned short device,
794 unsigned short class);
796 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
798 const char * pci_class_str(u8 class);
799 int pci_last_busno(void);
801 #ifdef CONFIG_MPC85xx
802 extern void pci_mpc85xx_init (struct pci_controller *hose);
805 #ifdef CONFIG_PCIE_IMX
806 extern void imx_pcie_remove(void);
809 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
811 * pci_write_bar32() - Write the address of a BAR including control bits
813 * This writes a raw address (with control bits) to a bar. This can be used
814 * with devices which require hard-coded addresses, not part of the normal
815 * PCI enumeration process.
817 * @hose: PCI hose to use
818 * @dev: PCI device to update
819 * @barnum: BAR number (0-5)
820 * @addr: BAR address with control bits
822 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
826 * pci_read_bar32() - read the address of a bar
828 * @hose: PCI hose to use
829 * @dev: PCI device to inspect
830 * @barnum: BAR number (0-5)
831 * @return address of the bar, masking out any control bits
833 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
836 * pci_hose_find_devices() - Find devices by vendor/device ID
838 * @hose: PCI hose to search
839 * @busnum: Bus number to search
840 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
841 * @indexp: Pointer to device index to find. To find the first matching
842 * device, pass 0; to find the second, pass 1, etc. This
843 * parameter is decremented for each non-matching device so
844 * can be called repeatedly.
846 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
847 struct pci_device_id *ids, int *indexp);
848 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
850 /* Access sizes for PCI reads and writes */
861 * struct pci_child_platdata - information stored about each PCI device
863 * Every device on a PCI bus has this per-child data.
865 * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
866 * PCI bus (i.e. UCLASS_PCI)
868 * @devfn: Encoded device and function index - see PCI_DEVFN()
869 * @vendor: PCI vendor ID (see pci_ids.h)
870 * @device: PCI device ID (see pci_ids.h)
871 * @class: PCI class, 3 bytes: (base, sub, prog-if)
873 struct pci_child_platdata {
875 unsigned short vendor;
876 unsigned short device;
880 /* PCI bus operations */
883 * read_config() - Read a PCI configuration value
885 * PCI buses must support reading and writing configuration values
886 * so that the bus can be scanned and its devices configured.
888 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
889 * If bridges exist it is possible to use the top-level bus to
890 * access a sub-bus. In that case @bus will be the top-level bus
891 * and PCI_BUS(bdf) will be a different (higher) value
893 * @bus: Bus to read from
894 * @bdf: Bus, device and function to read
895 * @offset: Byte offset within the device's configuration space
896 * @valuep: Place to put the returned value
898 * @return 0 if OK, -ve on error
900 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
901 ulong *valuep, enum pci_size_t size);
903 * write_config() - Write a PCI configuration value
905 * @bus: Bus to write to
906 * @bdf: Bus, device and function to write
907 * @offset: Byte offset within the device's configuration space
908 * @value: Value to write
910 * @return 0 if OK, -ve on error
912 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
913 ulong value, enum pci_size_t size);
916 /* Get access to a PCI bus' operations */
917 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
920 * dm_pci_get_bdf() - Get the BDF value for a device
922 * @dev: Device to check
923 * @return bus/device/function value (see PCI_BDF())
925 pci_dev_t dm_pci_get_bdf(struct udevice *dev);
928 * pci_bind_bus_devices() - scan a PCI bus and bind devices
930 * Scan a PCI bus looking for devices. Bind each one that is found. If
931 * devices are already bound that match the scanned devices, just update the
932 * child data so that the device can be used correctly (this happens when
933 * the device tree describes devices we expect to see on the bus).
935 * Devices that are bound in this way will use a generic PCI driver which
936 * does nothing. The device can still be accessed but will not provide any
939 * @bus: Bus containing devices to bind
940 * @return 0 if OK, -ve on error
942 int pci_bind_bus_devices(struct udevice *bus);
945 * pci_auto_config_devices() - configure bus devices ready for use
947 * This works through all devices on a bus by scanning the driver model
948 * data structures (normally these have been set up by pci_bind_bus_devices()
951 * Space is allocated for each PCI base address register (BAR) so that the
952 * devices are mapped into memory and I/O space ready for use.
954 * @bus: Bus containing devices to bind
955 * @return 0 if OK, -ve on error
957 int pci_auto_config_devices(struct udevice *bus);
960 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
962 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
963 * @devp: Returns the device for this address, if found
964 * @return 0 if OK, -ENODEV if not found
966 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
969 * pci_bus_find_devfn() - Find a device on a bus
971 * @find_devfn: PCI device address (device and function only)
972 * @devp: Returns the device for this address, if found
973 * @return 0 if OK, -ENODEV if not found
975 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
976 struct udevice **devp);
979 * pci_find_first_device() - return the first available PCI device
981 * This function and pci_find_first_device() allow iteration through all
982 * available PCI devices on all buses. Assuming there are any, this will
983 * return the first one.
985 * @devp: Set to the first available device, or NULL if no more are left
987 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
989 int pci_find_first_device(struct udevice **devp);
992 * pci_find_next_device() - return the next available PCI device
994 * Finds the next available PCI device after the one supplied, or sets @devp
995 * to NULL if there are no more.
997 * @devp: On entry, the last device returned. Set to the next available
998 * device, or NULL if no more are left or we got an error
999 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
1001 int pci_find_next_device(struct udevice **devp);
1004 * pci_get_ff() - Returns a mask for the given access size
1006 * @size: Access size
1007 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
1010 int pci_get_ff(enum pci_size_t size);
1013 * pci_bus_find_devices () - Find devices on a bus
1015 * @bus: Bus to search
1016 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1017 * @indexp: Pointer to device index to find. To find the first matching
1018 * device, pass 0; to find the second, pass 1, etc. This
1019 * parameter is decremented for each non-matching device so
1020 * can be called repeatedly.
1021 * @devp: Returns matching device if found
1022 * @return 0 if found, -ENODEV if not
1024 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
1025 int *indexp, struct udevice **devp);
1028 * pci_find_device_id() - Find a device on any bus
1030 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1031 * @index: Index number of device to find, 0 for the first match, 1 for
1033 * @devp: Returns matching device if found
1034 * @return 0 if found, -ENODEV if not
1036 int pci_find_device_id(struct pci_device_id *ids, int index,
1037 struct udevice **devp);
1040 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1042 * This probes the given bus which causes it to be scanned for devices. The
1043 * devices will be bound but not probed.
1045 * @hose specifies the PCI hose that will be used for the scan. This is
1046 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1047 * in @bdf, and is a subordinate bus reachable from @hose.
1049 * @hose: PCI hose to scan
1050 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1051 * @return 0 if OK, -ve on error
1053 int dm_pci_hose_probe_bus(struct udevice *bus);
1056 * pci_bus_read_config() - Read a configuration value from a device
1058 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1059 * it do the right thing. It would be good to have that function also.
1061 * @bus: Bus to read from
1062 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1063 * @offset: Register offset to read
1064 * @valuep: Place to put the returned value
1065 * @size: Access size
1066 * @return 0 if OK, -ve on error
1068 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1069 unsigned long *valuep, enum pci_size_t size);
1072 * pci_bus_write_config() - Write a configuration value to a device
1074 * @bus: Bus to write from
1075 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1076 * @offset: Register offset to write
1077 * @value: Value to write
1078 * @size: Access size
1079 * @return 0 if OK, -ve on error
1081 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1082 unsigned long value, enum pci_size_t size);
1085 * pci_bus_clrset_config32() - Update a configuration value for a device
1087 * The register at @offset is updated to (oldvalue & ~clr) | set.
1089 * @bus: Bus to access
1090 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1091 * @offset: Register offset to update
1092 * @clr: Bits to clear
1094 * @return 0 if OK, -ve on error
1096 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1100 * Driver model PCI config access functions. Use these in preference to others
1101 * when you have a valid device
1103 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1104 enum pci_size_t size);
1106 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1107 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1108 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1110 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1111 enum pci_size_t size);
1113 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1114 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1115 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1118 * These permit convenient read/modify/write on PCI configuration. The
1119 * register is updated to (oldvalue & ~clr) | set.
1121 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1122 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1123 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1126 * The following functions provide access to the above without needing the
1127 * size parameter. We are trying to encourage the use of the 8/16/32-style
1128 * functions, rather than byte/word/dword. But both are supported.
1130 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1131 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1132 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1133 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1134 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1135 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1138 * pci_generic_mmap_write_config() - Generic helper for writing to
1139 * memory-mapped PCI configuration space.
1140 * @bus: Pointer to the PCI bus
1141 * @addr_f: Callback for calculating the config space address
1142 * @bdf: Identifies the PCI device to access
1143 * @offset: The offset into the device's configuration space
1144 * @value: The value to write
1145 * @size: Indicates the size of access to perform
1147 * Write the value @value of size @size from offset @offset within the
1148 * configuration space of the device identified by the bus, device & function
1149 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1150 * responsible for calculating the CPU address of the respective configuration
1153 * Return: 0 on success, else -EINVAL
1155 int pci_generic_mmap_write_config(
1156 struct udevice *bus,
1157 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1161 enum pci_size_t size);
1164 * pci_generic_mmap_read_config() - Generic helper for reading from
1165 * memory-mapped PCI configuration space.
1166 * @bus: Pointer to the PCI bus
1167 * @addr_f: Callback for calculating the config space address
1168 * @bdf: Identifies the PCI device to access
1169 * @offset: The offset into the device's configuration space
1170 * @valuep: A pointer at which to store the read value
1171 * @size: Indicates the size of access to perform
1173 * Read a value of size @size from offset @offset within the configuration
1174 * space of the device identified by the bus, device & function numbers in @bdf
1175 * on the PCI bus @bus. The callback function @addr_f is responsible for
1176 * calculating the CPU address of the respective configuration space offset.
1178 * Return: 0 on success, else -EINVAL
1180 int pci_generic_mmap_read_config(
1181 struct udevice *bus,
1182 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1186 enum pci_size_t size);
1188 #ifdef CONFIG_DM_PCI_COMPAT
1189 /* Compatibility with old naming */
1190 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1193 return pci_write_config32(pcidev, offset, value);
1196 /* Compatibility with old naming */
1197 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1200 return pci_write_config16(pcidev, offset, value);
1203 /* Compatibility with old naming */
1204 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1207 return pci_write_config8(pcidev, offset, value);
1210 /* Compatibility with old naming */
1211 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1214 return pci_read_config32(pcidev, offset, valuep);
1217 /* Compatibility with old naming */
1218 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1221 return pci_read_config16(pcidev, offset, valuep);
1224 /* Compatibility with old naming */
1225 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1228 return pci_read_config8(pcidev, offset, valuep);
1230 #endif /* CONFIG_DM_PCI_COMPAT */
1233 * dm_pciauto_config_device() - configure a device ready for use
1235 * Space is allocated for each PCI base address register (BAR) so that the
1236 * devices are mapped into memory and I/O space ready for use.
1238 * @dev: Device to configure
1239 * @return 0 if OK, -ve on error
1241 int dm_pciauto_config_device(struct udevice *dev);
1244 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1246 * Some PCI buses must always perform 32-bit reads. The data must then be
1247 * shifted and masked to reflect the required access size and offset. This
1248 * function performs this transformation.
1250 * @value: Value to transform (32-bit value read from @offset & ~3)
1251 * @offset: Register offset that was read
1252 * @size: Required size of the result
1253 * @return the value that would have been obtained if the read had been
1254 * performed at the given offset with the correct size
1256 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1259 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1261 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1262 * write the old 32-bit data must be read, updated with the required new data
1263 * and written back as a 32-bit value. This function performs the
1264 * transformation from the old value to the new value.
1266 * @value: Value to transform (32-bit value read from @offset & ~3)
1267 * @offset: Register offset that should be written
1268 * @size: Required size of the write
1269 * @return the value that should be written as a 32-bit access to @offset & ~3.
1271 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1272 enum pci_size_t size);
1275 * pci_get_controller() - obtain the controller to use for a bus
1277 * @dev: Device to check
1278 * @return pointer to the controller device for this bus
1280 struct udevice *pci_get_controller(struct udevice *dev);
1283 * pci_get_regions() - obtain pointers to all the region types
1285 * @dev: Device to check
1286 * @iop: Returns a pointer to the I/O region, or NULL if none
1287 * @memp: Returns a pointer to the memory region, or NULL if none
1288 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1289 * @return the number of non-NULL regions returned, normally 3
1291 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1292 struct pci_region **memp, struct pci_region **prefp);
1295 * dm_pci_write_bar32() - Write the address of a BAR
1297 * This writes a raw address to a bar
1299 * @dev: PCI device to update
1300 * @barnum: BAR number (0-5)
1301 * @addr: BAR address
1303 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1306 * dm_pci_read_bar32() - read a base address register from a device
1308 * @dev: Device to check
1309 * @barnum: Bar number to read (numbered from 0)
1310 * @return: value of BAR
1312 u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1315 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1317 * @dev: Device containing the PCI address
1318 * @addr: PCI address to convert
1319 * @flags: Flags for the region type (PCI_REGION_...)
1320 * @return physical address corresponding to that PCI bus address
1322 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1323 unsigned long flags);
1326 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1328 * @dev: Device containing the bus address
1329 * @addr: Physical address to convert
1330 * @flags: Flags for the region type (PCI_REGION_...)
1331 * @return PCI bus address corresponding to that physical address
1333 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1334 unsigned long flags);
1337 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1339 * Looks up a base address register and finds the physical memory address
1340 * that corresponds to it.
1341 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
1343 * Can also be used on type 0 functions that support Enhanced Allocation for
1344 * 32b/64b BARs. Note that duplicate BEI entries are not supported.
1346 * @dev: Device to check
1347 * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
1348 * @flags: Flags for the region type (PCI_REGION_...)
1349 * @return: pointer to the virtual address to use or 0 on error
1351 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1354 * dm_pci_find_next_capability() - find a capability starting from an offset
1356 * Tell if a device supports a given PCI capability. Returns the
1357 * address of the requested capability structure within the device's
1358 * PCI configuration space or 0 in case the device does not support it.
1360 * Possible values for @cap:
1362 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1363 * %PCI_CAP_ID_PCIX PCI-X
1364 * %PCI_CAP_ID_EXP PCI Express
1365 * %PCI_CAP_ID_MSIX MSI-X
1367 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1369 * @dev: PCI device to query
1370 * @start: offset to start from
1371 * @cap: capability code
1372 * @return: capability address or 0 if not supported
1374 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1377 * dm_pci_find_capability() - find a capability
1379 * Tell if a device supports a given PCI capability. Returns the
1380 * address of the requested capability structure within the device's
1381 * PCI configuration space or 0 in case the device does not support it.
1383 * Possible values for @cap:
1385 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1386 * %PCI_CAP_ID_PCIX PCI-X
1387 * %PCI_CAP_ID_EXP PCI Express
1388 * %PCI_CAP_ID_MSIX MSI-X
1390 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1392 * @dev: PCI device to query
1393 * @cap: capability code
1394 * @return: capability address or 0 if not supported
1396 int dm_pci_find_capability(struct udevice *dev, int cap);
1399 * dm_pci_find_next_ext_capability() - find an extended capability
1400 * starting from an offset
1402 * Tell if a device supports a given PCI express extended capability.
1403 * Returns the address of the requested extended capability structure
1404 * within the device's PCI configuration space or 0 in case the device
1405 * does not support it.
1407 * Possible values for @cap:
1409 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1410 * %PCI_EXT_CAP_ID_VC Virtual Channel
1411 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1412 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1414 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1416 * @dev: PCI device to query
1417 * @start: offset to start from
1418 * @cap: extended capability code
1419 * @return: extended capability address or 0 if not supported
1421 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1424 * dm_pci_find_ext_capability() - find an extended capability
1426 * Tell if a device supports a given PCI express extended capability.
1427 * Returns the address of the requested extended capability structure
1428 * within the device's PCI configuration space or 0 in case the device
1429 * does not support it.
1431 * Possible values for @cap:
1433 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1434 * %PCI_EXT_CAP_ID_VC Virtual Channel
1435 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1436 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1438 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1440 * @dev: PCI device to query
1441 * @cap: extended capability code
1442 * @return: extended capability address or 0 if not supported
1444 int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1447 * dm_pci_flr() - Perform FLR if the device suppoorts it
1449 * @dev: PCI device to reset
1450 * @return: 0 if OK, -ENOENT if FLR is not supported by dev
1452 int dm_pci_flr(struct udevice *dev);
1454 #define dm_pci_virt_to_bus(dev, addr, flags) \
1455 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1456 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1457 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1460 #define dm_pci_phys_to_mem(dev, addr) \
1461 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1462 #define dm_pci_mem_to_phys(dev, addr) \
1463 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1464 #define dm_pci_phys_to_io(dev, addr) \
1465 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1466 #define dm_pci_io_to_phys(dev, addr) \
1467 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1469 #define dm_pci_virt_to_mem(dev, addr) \
1470 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1471 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1472 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1473 #define dm_pci_virt_to_io(dev, addr) \
1474 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1475 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1476 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1479 * dm_pci_find_device() - find a device by vendor/device ID
1481 * @vendor: Vendor ID
1482 * @device: Device ID
1483 * @index: 0 to find the first match, 1 for second, etc.
1484 * @devp: Returns pointer to the device, if found
1485 * @return 0 if found, -ve on error
1487 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1488 struct udevice **devp);
1491 * dm_pci_find_class() - find a device by class
1493 * @find_class: 3-byte (24-bit) class value to find
1494 * @index: 0 to find the first match, 1 for second, etc.
1495 * @devp: Returns pointer to the device, if found
1496 * @return 0 if found, -ve on error
1498 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1501 * struct pci_emul_uc_priv - holds info about an emulator device
1503 * There is always at most one emulator per client
1505 * @client: Client device if any, else NULL
1507 struct pci_emul_uc_priv {
1508 struct udevice *client;
1512 * struct dm_pci_emul_ops - PCI device emulator operations
1514 struct dm_pci_emul_ops {
1516 * read_config() - Read a PCI configuration value
1518 * @dev: Emulated device to read from
1519 * @offset: Byte offset within the device's configuration space
1520 * @valuep: Place to put the returned value
1521 * @size: Access size
1522 * @return 0 if OK, -ve on error
1524 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1525 enum pci_size_t size);
1527 * write_config() - Write a PCI configuration value
1529 * @dev: Emulated device to write to
1530 * @offset: Byte offset within the device's configuration space
1531 * @value: Value to write
1532 * @size: Access size
1533 * @return 0 if OK, -ve on error
1535 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1536 enum pci_size_t size);
1538 * read_io() - Read a PCI I/O value
1540 * @dev: Emulated device to read from
1541 * @addr: I/O address to read
1542 * @valuep: Place to put the returned value
1543 * @size: Access size
1544 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1545 * other -ve value on error
1547 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1548 enum pci_size_t size);
1550 * write_io() - Write a PCI I/O value
1552 * @dev: Emulated device to write from
1553 * @addr: I/O address to write
1554 * @value: Value to write
1555 * @size: Access size
1556 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1557 * other -ve value on error
1559 int (*write_io)(struct udevice *dev, unsigned int addr,
1560 ulong value, enum pci_size_t size);
1562 * map_physmem() - Map a device into sandbox memory
1564 * @dev: Emulated device to map
1565 * @addr: Memory address, normally corresponding to a PCI BAR.
1566 * The device should have been configured to have a BAR
1568 * @lenp: On entry, the size of the area to map, On exit it is
1569 * updated to the size actually mapped, which may be less
1570 * if the device has less space
1571 * @ptrp: Returns a pointer to the mapped address. The device's
1572 * space can be accessed as @lenp bytes starting here
1573 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1574 * other -ve value on error
1576 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1577 unsigned long *lenp, void **ptrp);
1579 * unmap_physmem() - undo a memory mapping
1581 * This must be called after map_physmem() to undo the mapping.
1582 * Some devices can use this to check what has been written into
1583 * their mapped memory and perform an operations they require on it.
1584 * In this way, map/unmap can be used as a sort of handshake between
1585 * the emulated device and its users.
1587 * @dev: Emuated device to unmap
1588 * @vaddr: Mapped memory address, as passed to map_physmem()
1589 * @len: Size of area mapped, as returned by map_physmem()
1590 * @return 0 if OK, -ve on error
1592 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1596 /* Get access to a PCI device emulator's operations */
1597 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1600 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1602 * Searches for a suitable emulator for the given PCI bus device
1604 * @bus: PCI bus to search
1605 * @find_devfn: PCI device and function address (PCI_DEVFN())
1606 * @containerp: Returns container device if found
1607 * @emulp: Returns emulated device if found
1608 * @return 0 if found, -ENODEV if not found
1610 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1611 struct udevice **containerp, struct udevice **emulp);
1614 * sandbox_pci_get_client() - Find the client for an emulation device
1616 * @emul: Emulation device to check
1617 * @devp: Returns the client device emulated by this device
1618 * @return 0 if OK, -ENOENT if the device has no client yet
1620 int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
1623 * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
1625 * Get devfn from fdt_pci_addr of the specified device
1628 * @return devfn in bits 15...8 if found, -ENODEV if not found
1630 int pci_get_devfn(struct udevice *dev);
1632 #endif /* CONFIG_DM_PCI */
1635 * PCI_DEVICE - macro used to describe a specific pci device
1636 * @vend: the 16 bit PCI Vendor ID
1637 * @dev: the 16 bit PCI Device ID
1639 * This macro is used to create a struct pci_device_id that matches a
1640 * specific device. The subvendor and subdevice fields will be set to
1643 #define PCI_DEVICE(vend, dev) \
1644 .vendor = (vend), .device = (dev), \
1645 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1648 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1649 * @vend: the 16 bit PCI Vendor ID
1650 * @dev: the 16 bit PCI Device ID
1651 * @subvend: the 16 bit PCI Subvendor ID
1652 * @subdev: the 16 bit PCI Subdevice ID
1654 * This macro is used to create a struct pci_device_id that matches a
1655 * specific device with subsystem information.
1657 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1658 .vendor = (vend), .device = (dev), \
1659 .subvendor = (subvend), .subdevice = (subdev)
1662 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1663 * @dev_class: the class, subclass, prog-if triple for this device
1664 * @dev_class_mask: the class mask for this device
1666 * This macro is used to create a struct pci_device_id that matches a
1667 * specific PCI class. The vendor, device, subvendor, and subdevice
1668 * fields will be set to PCI_ANY_ID.
1670 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1671 .class = (dev_class), .class_mask = (dev_class_mask), \
1672 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1673 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1676 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1677 * @vend: the vendor name
1678 * @dev: the 16 bit PCI Device ID
1680 * This macro is used to create a struct pci_device_id that matches a
1681 * specific PCI device. The subvendor, and subdevice fields will be set
1682 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1686 #define PCI_VDEVICE(vend, dev) \
1687 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1688 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1691 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1692 * @driver: Driver to use
1693 * @match: List of match records for this driver, terminated by {}
1695 struct pci_driver_entry {
1696 struct driver *driver;
1697 const struct pci_device_id *match;
1700 #define U_BOOT_PCI_DEVICE(__name, __match) \
1701 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1702 .driver = llsym(struct driver, __name, driver), \
1706 #endif /* __ASSEMBLY__ */