3 * originally from linux source (arch/ppc/boot/ns16550.h)
5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
9 * have addresses as offsets from CONFIG_SYS_ISA_BASE
10 * added a few more definitions
11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
15 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
19 #if (CONFIG_SYS_NS16550_REG_SIZE == 1)
21 unsigned char rbr; /* 0 */
22 unsigned char ier; /* 1 */
23 unsigned char fcr; /* 2 */
24 unsigned char lcr; /* 3 */
25 unsigned char mcr; /* 4 */
26 unsigned char lsr; /* 5 */
27 unsigned char msr; /* 6 */
28 unsigned char scr; /* 7 */
29 #if defined(CONFIG_OMAP730)
30 unsigned char mdr1; /* 8 */
31 unsigned char reg9; /* 9 */
32 unsigned char regA; /* A */
33 unsigned char regB; /* B */
34 unsigned char regC; /* C */
35 unsigned char regD; /* D */
36 unsigned char regE; /* E */
37 unsigned char regF; /* F */
38 unsigned char reg10; /* 10 */
39 unsigned char ssr; /* 11*/
41 } __attribute__ ((packed));
42 #elif (CONFIG_SYS_NS16550_REG_SIZE == 2)
44 unsigned short rbr; /* 0 */
45 unsigned short ier; /* 1 */
46 unsigned short fcr; /* 2 */
47 unsigned short lcr; /* 3 */
48 unsigned short mcr; /* 4 */
49 unsigned short lsr; /* 5 */
50 unsigned short msr; /* 6 */
51 unsigned short scr; /* 7 */
52 } __attribute__ ((packed));
53 #elif (CONFIG_SYS_NS16550_REG_SIZE == 4)
55 unsigned long rbr; /* 0 r */
56 unsigned long ier; /* 1 rw */
57 unsigned long fcr; /* 2 w */
58 unsigned long lcr; /* 3 rw */
59 unsigned long mcr; /* 4 rw */
60 unsigned long lsr; /* 5 r */
61 unsigned long msr; /* 6 r */
62 unsigned long scr; /* 7 rw */
63 }; /* No need to pack an already aligned struct */
64 #elif (CONFIG_SYS_NS16550_REG_SIZE == -4)
66 unsigned char rbr; /* 0 */
68 unsigned char ier; /* 1 */
70 unsigned char fcr; /* 2 */
72 unsigned char lcr; /* 3 */
74 unsigned char mcr; /* 4 */
76 unsigned char lsr; /* 5 */
78 unsigned char msr; /* 6 */
80 unsigned char scr; /* 7 */
82 #if defined(CONFIG_OMAP)
83 unsigned char mdr1; /* mode select reset TL16C750*/
85 #ifdef CONFIG_OMAP1510
87 unsigned long pad[10];
88 unsigned char osc_12m_sel;
91 } __attribute__ ((packed));
92 #elif (CONFIG_SYS_NS16550_REG_SIZE == -8)
94 unsigned char rbr; /* 0 */
95 unsigned char pad0[7];
96 unsigned char ier; /* 1 */
97 unsigned char pad1[7];
98 unsigned char fcr; /* 2 */
99 unsigned char pad2[7];
100 unsigned char lcr; /* 3 */
101 unsigned char pad3[7];
102 unsigned char mcr; /* 4 */
103 unsigned char pad4[7];
104 unsigned char lsr; /* 5 */
105 unsigned char pad5[7];
106 unsigned char msr; /* 6 */
107 unsigned char pad6[7];
108 unsigned char scr; /* 7 */
109 unsigned char pad7[7];
110 } __attribute__ ((packed));
112 #error "Please define NS16550 registers size."
120 typedef volatile struct NS16550 *NS16550_t;
123 * These are the definitions for the FIFO Control Register
125 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
126 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
127 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
128 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
129 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
130 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
131 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
132 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
133 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
135 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
136 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
139 * These are the definitions for the Modem Control Register
141 #define UART_MCR_DTR 0x01 /* DTR */
142 #define UART_MCR_RTS 0x02 /* RTS */
143 #define UART_MCR_OUT1 0x04 /* Out 1 */
144 #define UART_MCR_OUT2 0x08 /* Out 2 */
145 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
147 #define UART_MCR_DMA_EN 0x04
148 #define UART_MCR_TX_DFR 0x08
151 * These are the definitions for the Line Control Register
153 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
154 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
156 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
157 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
158 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
159 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
160 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
161 #define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
162 #define UART_LCR_PEN 0x08 /* Parity eneble */
163 #define UART_LCR_EPS 0x10 /* Even Parity Select */
164 #define UART_LCR_STKP 0x20 /* Stick Parity */
165 #define UART_LCR_SBRK 0x40 /* Set Break */
166 #define UART_LCR_BKSE 0x80 /* Bank select enable */
167 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
170 * These are the definitions for the Line Status Register
172 #define UART_LSR_DR 0x01 /* Data ready */
173 #define UART_LSR_OE 0x02 /* Overrun */
174 #define UART_LSR_PE 0x04 /* Parity error */
175 #define UART_LSR_FE 0x08 /* Framing error */
176 #define UART_LSR_BI 0x10 /* Break */
177 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
178 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
179 #define UART_LSR_ERR 0x80 /* Error */
181 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
182 #define UART_MSR_RI 0x40 /* Ring Indicator */
183 #define UART_MSR_DSR 0x20 /* Data Set Ready */
184 #define UART_MSR_CTS 0x10 /* Clear to Send */
185 #define UART_MSR_DDCD 0x08 /* Delta DCD */
186 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
187 #define UART_MSR_DDSR 0x02 /* Delta DSR */
188 #define UART_MSR_DCTS 0x01 /* Delta CTS */
191 * These are the definitions for the Interrupt Identification Register
193 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
194 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
196 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
197 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
198 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
199 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
202 * These are the definitions for the Interrupt Enable Register
204 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
205 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
206 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
207 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
210 #ifdef CONFIG_OMAP1510
211 #define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
214 /* useful defaults for LCR */
215 #define UART_LCR_8N1 0x03
217 void NS16550_init (NS16550_t com_port, int baud_divisor);
218 void NS16550_putc (NS16550_t com_port, char c);
219 char NS16550_getc (NS16550_t com_port);
220 int NS16550_tstc (NS16550_t com_port);
221 void NS16550_reinit (NS16550_t com_port, int baud_divisor);