1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
15 #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
16 /* Only valid for mem access register interface */
17 #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
18 #define CLASS_DMEM_SIZE 0x00002000
19 #define CLASS_IMEM_SIZE 0x00008000
21 #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
22 /* Only valid for mem access register interface */
23 #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
24 #define TMU_DMEM_SIZE 0x00000800
25 #define TMU_IMEM_SIZE 0x00002000
27 #define UTIL_DMEM_BASE_ADDR 0x00000000
28 #define UTIL_DMEM_SIZE 0x00002000
30 #define PE_LMEM_BASE_ADDR 0xc3010000
31 #define PE_LMEM_SIZE 0x8000
32 #define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
34 #define DMEM_BASE_ADDR 0x00000000
35 #define DMEM_SIZE 0x2000 /* TMU has less... */
36 #define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
38 #define PMEM_BASE_ADDR 0x00010000
39 #define PMEM_SIZE 0x8000 /* TMU has less... */
40 #define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
42 /* Memory ranges check from PE point of view/memory map */
43 #define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
44 (((unsigned long)(addr) +\
46 #define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
47 (((unsigned long)(addr) +\
49 #define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
50 ) && (((unsigned long)(addr)\
51 + (len)) <= PE_LMEM_END))
53 #define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
54 CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
55 (((unsigned long)(addr) + (len)) <=\
56 CBUS_VIRT_TO_PFE(LMEM_END)))
57 #define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
58 PFE_DDR_PHYS_BASE_ADDR) &&\
59 (((unsigned long)(addr) + (len)) <=\
62 /* Host View Address */
63 extern void *ddr_pfe_base_addr;
65 /* PFE View Address */
66 /* DDR physical base address as seen by PE's. */
67 #define PFE_DDR_PHYS_BASE_ADDR 0x03800000
68 #define PFE_DDR_PHYS_SIZE 0xC000000
69 #define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
70 /* CBUS physical base address as seen by PE's. */
71 #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
73 /* Host<->PFE Mapping */
74 #define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
75 #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
76 PFE_CBUS_PHYS_BASE_ADDR)
77 #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
95 #define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
96 | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
98 #define CLASS_MAX_ID CLASS5_ID
100 #define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
101 #define TMU_MAX_ID TMU3_ID
105 * Structure containing PE's specific information. It is used to create
106 * generic C functions common to all PEs.
107 * Before using the library functions this structure needs to be
108 * initialized with the different registers virtual addresses
109 * (according to the ARM MMU mmaping). The default initialization supports a
110 * virtual == physical mapping.
114 u32 dmem_base_addr; /* PE's dmem base address */
115 u32 pmem_base_addr; /* PE's pmem base address */
116 u32 pmem_size; /* PE's pmem size */
118 void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
121 void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
124 void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
129 void pe_lmem_read(u32 *dst, u32 len, u32 offset);
130 void pe_lmem_write(u32 *src, u32 len, u32 offset);
132 u32 pe_pmem_read(int id, u32 addr, u8 size);
133 void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
134 u32 pe_dmem_read(int id, u32 addr, u8 size);
136 int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
138 void pfe_lib_init(void);
140 void bmu_init(void *base, struct bmu_cfg *cfg);
141 void bmu_enable(void *base);
143 void gpi_init(void *base, struct gpi_cfg *cfg);
144 void gpi_enable(void *base);
145 void gpi_disable(void *base);
147 void class_init(struct class_cfg *cfg);
148 void class_enable(void);
149 void class_disable(void);
151 void tmu_init(struct tmu_cfg *cfg);
152 void tmu_enable(u32 pe_mask);
153 void tmu_disable(u32 pe_mask);
156 void hif_tx_enable(void);
157 void hif_tx_disable(void);
158 void hif_rx_enable(void);
159 void hif_rx_disable(void);
160 void hif_rx_desc_disable(void);