PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)
[oweals/u-boot.git] / include / mpc83xx.h
1 /*
2  * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12
13 #ifndef __MPC83XX_H__
14 #define __MPC83XX_H__
15
16 #include <config.h>
17 #include <asm/fsl_lbc.h>
18 #if defined(CONFIG_E300)
19 #include <asm/e300.h>
20 #endif
21
22 /*
23  * MPC83xx cpu provide RCR register to do reset thing specially
24  */
25 #define MPC83xx_RESET
26
27 /*
28  * System reset offset (PowerPC standard)
29  */
30 #define EXC_OFF_SYS_RESET               0x0100
31 #define _START_OFFSET                   EXC_OFF_SYS_RESET
32
33 /*
34  * IMMRBAR - Internal Memory Register Base Address
35  */
36 #ifndef CONFIG_DEFAULT_IMMR
37 /* Default IMMR base address */
38 #define CONFIG_DEFAULT_IMMR             0xFF400000
39 #endif
40 /* Register offset to immr */
41 #define IMMRBAR                         0x0000
42 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base addr. mask */
43 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
44
45 /*
46  * LAWBAR - Local Access Window Base Address Register
47  */
48 /* Register offset to immr */
49 #define LBLAWBAR0                       0x0020
50 #define LBLAWAR0                        0x0024
51 #define LBLAWBAR1                       0x0028
52 #define LBLAWAR1                        0x002C
53 #define LBLAWBAR2                       0x0030
54 #define LBLAWAR2                        0x0034
55 #define LBLAWBAR3                       0x0038
56 #define LBLAWAR3                        0x003C
57 #define LAWBAR_BAR                      0xFFFFF000      /* Base addr. mask */
58
59 /*
60  * SPRIDR - System Part and Revision ID Register
61  */
62 #define SPRIDR_PARTID                   0xFFFF0000      /* Part Id */
63 #define SPRIDR_REVID                    0x0000FFFF      /* Revision Id */
64
65 #if defined(CONFIG_MPC834x)
66 #define REVID_MAJOR(spridr)             ((spridr & 0x0000FF00) >> 8)
67 #define REVID_MINOR(spridr)             (spridr & 0x000000FF)
68 #else
69 #define REVID_MAJOR(spridr)             ((spridr & 0x000000F0) >> 4)
70 #define REVID_MINOR(spridr)             (spridr & 0x0000000F)
71 #endif
72
73 #define PARTID_NO_E(spridr)             ((spridr & 0xFFFE0000) >> 16)
74 #define SPR_FAMILY(spridr)              ((spridr & 0xFFF00000) >> 20)
75
76 #define SPR_8308                        0x8100
77 #define SPR_8309                        0x8110
78 #define SPR_831X_FAMILY                 0x80B
79 #define SPR_8311                        0x80B2
80 #define SPR_8313                        0x80B0
81 #define SPR_8314                        0x80B6
82 #define SPR_8315                        0x80B4
83 #define SPR_832X_FAMILY                 0x806
84 #define SPR_8321                        0x8066
85 #define SPR_8323                        0x8062
86 #define SPR_834X_FAMILY                 0x803
87 #define SPR_8343                        0x8036
88 #define SPR_8347_TBGA_                  0x8032
89 #define SPR_8347_PBGA_                  0x8034
90 #define SPR_8349                        0x8030
91 #define SPR_836X_FAMILY                 0x804
92 #define SPR_8358_TBGA_                  0x804A
93 #define SPR_8358_PBGA_                  0x804E
94 #define SPR_8360                        0x8048
95 #define SPR_837X_FAMILY                 0x80C
96 #define SPR_8377                        0x80C6
97 #define SPR_8378                        0x80C4
98 #define SPR_8379                        0x80C2
99
100 /*
101  * SPCR - System Priority Configuration Register
102  */
103 /* PCI Highest Priority Enable */
104 #define SPCR_PCIHPE                     0x10000000
105 #define SPCR_PCIHPE_SHIFT               (31-3)
106 /* PCI bridge system bus request priority */
107 #define SPCR_PCIPR                      0x03000000
108 #define SPCR_PCIPR_SHIFT                (31-7)
109 #define SPCR_OPT                        0x00800000      /* Optimize */
110 #define SPCR_OPT_SHIFT                  (31-8)
111 /* E300 PowerPC core time base unit enable */
112 #define SPCR_TBEN                       0x00400000
113 #define SPCR_TBEN_SHIFT                 (31-9)
114 /* E300 PowerPC Core system bus request priority */
115 #define SPCR_COREPR                     0x00300000
116 #define SPCR_COREPR_SHIFT               (31-11)
117
118 #if defined(CONFIG_MPC834x)
119 /* SPCR bits - MPC8349 specific */
120 /* TSEC1 data priority */
121 #define SPCR_TSEC1DP                    0x00003000
122 #define SPCR_TSEC1DP_SHIFT              (31-19)
123 /* TSEC1 buffer descriptor priority */
124 #define SPCR_TSEC1BDP                   0x00000C00
125 #define SPCR_TSEC1BDP_SHIFT             (31-21)
126 /* TSEC1 emergency priority */
127 #define SPCR_TSEC1EP                    0x00000300
128 #define SPCR_TSEC1EP_SHIFT              (31-23)
129 /* TSEC2 data priority */
130 #define SPCR_TSEC2DP                    0x00000030
131 #define SPCR_TSEC2DP_SHIFT              (31-27)
132 /* TSEC2 buffer descriptor priority */
133 #define SPCR_TSEC2BDP                   0x0000000C
134 #define SPCR_TSEC2BDP_SHIFT             (31-29)
135 /* TSEC2 emergency priority */
136 #define SPCR_TSEC2EP                    0x00000003
137 #define SPCR_TSEC2EP_SHIFT              (31-31)
138
139 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
140         defined(CONFIG_MPC837x)
141 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */
142 /* TSEC data priority */
143 #define SPCR_TSECDP                     0x00003000
144 #define SPCR_TSECDP_SHIFT               (31-19)
145 /* TSEC buffer descriptor priority */
146 #define SPCR_TSECBDP                    0x00000C00
147 #define SPCR_TSECBDP_SHIFT              (31-21)
148 /* TSEC emergency priority */
149 #define SPCR_TSECEP                     0x00000300
150 #define SPCR_TSECEP_SHIFT               (31-23)
151 #endif
152
153 /* SICRL/H - System I/O Configuration Register Low/High
154  */
155 #if defined(CONFIG_MPC834x)
156 /* SICRL bits - MPC8349 specific */
157 #define SICRL_LDP_A                     0x80000000
158 #define SICRL_USB1                      0x40000000
159 #define SICRL_USB0                      0x20000000
160 #define SICRL_UART                      0x0C000000
161 #define SICRL_GPIO1_A                   0x02000000
162 #define SICRL_GPIO1_B                   0x01000000
163 #define SICRL_GPIO1_C                   0x00800000
164 #define SICRL_GPIO1_D                   0x00400000
165 #define SICRL_GPIO1_E                   0x00200000
166 #define SICRL_GPIO1_F                   0x00180000
167 #define SICRL_GPIO1_G                   0x00040000
168 #define SICRL_GPIO1_H                   0x00020000
169 #define SICRL_GPIO1_I                   0x00010000
170 #define SICRL_GPIO1_J                   0x00008000
171 #define SICRL_GPIO1_K                   0x00004000
172 #define SICRL_GPIO1_L                   0x00003000
173
174 /* SICRH bits - MPC8349 specific */
175 #define SICRH_DDR                       0x80000000
176 #define SICRH_TSEC1_A                   0x10000000
177 #define SICRH_TSEC1_B                   0x08000000
178 #define SICRH_TSEC1_C                   0x04000000
179 #define SICRH_TSEC1_D                   0x02000000
180 #define SICRH_TSEC1_E                   0x01000000
181 #define SICRH_TSEC1_F                   0x00800000
182 #define SICRH_TSEC2_A                   0x00400000
183 #define SICRH_TSEC2_B                   0x00200000
184 #define SICRH_TSEC2_C                   0x00100000
185 #define SICRH_TSEC2_D                   0x00080000
186 #define SICRH_TSEC2_E                   0x00040000
187 #define SICRH_TSEC2_F                   0x00020000
188 #define SICRH_TSEC2_G                   0x00010000
189 #define SICRH_TSEC2_H                   0x00008000
190 #define SICRH_GPIO2_A                   0x00004000
191 #define SICRH_GPIO2_B                   0x00002000
192 #define SICRH_GPIO2_C                   0x00001000
193 #define SICRH_GPIO2_D                   0x00000800
194 #define SICRH_GPIO2_E                   0x00000400
195 #define SICRH_GPIO2_F                   0x00000200
196 #define SICRH_GPIO2_G                   0x00000180
197 #define SICRH_GPIO2_H                   0x00000060
198 #define SICRH_TSOBI1                    0x00000002
199 #define SICRH_TSOBI2                    0x00000001
200
201 #elif defined(CONFIG_MPC8360)
202 /* SICRL bits - MPC8360 specific */
203 #define SICRL_LDP_A                     0xC0000000
204 #define SICRL_LCLK_1                    0x10000000
205 #define SICRL_LCLK_2                    0x08000000
206 #define SICRL_SRCID_A                   0x03000000
207 #define SICRL_IRQ_CKSTP_A               0x00C00000
208
209 /* SICRH bits - MPC8360 specific */
210 #define SICRH_DDR                       0x80000000
211 #define SICRH_SECONDARY_DDR             0x40000000
212 #define SICRH_SDDROE                    0x20000000
213 #define SICRH_IRQ3                      0x10000000
214 #define SICRH_UC1EOBI                   0x00000004
215 #define SICRH_UC2E1OBI                  0x00000002
216 #define SICRH_UC2E2OBI                  0x00000001
217
218 #elif defined(CONFIG_MPC832x)
219 /* SICRL bits - MPC832x specific */
220 #define SICRL_LDP_LCS_A                 0x80000000
221 #define SICRL_IRQ_CKS                   0x20000000
222 #define SICRL_PCI_MSRC                  0x10000000
223 #define SICRL_URT_CTPR                  0x06000000
224 #define SICRL_IRQ_CTPR                  0x00C00000
225
226 #elif defined(CONFIG_MPC8313)
227 /* SICRL bits - MPC8313 specific */
228 #define SICRL_LBC                       0x30000000
229 #define SICRL_UART                      0x0C000000
230 #define SICRL_SPI_A                     0x03000000
231 #define SICRL_SPI_B                     0x00C00000
232 #define SICRL_SPI_C                     0x00300000
233 #define SICRL_SPI_D                     0x000C0000
234 #define SICRL_USBDR_11                  0x00000C00
235 #define SICRL_USBDR_10                  0x00000800
236 #define SICRL_USBDR_01                  0x00000400
237 #define SICRL_USBDR_00                  0x00000000
238 #define SICRL_ETSEC1_A                  0x0000000C
239 #define SICRL_ETSEC2_A                  0x00000003
240
241 /* SICRH bits - MPC8313 specific */
242 #define SICRH_INTR_A                    0x02000000
243 #define SICRH_INTR_B                    0x00C00000
244 #define SICRH_IIC                       0x00300000
245 #define SICRH_ETSEC2_B                  0x000C0000
246 #define SICRH_ETSEC2_C                  0x00030000
247 #define SICRH_ETSEC2_D                  0x0000C000
248 #define SICRH_ETSEC2_E                  0x00003000
249 #define SICRH_ETSEC2_F                  0x00000C00
250 #define SICRH_ETSEC2_G                  0x00000300
251 #define SICRH_ETSEC1_B                  0x00000080
252 #define SICRH_ETSEC1_C                  0x00000060
253 #define SICRH_GTX1_DLY                  0x00000008
254 #define SICRH_GTX2_DLY                  0x00000004
255 #define SICRH_TSOBI1                    0x00000002
256 #define SICRH_TSOBI2                    0x00000001
257
258 #elif defined(CONFIG_MPC8315)
259 /* SICRL bits - MPC8315 specific */
260 #define SICRL_DMA_CH0                   0xc0000000
261 #define SICRL_DMA_SPI                   0x30000000
262 #define SICRL_UART                      0x0c000000
263 #define SICRL_IRQ4                      0x02000000
264 #define SICRL_IRQ5                      0x01800000
265 #define SICRL_IRQ6_7                    0x00400000
266 #define SICRL_IIC1                      0x00300000
267 #define SICRL_TDM                       0x000c0000
268 #define SICRL_TDM_SHARED                0x00030000
269 #define SICRL_PCI_A                     0x0000c000
270 #define SICRL_ELBC_A                    0x00003000
271 #define SICRL_ETSEC1_A                  0x000000c0
272 #define SICRL_ETSEC1_B                  0x00000030
273 #define SICRL_ETSEC1_C                  0x0000000c
274 #define SICRL_TSEXPOBI                  0x00000001
275
276 /* SICRH bits - MPC8315 specific */
277 #define SICRH_GPIO_0                    0xc0000000
278 #define SICRH_GPIO_1                    0x30000000
279 #define SICRH_GPIO_2                    0x0c000000
280 #define SICRH_GPIO_3                    0x03000000
281 #define SICRH_GPIO_4                    0x00c00000
282 #define SICRH_GPIO_5                    0x00300000
283 #define SICRH_GPIO_6                    0x000c0000
284 #define SICRH_GPIO_7                    0x00030000
285 #define SICRH_GPIO_8                    0x0000c000
286 #define SICRH_GPIO_9                    0x00003000
287 #define SICRH_GPIO_10                   0x00000c00
288 #define SICRH_GPIO_11                   0x00000300
289 #define SICRH_ETSEC2_A                  0x000000c0
290 #define SICRH_TSOBI1                    0x00000002
291 #define SICRH_TSOBI2                    0x00000001
292
293 #elif defined(CONFIG_MPC837x)
294 /* SICRL bits - MPC837x specific */
295 #define SICRL_USB_A                     0xC0000000
296 #define SICRL_USB_B                     0x30000000
297 #define SICRL_USB_B_SD                  0x20000000
298 #define SICRL_UART                      0x0C000000
299 #define SICRL_GPIO_A                    0x02000000
300 #define SICRL_GPIO_B                    0x01000000
301 #define SICRL_GPIO_C                    0x00800000
302 #define SICRL_GPIO_D                    0x00400000
303 #define SICRL_GPIO_E                    0x00200000
304 #define SICRL_GPIO_F                    0x00180000
305 #define SICRL_GPIO_G                    0x00040000
306 #define SICRL_GPIO_H                    0x00020000
307 #define SICRL_GPIO_I                    0x00010000
308 #define SICRL_GPIO_J                    0x00008000
309 #define SICRL_GPIO_K                    0x00004000
310 #define SICRL_GPIO_L                    0x00003000
311 #define SICRL_DMA_A                     0x00000800
312 #define SICRL_DMA_B                     0x00000400
313 #define SICRL_DMA_C                     0x00000200
314 #define SICRL_DMA_D                     0x00000100
315 #define SICRL_DMA_E                     0x00000080
316 #define SICRL_DMA_F                     0x00000040
317 #define SICRL_DMA_G                     0x00000020
318 #define SICRL_DMA_H                     0x00000010
319 #define SICRL_DMA_I                     0x00000008
320 #define SICRL_DMA_J                     0x00000004
321 #define SICRL_LDP_A                     0x00000002
322 #define SICRL_LDP_B                     0x00000001
323
324 /* SICRH bits - MPC837x specific */
325 #define SICRH_DDR                       0x80000000
326 #define SICRH_TSEC1_A                   0x10000000
327 #define SICRH_TSEC1_B                   0x08000000
328 #define SICRH_TSEC2_A                   0x00400000
329 #define SICRH_TSEC2_B                   0x00200000
330 #define SICRH_TSEC2_C                   0x00100000
331 #define SICRH_TSEC2_D                   0x00080000
332 #define SICRH_TSEC2_E                   0x00040000
333 #define SICRH_TMR                       0x00010000
334 #define SICRH_GPIO2_A                   0x00008000
335 #define SICRH_GPIO2_B                   0x00004000
336 #define SICRH_GPIO2_C                   0x00002000
337 #define SICRH_GPIO2_D                   0x00001000
338 #define SICRH_GPIO2_E                   0x00000C00
339 #define SICRH_GPIO2_E_SD                0x00000800
340 #define SICRH_GPIO2_F                   0x00000300
341 #define SICRH_GPIO2_G                   0x000000C0
342 #define SICRH_GPIO2_H                   0x00000030
343 #define SICRH_SPI                       0x00000003
344 #define SICRH_SPI_SD                    0x00000001
345
346 #elif defined(CONFIG_MPC8308)
347 /* SICRL bits - MPC8308 specific */
348 #define SICRL_SPI_PF0                   (0 << 28)
349 #define SICRL_SPI_PF1                   (1 << 28)
350 #define SICRL_SPI_PF3                   (3 << 28)
351 #define SICRL_UART_PF0                  (0 << 26)
352 #define SICRL_UART_PF1                  (1 << 26)
353 #define SICRL_UART_PF3                  (3 << 26)
354 #define SICRL_IRQ_PF0                   (0 << 24)
355 #define SICRL_IRQ_PF1                   (1 << 24)
356 #define SICRL_I2C2_PF0                  (0 << 20)
357 #define SICRL_I2C2_PF1                  (1 << 20)
358 #define SICRL_ETSEC1_TX_CLK             (0 << 6)
359 #define SICRL_ETSEC1_GTX_CLK125         (1 << 6)
360
361 /* SICRH bits - MPC8308 specific */
362 #define SICRH_ESDHC_A_SD                (0 << 30)
363 #define SICRH_ESDHC_A_GTM               (1 << 30)
364 #define SICRH_ESDHC_A_GPIO              (3 << 30)
365 #define SICRH_ESDHC_B_SD                (0 << 28)
366 #define SICRH_ESDHC_B_GTM               (1 << 28)
367 #define SICRH_ESDHC_B_GPIO              (3 << 28)
368 #define SICRH_ESDHC_C_SD                (0 << 26)
369 #define SICRH_ESDHC_C_GTM               (1 << 26)
370 #define SICRH_ESDHC_C_GPIO              (3 << 26)
371 #define SICRH_GPIO_A_GPIO               (0 << 24)
372 #define SICRH_GPIO_A_TSEC2              (1 << 24)
373 #define SICRH_GPIO_B_GPIO               (0 << 22)
374 #define SICRH_GPIO_B_TSEC2_TX_CLK       (1 << 22)
375 #define SICRH_GPIO_B_TSEC2_GTX_CLK125   (2 << 22)
376 #define SICRH_IEEE1588_A_TMR            (1 << 20)
377 #define SICRH_IEEE1588_A_GPIO           (3 << 20)
378 #define SICRH_USB                       (1 << 18)
379 #define SICRH_GTM_GTM                   (1 << 16)
380 #define SICRH_GTM_GPIO                  (3 << 16)
381 #define SICRH_IEEE1588_B_TMR            (1 << 14)
382 #define SICRH_IEEE1588_B_GPIO           (3 << 14)
383 #define SICRH_ETSEC2_CRS                (1 << 12)
384 #define SICRH_ETSEC2_GPIO               (3 << 12)
385 #define SICRH_GPIOSEL_0                 (0 << 8)
386 #define SICRH_GPIOSEL_1                 (1 << 8)
387 #define SICRH_TMROBI_V3P3               (0 << 4)
388 #define SICRH_TMROBI_V2P5               (1 << 4)
389 #define SICRH_TSOBI1_V3P3               (0 << 1)
390 #define SICRH_TSOBI1_V2P5               (1 << 1)
391 #define SICRH_TSOBI2_V3P3               (0 << 0)
392 #define SICRH_TSOBI2_V2P5               (1 << 0)
393
394 #elif defined(CONFIG_MPC8309)
395 /* SICR_1 */
396 #define SICR_1_UART1_UART1S             (0 << (30-2))
397 #define SICR_1_UART1_UART1RTS           (1 << (30-2))
398 #define SICR_1_I2C_I2C                  (0 << (30-4))
399 #define SICR_1_I2C_CKSTOP               (1 << (30-4))
400 #define SICR_1_IRQ_A_IRQ                (0 << (30-6))
401 #define SICR_1_IRQ_A_MCP                (1 << (30-6))
402 #define SICR_1_IRQ_B_IRQ                (0 << (30-8))
403 #define SICR_1_IRQ_B_CKSTOP             (1 << (30-8))
404 #define SICR_1_GPIO_A_GPIO              (0 << (30-10))
405 #define SICR_1_GPIO_A_SD                (2 << (30-10))
406 #define SICR_1_GPIO_A_DDR               (3 << (30-10))
407 #define SICR_1_GPIO_B_GPIO              (0 << (30-12))
408 #define SICR_1_GPIO_B_SD                (2 << (30-12))
409 #define SICR_1_GPIO_B_QE                (3 << (30-12))
410 #define SICR_1_GPIO_C_GPIO              (0 << (30-14))
411 #define SICR_1_GPIO_C_CAN               (1 << (30-14))
412 #define SICR_1_GPIO_C_DDR               (2 << (30-14))
413 #define SICR_1_GPIO_C_LCS               (3 << (30-14))
414 #define SICR_1_GPIO_D_GPIO              (0 << (30-16))
415 #define SICR_1_GPIO_D_CAN               (1 << (30-16))
416 #define SICR_1_GPIO_D_DDR               (2 << (30-16))
417 #define SICR_1_GPIO_D_LCS               (3 << (30-16))
418 #define SICR_1_GPIO_E_GPIO              (0 << (30-18))
419 #define SICR_1_GPIO_E_CAN               (1 << (30-18))
420 #define SICR_1_GPIO_E_DDR               (2 << (30-18))
421 #define SICR_1_GPIO_E_LCS               (3 << (30-18))
422 #define SICR_1_GPIO_F_GPIO              (0 << (30-20))
423 #define SICR_1_GPIO_F_CAN               (1 << (30-20))
424 #define SICR_1_GPIO_F_CK                (2 << (30-20))
425 #define SICR_1_USB_A_USBDR              (0 << (30-22))
426 #define SICR_1_USB_A_UART2S             (1 << (30-22))
427 #define SICR_1_USB_B_USBDR              (0 << (30-24))
428 #define SICR_1_USB_B_UART2S             (1 << (30-24))
429 #define SICR_1_USB_B_UART2RTS           (2 << (30-24))
430 #define SICR_1_USB_C_USBDR              (0 << (30-26))
431 #define SICR_1_USB_C_QE_EXT             (3 << (30-26))
432 #define SICR_1_FEC1_FEC1                (0 << (30-28))
433 #define SICR_1_FEC1_GTM                 (1 << (30-28))
434 #define SICR_1_FEC1_GPIO                (2 << (30-28))
435 #define SICR_1_FEC2_FEC2                (0 << (30-30))
436 #define SICR_1_FEC2_GTM                 (1 << (30-30))
437 #define SICR_1_FEC2_GPIO                (2 << (30-30))
438 /* SICR_2 */
439 #define SICR_2_FEC3_FEC3                (0 << (30-0))
440 #define SICR_2_FEC3_TMR                 (1 << (30-0))
441 #define SICR_2_FEC3_GPIO                (2 << (30-0))
442 #define SICR_2_HDLC1_A_HDLC1            (0 << (30-2))
443 #define SICR_2_HDLC1_A_GPIO             (1 << (30-2))
444 #define SICR_2_HDLC1_A_TDM1             (2 << (30-2))
445 #define SICR_2_ELBC_A_LA                (0 << (30-4))
446 #define SICR_2_ELBC_B_LCLK              (0 << (30-6))
447 #define SICR_2_HDLC2_A_HDLC2            (0 << (30-8))
448 #define SICR_2_HDLC2_A_GPIO             (0 << (30-8))
449 #define SICR_2_HDLC2_A_TDM2             (0 << (30-8))
450 /* bits 10-11 unused */
451 #define SICR_2_USB_D_USBDR              (0 << (30-12))
452 #define SICR_2_USB_D_GPIO               (2 << (30-12))
453 #define SICR_2_USB_D_QE_BRG             (3 << (30-12))
454 #define SICR_2_PCI_PCI                  (0 << (30-14))
455 #define SICR_2_PCI_CPCI_HS              (2 << (30-14))
456 #define SICR_2_HDLC1_B_HDLC1            (0 << (30-16))
457 #define SICR_2_HDLC1_B_GPIO             (1 << (30-16))
458 #define SICR_2_HDLC1_B_QE_BRG           (2 << (30-16))
459 #define SICR_2_HDLC1_B_TDM1             (3 << (30-16))
460 #define SICR_2_HDLC1_C_HDLC1            (0 << (30-18))
461 #define SICR_2_HDLC1_C_GPIO             (1 << (30-18))
462 #define SICR_2_HDLC1_C_TDM1             (2 << (30-18))
463 #define SICR_2_HDLC2_B_HDLC2            (0 << (30-20))
464 #define SICR_2_HDLC2_B_GPIO             (1 << (30-20))
465 #define SICR_2_HDLC2_B_QE_BRG           (2 << (30-20))
466 #define SICR_2_HDLC2_B_TDM2             (3 << (30-20))
467 #define SICR_2_HDLC2_C_HDLC2            (0 << (30-22))
468 #define SICR_2_HDLC2_C_GPIO             (1 << (30-22))
469 #define SICR_2_HDLC2_C_TDM2             (2 << (30-22))
470 #define SICR_2_HDLC2_C_QE_BRG           (3 << (30-22))
471 #define SICR_2_QUIESCE_B                (0 << (30-24))
472
473 #endif
474
475 /*
476  * SWCRR - System Watchdog Control Register
477  */
478 /* Register offset to immr */
479 #define SWCRR                           0x0204
480 /* Software Watchdog Time Count */
481 #define SWCRR_SWTC                      0xFFFF0000
482 /* Watchdog Enable bit */
483 #define SWCRR_SWEN                      0x00000004
484 /* Software Watchdog Reset/Interrupt Select bit */
485 #define SWCRR_SWRI                      0x00000002
486 /* Software Watchdog Counter Prescale bit */
487 #define SWCRR_SWPR                      0x00000001
488 #define SWCRR_RES                       (~(SWCRR_SWTC | SWCRR_SWEN | \
489                                                 SWCRR_SWRI | SWCRR_SWPR))
490
491 /*
492  * SWCNR - System Watchdog Counter Register
493  */
494 /* Register offset to immr */
495 #define SWCNR                           0x0208
496 /* Software Watchdog Count mask */
497 #define SWCNR_SWCN                      0x0000FFFF
498 #define SWCNR_RES                       ~(SWCNR_SWCN)
499
500 /*
501  * SWSRR - System Watchdog Service Register
502  */
503 /* Register offset to immr */
504 #define SWSRR                           0x020E
505
506 /*
507  * ACR - Arbiter Configuration Register
508  */
509 #define ACR_COREDIS                     0x10000000      /* Core disable */
510 #define ACR_COREDIS_SHIFT               (31-7)
511 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
512 #define ACR_PIPE_DEP_SHIFT              (31-15)
513 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
514 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
515 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
516 #define ACR_RPTCNT_SHIFT                (31-23)
517 #define ACR_APARK                       0x00000030      /* Address parking */
518 #define ACR_APARK_SHIFT                 (31-27)
519 #define ACR_PARKM                       0x0000000F      /* Parking master */
520 #define ACR_PARKM_SHIFT                 (31-31)
521
522 /*
523  * ATR - Arbiter Timers Register
524  */
525 #define ATR_DTO                         0x00FF0000      /* Data time out */
526 #define ATR_DTO_SHIFT                   16
527 #define ATR_ATO                         0x000000FF      /* Address time out */
528 #define ATR_ATO_SHIFT                   0
529
530 /*
531  * AER - Arbiter Event Register
532  */
533 #define AER_ETEA                        0x00000020      /* Transfer error */
534 /* Reserved transfer type */
535 #define AER_RES                         0x00000010
536 /* External control word transfer type */
537 #define AER_ECW                         0x00000008
538 /* Address Only transfer type */
539 #define AER_AO                          0x00000004
540 #define AER_DTO                         0x00000002      /* Data time out */
541 #define AER_ATO                         0x00000001      /* Address time out */
542
543 /*
544  * AEATR - Arbiter Event Address Register
545  */
546 #define AEATR_EVENT                     0x07000000      /* Event type */
547 #define AEATR_EVENT_SHIFT               24
548 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
549 #define AEATR_MSTR_ID_SHIFT             16
550 #define AEATR_TBST                      0x00000800      /* Transfer burst */
551 #define AEATR_TBST_SHIFT                11
552 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
553 #define AEATR_TSIZE_SHIFT               8
554 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
555 #define AEATR_TTYPE_SHIFT               0
556
557 /*
558  * HRCWL - Hard Reset Configuration Word Low
559  */
560 #define HRCWL_LBIUCM                    0x80000000
561 #define HRCWL_LBIUCM_SHIFT              31
562 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1    0x00000000
563 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1    0x80000000
564
565 #define HRCWL_DDRCM                     0x40000000
566 #define HRCWL_DDRCM_SHIFT               30
567 #define HRCWL_DDR_TO_SCB_CLK_1X1        0x00000000
568 #define HRCWL_DDR_TO_SCB_CLK_2X1        0x40000000
569
570 #define HRCWL_SPMF                      0x0f000000
571 #define HRCWL_SPMF_SHIFT                24
572 #define HRCWL_CSB_TO_CLKIN_16X1         0x00000000
573 #define HRCWL_CSB_TO_CLKIN_1X1          0x01000000
574 #define HRCWL_CSB_TO_CLKIN_2X1          0x02000000
575 #define HRCWL_CSB_TO_CLKIN_3X1          0x03000000
576 #define HRCWL_CSB_TO_CLKIN_4X1          0x04000000
577 #define HRCWL_CSB_TO_CLKIN_5X1          0x05000000
578 #define HRCWL_CSB_TO_CLKIN_6X1          0x06000000
579 #define HRCWL_CSB_TO_CLKIN_7X1          0x07000000
580 #define HRCWL_CSB_TO_CLKIN_8X1          0x08000000
581 #define HRCWL_CSB_TO_CLKIN_9X1          0x09000000
582 #define HRCWL_CSB_TO_CLKIN_10X1         0x0A000000
583 #define HRCWL_CSB_TO_CLKIN_11X1         0x0B000000
584 #define HRCWL_CSB_TO_CLKIN_12X1         0x0C000000
585 #define HRCWL_CSB_TO_CLKIN_13X1         0x0D000000
586 #define HRCWL_CSB_TO_CLKIN_14X1         0x0E000000
587 #define HRCWL_CSB_TO_CLKIN_15X1         0x0F000000
588
589 #define HRCWL_VCO_BYPASS                0x00000000
590 #define HRCWL_VCO_1X2                   0x00000000
591 #define HRCWL_VCO_1X4                   0x00200000
592 #define HRCWL_VCO_1X8                   0x00400000
593
594 #define HRCWL_COREPLL                   0x007F0000
595 #define HRCWL_COREPLL_SHIFT             16
596 #define HRCWL_CORE_TO_CSB_BYPASS        0x00000000
597 #define HRCWL_CORE_TO_CSB_1X1           0x00020000
598 #define HRCWL_CORE_TO_CSB_1_5X1         0x00030000
599 #define HRCWL_CORE_TO_CSB_2X1           0x00040000
600 #define HRCWL_CORE_TO_CSB_2_5X1         0x00050000
601 #define HRCWL_CORE_TO_CSB_3X1           0x00060000
602
603 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
604 #define HRCWL_CEVCOD                    0x000000C0
605 #define HRCWL_CEVCOD_SHIFT              6
606 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000000
607 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000040
608 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000080
609
610 #define HRCWL_CEPDF                     0x00000020
611 #define HRCWL_CEPDF_SHIFT               5
612 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
613 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
614
615 #define HRCWL_CEPMF                     0x0000001F
616 #define HRCWL_CEPMF_SHIFT               0
617 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
618 #define HRCWL_CE_TO_PLL_1X2             0x00000002
619 #define HRCWL_CE_TO_PLL_1X3             0x00000003
620 #define HRCWL_CE_TO_PLL_1X4             0x00000004
621 #define HRCWL_CE_TO_PLL_1X5             0x00000005
622 #define HRCWL_CE_TO_PLL_1X6             0x00000006
623 #define HRCWL_CE_TO_PLL_1X7             0x00000007
624 #define HRCWL_CE_TO_PLL_1X8             0x00000008
625 #define HRCWL_CE_TO_PLL_1X9             0x00000009
626 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
627 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
628 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
629 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
630 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
631 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
632 #define HRCWL_CE_TO_PLL_1X16            0x00000010
633 #define HRCWL_CE_TO_PLL_1X17            0x00000011
634 #define HRCWL_CE_TO_PLL_1X18            0x00000012
635 #define HRCWL_CE_TO_PLL_1X19            0x00000013
636 #define HRCWL_CE_TO_PLL_1X20            0x00000014
637 #define HRCWL_CE_TO_PLL_1X21            0x00000015
638 #define HRCWL_CE_TO_PLL_1X22            0x00000016
639 #define HRCWL_CE_TO_PLL_1X23            0x00000017
640 #define HRCWL_CE_TO_PLL_1X24            0x00000018
641 #define HRCWL_CE_TO_PLL_1X25            0x00000019
642 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
643 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
644 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
645 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
646 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
647 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
648
649 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
650 #define HRCWL_SVCOD                     0x30000000
651 #define HRCWL_SVCOD_SHIFT               28
652 #define HRCWL_SVCOD_DIV_2               0x00000000
653 #define HRCWL_SVCOD_DIV_4               0x10000000
654 #define HRCWL_SVCOD_DIV_8               0x20000000
655 #define HRCWL_SVCOD_DIV_1               0x30000000
656
657 #elif defined(CONFIG_MPC837x)
658 #define HRCWL_SVCOD                     0x30000000
659 #define HRCWL_SVCOD_SHIFT               28
660 #define HRCWL_SVCOD_DIV_4               0x00000000
661 #define HRCWL_SVCOD_DIV_8               0x10000000
662 #define HRCWL_SVCOD_DIV_2               0x20000000
663 #define HRCWL_SVCOD_DIV_1               0x30000000
664 #elif defined(CONFIG_MPC8309)
665
666 #define HRCWL_CEVCOD                    0x000000C0
667 #define HRCWL_CEVCOD_SHIFT              6
668 /*
669  * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
670  * these are different than with 8360, 832x
671  */
672 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000000
673 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000040
674 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000080
675
676 #define HRCWL_CEPDF                     0x00000020
677 #define HRCWL_CEPDF_SHIFT               5
678 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
679 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
680
681 #define HRCWL_CEPMF                     0x0000001F
682 #define HRCWL_CEPMF_SHIFT               0
683 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
684 #define HRCWL_CE_TO_PLL_1X2             0x00000002
685 #define HRCWL_CE_TO_PLL_1X3             0x00000003
686 #define HRCWL_CE_TO_PLL_1X4             0x00000004
687 #define HRCWL_CE_TO_PLL_1X5             0x00000005
688 #define HRCWL_CE_TO_PLL_1X6             0x00000006
689 #define HRCWL_CE_TO_PLL_1X7             0x00000007
690 #define HRCWL_CE_TO_PLL_1X8             0x00000008
691 #define HRCWL_CE_TO_PLL_1X9             0x00000009
692 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
693 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
694 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
695 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
696 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
697 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
698 #define HRCWL_CE_TO_PLL_1X16            0x00000010
699 #define HRCWL_CE_TO_PLL_1X17            0x00000011
700 #define HRCWL_CE_TO_PLL_1X18            0x00000012
701 #define HRCWL_CE_TO_PLL_1X19            0x00000013
702 #define HRCWL_CE_TO_PLL_1X20            0x00000014
703 #define HRCWL_CE_TO_PLL_1X21            0x00000015
704 #define HRCWL_CE_TO_PLL_1X22            0x00000016
705 #define HRCWL_CE_TO_PLL_1X23            0x00000017
706 #define HRCWL_CE_TO_PLL_1X24            0x00000018
707 #define HRCWL_CE_TO_PLL_1X25            0x00000019
708 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
709 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
710 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
711 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
712 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
713 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
714
715 #define HRCWL_SVCOD                     0x30000000
716 #define HRCWL_SVCOD_SHIFT               28
717 #define HRCWL_SVCOD_DIV_2               0x00000000
718 #define HRCWL_SVCOD_DIV_4               0x10000000
719 #define HRCWL_SVCOD_DIV_8               0x20000000
720 #define HRCWL_SVCOD_DIV_1               0x30000000
721 #endif
722
723 /*
724  * HRCWH - Hardware Reset Configuration Word High
725  */
726 #define HRCWH_PCI_HOST                  0x80000000
727 #define HRCWH_PCI_HOST_SHIFT            31
728 #define HRCWH_PCI_AGENT                 0x00000000
729
730 #if defined(CONFIG_MPC834x)
731 #define HRCWH_32_BIT_PCI                0x00000000
732 #define HRCWH_64_BIT_PCI                0x40000000
733 #endif
734
735 #define HRCWH_PCI1_ARBITER_DISABLE      0x00000000
736 #define HRCWH_PCI1_ARBITER_ENABLE       0x20000000
737
738 #define HRCWH_PCI_ARBITER_DISABLE       0x00000000
739 #define HRCWH_PCI_ARBITER_ENABLE        0x20000000
740
741 #if defined(CONFIG_MPC834x)
742 #define HRCWH_PCI2_ARBITER_DISABLE      0x00000000
743 #define HRCWH_PCI2_ARBITER_ENABLE       0x10000000
744
745 #elif defined(CONFIG_MPC8360)
746 #define HRCWH_PCICKDRV_DISABLE          0x00000000
747 #define HRCWH_PCICKDRV_ENABLE           0x10000000
748 #endif
749
750 #define HRCWH_CORE_DISABLE              0x08000000
751 #define HRCWH_CORE_ENABLE               0x00000000
752
753 #define HRCWH_FROM_0X00000100           0x00000000
754 #define HRCWH_FROM_0XFFF00100           0x04000000
755
756 #define HRCWH_BOOTSEQ_DISABLE           0x00000000
757 #define HRCWH_BOOTSEQ_NORMAL            0x01000000
758 #define HRCWH_BOOTSEQ_EXTENDED          0x02000000
759
760 #define HRCWH_SW_WATCHDOG_DISABLE       0x00000000
761 #define HRCWH_SW_WATCHDOG_ENABLE        0x00800000
762
763 #define HRCWH_ROM_LOC_DDR_SDRAM         0x00000000
764 #define HRCWH_ROM_LOC_PCI1              0x00100000
765 #if defined(CONFIG_MPC834x)
766 #define HRCWH_ROM_LOC_PCI2              0x00200000
767 #endif
768 #if defined(CONFIG_MPC837x)
769 #define HRCWH_ROM_LOC_ON_CHIP_ROM       0x00300000
770 #endif
771 #define HRCWH_ROM_LOC_LOCAL_8BIT        0x00500000
772 #define HRCWH_ROM_LOC_LOCAL_16BIT       0x00600000
773 #define HRCWH_ROM_LOC_LOCAL_32BIT       0x00700000
774
775 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
776         defined(CONFIG_MPC837x)
777 #define HRCWH_ROM_LOC_NAND_SP_8BIT      0x00100000
778 #define HRCWH_ROM_LOC_NAND_SP_16BIT     0x00200000
779 #define HRCWH_ROM_LOC_NAND_LP_8BIT      0x00500000
780 #define HRCWH_ROM_LOC_NAND_LP_16BIT     0x00600000
781
782 #define HRCWH_RL_EXT_LEGACY             0x00000000
783 #define HRCWH_RL_EXT_NAND               0x00040000
784
785 #define HRCWH_TSEC1M_MASK               0x0000E000
786 #define HRCWH_TSEC1M_IN_MII             0x00000000
787 #define HRCWH_TSEC1M_IN_RMII            0x00002000
788 #define HRCWH_TSEC1M_IN_RGMII           0x00006000
789 #define HRCWH_TSEC1M_IN_RTBI            0x0000A000
790 #define HRCWH_TSEC1M_IN_SGMII           0x0000C000
791
792 #define HRCWH_TSEC2M_MASK               0x00001C00
793 #define HRCWH_TSEC2M_IN_MII             0x00000000
794 #define HRCWH_TSEC2M_IN_RMII            0x00000400
795 #define HRCWH_TSEC2M_IN_RGMII           0x00000C00
796 #define HRCWH_TSEC2M_IN_RTBI            0x00001400
797 #define HRCWH_TSEC2M_IN_SGMII           0x00001800
798 #endif
799
800 #if defined(CONFIG_MPC834x)
801 #define HRCWH_TSEC1M_IN_RGMII           0x00000000
802 #define HRCWH_TSEC1M_IN_RTBI            0x00004000
803 #define HRCWH_TSEC1M_IN_GMII            0x00008000
804 #define HRCWH_TSEC1M_IN_TBI             0x0000C000
805 #define HRCWH_TSEC2M_IN_RGMII           0x00000000
806 #define HRCWH_TSEC2M_IN_RTBI            0x00001000
807 #define HRCWH_TSEC2M_IN_GMII            0x00002000
808 #define HRCWH_TSEC2M_IN_TBI             0x00003000
809 #endif
810
811 #if defined(CONFIG_MPC8360)
812 #define HRCWH_SECONDARY_DDR_DISABLE     0x00000000
813 #define HRCWH_SECONDARY_DDR_ENABLE      0x00000010
814 #endif
815
816 #define HRCWH_BIG_ENDIAN                0x00000000
817 #define HRCWH_LITTLE_ENDIAN             0x00000008
818
819 #define HRCWH_LALE_NORMAL               0x00000000
820 #define HRCWH_LALE_EARLY                0x00000004
821
822 #define HRCWH_LDP_SET                   0x00000000
823 #define HRCWH_LDP_CLEAR                 0x00000002
824
825 /*
826  * RSR - Reset Status Register
827  */
828 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
829         defined(CONFIG_MPC837x)
830 #define RSR_RSTSRC                      0xF0000000      /* Reset source */
831 #define RSR_RSTSRC_SHIFT                28
832 #else
833 #define RSR_RSTSRC                      0xE0000000      /* Reset source */
834 #define RSR_RSTSRC_SHIFT                29
835 #endif
836 #define RSR_BSF                         0x00010000      /* Boot seq. fail */
837 #define RSR_BSF_SHIFT                   16
838 /* software soft reset */
839 #define RSR_SWSR                        0x00002000
840 #define RSR_SWSR_SHIFT                  13
841 /* software hard reset */
842 #define RSR_SWHR                        0x00001000
843 #define RSR_SWHR_SHIFT                  12
844 #define RSR_JHRS                        0x00000200      /* jtag hreset */
845 #define RSR_JHRS_SHIFT                  9
846 /* jtag sreset status */
847 #define RSR_JSRS                        0x00000100
848 #define RSR_JSRS_SHIFT                  8
849 /* checkstop reset status */
850 #define RSR_CSHR                        0x00000010
851 #define RSR_CSHR_SHIFT                  4
852 /* software watchdog reset status */
853 #define RSR_SWRS                        0x00000008
854 #define RSR_SWRS_SHIFT                  3
855 /* bus monitop reset status */
856 #define RSR_BMRS                        0x00000004
857 #define RSR_BMRS_SHIFT                  2
858 #define RSR_SRS                         0x00000002      /* soft reset status */
859 #define RSR_SRS_SHIFT                   1
860 #define RSR_HRS                         0x00000001      /* hard reset status */
861 #define RSR_HRS_SHIFT                   0
862 #define RSR_RES                         (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
863                                                 RSR_SWHR | RSR_JHRS | \
864                                                 RSR_JSRS | RSR_CSHR | \
865                                                 RSR_SWRS | RSR_BMRS | \
866                                                 RSR_SRS | RSR_HRS))
867 /*
868  * RMR - Reset Mode Register
869  */
870 /* checkstop reset enable */
871 #define RMR_CSRE                        0x00000001
872 #define RMR_CSRE_SHIFT                  0
873 #define RMR_RES                         ~(RMR_CSRE)
874
875 /*
876  * RCR - Reset Control Register
877  */
878 /* software hard reset */
879 #define RCR_SWHR                        0x00000002
880 /* software soft reset */
881 #define RCR_SWSR                        0x00000001
882 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
883
884 /*
885  * RCER - Reset Control Enable Register
886  */
887 /* software hard reset */
888 #define RCER_CRE                        0x00000001
889 #define RCER_RES                        ~(RCER_CRE)
890
891 /*
892  * SPMR - System PLL Mode Register
893  */
894 #define SPMR_LBIUCM                     0x80000000
895 #define SPMR_LBIUCM_SHIFT               31
896 #define SPMR_DDRCM                      0x40000000
897 #define SPMR_DDRCM_SHIFT                30
898 #define SPMR_SPMF                       0x0F000000
899 #define SPMR_SPMF_SHIFT         24
900 #define SPMR_CKID                       0x00800000
901 #define SPMR_CKID_SHIFT                 23
902 #define SPMR_COREPLL                    0x007F0000
903 #define SPMR_COREPLL_SHIFT              16
904 #define SPMR_CEVCOD                     0x000000C0
905 #define SPMR_CEVCOD_SHIFT               6
906 #define SPMR_CEPDF                      0x00000020
907 #define SPMR_CEPDF_SHIFT                5
908 #define SPMR_CEPMF                      0x0000001F
909 #define SPMR_CEPMF_SHIFT                0
910
911 /*
912  * OCCR - Output Clock Control Register
913  */
914 #define OCCR_PCICOE0                    0x80000000
915 #define OCCR_PCICOE1                    0x40000000
916 #define OCCR_PCICOE2                    0x20000000
917 #define OCCR_PCICOE3                    0x10000000
918 #define OCCR_PCICOE4                    0x08000000
919 #define OCCR_PCICOE5                    0x04000000
920 #define OCCR_PCICOE6                    0x02000000
921 #define OCCR_PCICOE7                    0x01000000
922 #define OCCR_PCICD0                     0x00800000
923 #define OCCR_PCICD1                     0x00400000
924 #define OCCR_PCICD2                     0x00200000
925 #define OCCR_PCICD3                     0x00100000
926 #define OCCR_PCICD4                     0x00080000
927 #define OCCR_PCICD5                     0x00040000
928 #define OCCR_PCICD6                     0x00020000
929 #define OCCR_PCICD7                     0x00010000
930 #define OCCR_PCI1CR                     0x00000002
931 #define OCCR_PCI2CR                     0x00000001
932 #define OCCR_PCICR                      OCCR_PCI1CR
933
934 /*
935  * SCCR - System Clock Control Register
936  */
937 #define SCCR_ENCCM                      0x03000000
938 #define SCCR_ENCCM_SHIFT                24
939 #define SCCR_ENCCM_0                    0x00000000
940 #define SCCR_ENCCM_1                    0x01000000
941 #define SCCR_ENCCM_2                    0x02000000
942 #define SCCR_ENCCM_3                    0x03000000
943
944 #define SCCR_PCICM                      0x00010000
945 #define SCCR_PCICM_SHIFT                16
946
947 #if defined(CONFIG_MPC834x)
948 /* SCCR bits - MPC834x specific */
949 #define SCCR_TSEC1CM                    0xc0000000
950 #define SCCR_TSEC1CM_SHIFT              30
951 #define SCCR_TSEC1CM_0                  0x00000000
952 #define SCCR_TSEC1CM_1                  0x40000000
953 #define SCCR_TSEC1CM_2                  0x80000000
954 #define SCCR_TSEC1CM_3                  0xC0000000
955
956 #define SCCR_TSEC2CM                    0x30000000
957 #define SCCR_TSEC2CM_SHIFT              28
958 #define SCCR_TSEC2CM_0                  0x00000000
959 #define SCCR_TSEC2CM_1                  0x10000000
960 #define SCCR_TSEC2CM_2                  0x20000000
961 #define SCCR_TSEC2CM_3                  0x30000000
962
963 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
964 #define SCCR_USBMPHCM                   0x00c00000
965 #define SCCR_USBMPHCM_SHIFT             22
966 #define SCCR_USBDRCM                    0x00300000
967 #define SCCR_USBDRCM_SHIFT              20
968 #define SCCR_USBCM                      0x00f00000
969 #define SCCR_USBCM_SHIFT                20
970 #define SCCR_USBCM_0                    0x00000000
971 #define SCCR_USBCM_1                    0x00500000
972 #define SCCR_USBCM_2                    0x00A00000
973 #define SCCR_USBCM_3                    0x00F00000
974
975 #elif defined(CONFIG_MPC8313)
976 /* TSEC1 bits are for TSEC2 as well */
977 #define SCCR_TSEC1CM                    0xc0000000
978 #define SCCR_TSEC1CM_SHIFT              30
979 #define SCCR_TSEC1CM_0                  0x00000000
980 #define SCCR_TSEC1CM_1                  0x40000000
981 #define SCCR_TSEC1CM_2                  0x80000000
982 #define SCCR_TSEC1CM_3                  0xC0000000
983
984 #define SCCR_TSEC1ON                    0x20000000
985 #define SCCR_TSEC1ON_SHIFT              29
986 #define SCCR_TSEC2ON                    0x10000000
987 #define SCCR_TSEC2ON_SHIFT              28
988
989 #define SCCR_USBDRCM                    0x00300000
990 #define SCCR_USBDRCM_SHIFT              20
991 #define SCCR_USBDRCM_0                  0x00000000
992 #define SCCR_USBDRCM_1                  0x00100000
993 #define SCCR_USBDRCM_2                  0x00200000
994 #define SCCR_USBDRCM_3                  0x00300000
995
996 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
997 /* SCCR bits - MPC8315/MPC8308 specific */
998 #define SCCR_TSEC1CM                    0xc0000000
999 #define SCCR_TSEC1CM_SHIFT              30
1000 #define SCCR_TSEC1CM_0                  0x00000000
1001 #define SCCR_TSEC1CM_1                  0x40000000
1002 #define SCCR_TSEC1CM_2                  0x80000000
1003 #define SCCR_TSEC1CM_3                  0xC0000000
1004
1005 #define SCCR_TSEC2CM                    0x30000000
1006 #define SCCR_TSEC2CM_SHIFT              28
1007 #define SCCR_TSEC2CM_0                  0x00000000
1008 #define SCCR_TSEC2CM_1                  0x10000000
1009 #define SCCR_TSEC2CM_2                  0x20000000
1010 #define SCCR_TSEC2CM_3                  0x30000000
1011
1012 #define SCCR_SDHCCM                     0x0c000000
1013 #define SCCR_SDHCCM_SHIFT               26
1014 #define SCCR_SDHCCM_0                   0x00000000
1015 #define SCCR_SDHCCM_1                   0x04000000
1016 #define SCCR_SDHCCM_2                   0x08000000
1017 #define SCCR_SDHCCM_3                   0x0c000000
1018
1019 #define SCCR_USBDRCM                    0x00c00000
1020 #define SCCR_USBDRCM_SHIFT              22
1021 #define SCCR_USBDRCM_0                  0x00000000
1022 #define SCCR_USBDRCM_1                  0x00400000
1023 #define SCCR_USBDRCM_2                  0x00800000
1024 #define SCCR_USBDRCM_3                  0x00c00000
1025
1026 #define SCCR_SATA1CM                    0x00003000
1027 #define SCCR_SATA1CM_SHIFT              12
1028 #define SCCR_SATACM                     0x00003c00
1029 #define SCCR_SATACM_SHIFT               10
1030 #define SCCR_SATACM_0                   0x00000000
1031 #define SCCR_SATACM_1                   0x00001400
1032 #define SCCR_SATACM_2                   0x00002800
1033 #define SCCR_SATACM_3                   0x00003c00
1034
1035 #define SCCR_TDMCM                      0x00000030
1036 #define SCCR_TDMCM_SHIFT                4
1037 #define SCCR_TDMCM_0                    0x00000000
1038 #define SCCR_TDMCM_1                    0x00000010
1039 #define SCCR_TDMCM_2                    0x00000020
1040 #define SCCR_TDMCM_3                    0x00000030
1041
1042 #elif defined(CONFIG_MPC837x)
1043 /* SCCR bits - MPC837x specific */
1044 #define SCCR_TSEC1CM                    0xc0000000
1045 #define SCCR_TSEC1CM_SHIFT              30
1046 #define SCCR_TSEC1CM_0                  0x00000000
1047 #define SCCR_TSEC1CM_1                  0x40000000
1048 #define SCCR_TSEC1CM_2                  0x80000000
1049 #define SCCR_TSEC1CM_3                  0xC0000000
1050
1051 #define SCCR_TSEC2CM                    0x30000000
1052 #define SCCR_TSEC2CM_SHIFT              28
1053 #define SCCR_TSEC2CM_0                  0x00000000
1054 #define SCCR_TSEC2CM_1                  0x10000000
1055 #define SCCR_TSEC2CM_2                  0x20000000
1056 #define SCCR_TSEC2CM_3                  0x30000000
1057
1058 #define SCCR_SDHCCM                     0x0c000000
1059 #define SCCR_SDHCCM_SHIFT               26
1060 #define SCCR_SDHCCM_0                   0x00000000
1061 #define SCCR_SDHCCM_1                   0x04000000
1062 #define SCCR_SDHCCM_2                   0x08000000
1063 #define SCCR_SDHCCM_3                   0x0c000000
1064
1065 #define SCCR_USBDRCM                    0x00c00000
1066 #define SCCR_USBDRCM_SHIFT              22
1067 #define SCCR_USBDRCM_0                  0x00000000
1068 #define SCCR_USBDRCM_1                  0x00400000
1069 #define SCCR_USBDRCM_2                  0x00800000
1070 #define SCCR_USBDRCM_3                  0x00c00000
1071
1072 /* All of the four SATA controllers must have the same clock ratio */
1073 #define SCCR_SATA1CM                    0x000000c0
1074 #define SCCR_SATA1CM_SHIFT              6
1075 #define SCCR_SATACM                     0x000000ff
1076 #define SCCR_SATACM_SHIFT               0
1077 #define SCCR_SATACM_0                   0x00000000
1078 #define SCCR_SATACM_1                   0x00000055
1079 #define SCCR_SATACM_2                   0x000000aa
1080 #define SCCR_SATACM_3                   0x000000ff
1081 #elif defined(CONFIG_MPC8309)
1082 /* SCCR bits - MPC8309 specific */
1083 #define SCCR_SDHCCM                     0x0c000000
1084 #define SCCR_SDHCCM_SHIFT               26
1085 #define SCCR_SDHCCM_0                   0x00000000
1086 #define SCCR_SDHCCM_1                   0x04000000
1087 #define SCCR_SDHCCM_2                   0x08000000
1088 #define SCCR_SDHCCM_3                   0x0c000000
1089
1090 #define SCCR_USBDRCM                    0x00c00000
1091 #define SCCR_USBDRCM_SHIFT              22
1092 #define SCCR_USBDRCM_0                  0x00000000
1093 #define SCCR_USBDRCM_1                  0x00400000
1094 #define SCCR_USBDRCM_2                  0x00800000
1095 #define SCCR_USBDRCM_3                  0x00c00000
1096 #endif
1097
1098 #define SCCR_PCIEXP1CM                  0x00300000
1099 #define SCCR_PCIEXP1CM_SHIFT            20
1100 #define SCCR_PCIEXP1CM_0                0x00000000
1101 #define SCCR_PCIEXP1CM_1                0x00100000
1102 #define SCCR_PCIEXP1CM_2                0x00200000
1103 #define SCCR_PCIEXP1CM_3                0x00300000
1104
1105 #define SCCR_PCIEXP2CM                  0x000c0000
1106 #define SCCR_PCIEXP2CM_SHIFT            18
1107 #define SCCR_PCIEXP2CM_0                0x00000000
1108 #define SCCR_PCIEXP2CM_1                0x00040000
1109 #define SCCR_PCIEXP2CM_2                0x00080000
1110 #define SCCR_PCIEXP2CM_3                0x000c0000
1111
1112 /*
1113  * CSn_BDNS - Chip Select memory Bounds Register
1114  */
1115 #define CSBNDS_SA                       0x00FF0000
1116 #define CSBNDS_SA_SHIFT                 8
1117 #define CSBNDS_EA                       0x000000FF
1118 #define CSBNDS_EA_SHIFT                 24
1119
1120 /*
1121  * CSn_CONFIG - Chip Select Configuration Register
1122  */
1123 #define CSCONFIG_EN                     0x80000000
1124 #define CSCONFIG_AP                     0x00800000
1125 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
1126 #define CSCONFIG_ODT_RD_NEVER           0x00000000
1127 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
1128 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
1129 #define CSCONFIG_ODT_RD_ALL             0x00400000
1130 #define CSCONFIG_ODT_WR_NEVER           0x00000000
1131 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
1132 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
1133 #define CSCONFIG_ODT_WR_ALL             0x00040000
1134 #elif defined(CONFIG_MPC832x)
1135 #define CSCONFIG_ODT_RD_CFG             0x00400000
1136 #define CSCONFIG_ODT_WR_CFG             0x00040000
1137 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
1138 #define CSCONFIG_ODT_RD_NEVER           0x00000000
1139 #define CSCONFIG_ODT_RD_ONLY_CURRENT    0x00100000
1140 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS   0x00200000
1141 #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
1142 #define CSCONFIG_ODT_RD_ALL             0x00400000
1143 #define CSCONFIG_ODT_WR_NEVER           0x00000000
1144 #define CSCONFIG_ODT_WR_ONLY_CURRENT    0x00010000
1145 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS   0x00020000
1146 #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
1147 #define CSCONFIG_ODT_WR_ALL             0x00040000
1148 #endif
1149 #define CSCONFIG_BANK_BIT_3             0x00004000
1150 #define CSCONFIG_ROW_BIT                0x00000700
1151 #define CSCONFIG_ROW_BIT_12             0x00000000
1152 #define CSCONFIG_ROW_BIT_13             0x00000100
1153 #define CSCONFIG_ROW_BIT_14             0x00000200
1154 #define CSCONFIG_COL_BIT                0x00000007
1155 #define CSCONFIG_COL_BIT_8              0x00000000
1156 #define CSCONFIG_COL_BIT_9              0x00000001
1157 #define CSCONFIG_COL_BIT_10             0x00000002
1158 #define CSCONFIG_COL_BIT_11             0x00000003
1159
1160 /*
1161  * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
1162  */
1163 #define TIMING_CFG0_RWT                 0xC0000000
1164 #define TIMING_CFG0_RWT_SHIFT           30
1165 #define TIMING_CFG0_WRT                 0x30000000
1166 #define TIMING_CFG0_WRT_SHIFT           28
1167 #define TIMING_CFG0_RRT                 0x0C000000
1168 #define TIMING_CFG0_RRT_SHIFT           26
1169 #define TIMING_CFG0_WWT                 0x03000000
1170 #define TIMING_CFG0_WWT_SHIFT           24
1171 #define TIMING_CFG0_ACT_PD_EXIT         0x00700000
1172 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT   20
1173 #define TIMING_CFG0_PRE_PD_EXIT         0x00070000
1174 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT   16
1175 #define TIMING_CFG0_ODT_PD_EXIT         0x00000F00
1176 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT   8
1177 #define TIMING_CFG0_MRS_CYC             0x0000000F
1178 #define TIMING_CFG0_MRS_CYC_SHIFT       0
1179
1180 /*
1181  * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
1182  */
1183 #define TIMING_CFG1_PRETOACT            0x70000000
1184 #define TIMING_CFG1_PRETOACT_SHIFT      28
1185 #define TIMING_CFG1_ACTTOPRE            0x0F000000
1186 #define TIMING_CFG1_ACTTOPRE_SHIFT      24
1187 #define TIMING_CFG1_ACTTORW             0x00700000
1188 #define TIMING_CFG1_ACTTORW_SHIFT       20
1189 #define TIMING_CFG1_CASLAT              0x00070000
1190 #define TIMING_CFG1_CASLAT_SHIFT        16
1191 #define TIMING_CFG1_REFREC              0x0000F000
1192 #define TIMING_CFG1_REFREC_SHIFT        12
1193 #define TIMING_CFG1_WRREC               0x00000700
1194 #define TIMING_CFG1_WRREC_SHIFT         8
1195 #define TIMING_CFG1_ACTTOACT            0x00000070
1196 #define TIMING_CFG1_ACTTOACT_SHIFT      4
1197 #define TIMING_CFG1_WRTORD              0x00000007
1198 #define TIMING_CFG1_WRTORD_SHIFT        0
1199 #define TIMING_CFG1_CASLAT_20           0x00030000      /* CAS latency = 2.0 */
1200 #define TIMING_CFG1_CASLAT_25           0x00040000      /* CAS latency = 2.5 */
1201 #define TIMING_CFG1_CASLAT_30           0x00050000      /* CAS latency = 3.0 */
1202 #define TIMING_CFG1_CASLAT_35           0x00060000      /* CAS latency = 3.5 */
1203 #define TIMING_CFG1_CASLAT_40           0x00070000      /* CAS latency = 4.0 */
1204 #define TIMING_CFG1_CASLAT_45           0x00080000      /* CAS latency = 4.5 */
1205 #define TIMING_CFG1_CASLAT_50           0x00090000      /* CAS latency = 5.0 */
1206
1207 /*
1208  * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
1209  */
1210 #define TIMING_CFG2_CPO                 0x0F800000
1211 #define TIMING_CFG2_CPO_SHIFT           23
1212 #define TIMING_CFG2_ACSM                0x00080000
1213 #define TIMING_CFG2_WR_DATA_DELAY       0x00001C00
1214 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
1215 /* default (= CASLAT + 1) */
1216 #define TIMING_CFG2_CPO_DEF             0x00000000
1217
1218 #define TIMING_CFG2_ADD_LAT             0x70000000
1219 #define TIMING_CFG2_ADD_LAT_SHIFT       28
1220 #define TIMING_CFG2_WR_LAT_DELAY        0x00380000
1221 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT  19
1222 #define TIMING_CFG2_RD_TO_PRE           0x0000E000
1223 #define TIMING_CFG2_RD_TO_PRE_SHIFT     13
1224 #define TIMING_CFG2_CKE_PLS             0x000001C0
1225 #define TIMING_CFG2_CKE_PLS_SHIFT       6
1226 #define TIMING_CFG2_FOUR_ACT            0x0000003F
1227 #define TIMING_CFG2_FOUR_ACT_SHIFT      0
1228
1229 /*
1230  * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1231  */
1232 #define TIMING_CFG3_EXT_REFREC          0x00070000
1233 #define TIMING_CFG3_EXT_REFREC_SHIFT    16
1234
1235 /*
1236  * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
1237  */
1238 #define SDRAM_CFG_MEM_EN                0x80000000
1239 #define SDRAM_CFG_SREN                  0x40000000
1240 #define SDRAM_CFG_ECC_EN                0x20000000
1241 #define SDRAM_CFG_RD_EN                 0x10000000
1242 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
1243 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
1244 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
1245 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
1246 #define SDRAM_CFG_DYN_PWR               0x00200000
1247 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
1248 #define SDRAM_CFG_DBW_MASK              0x00180000
1249 #define SDRAM_CFG_DBW_16                0x00100000
1250 #define SDRAM_CFG_DBW_32                0x00080000
1251 #else
1252 #define SDRAM_CFG_32_BE                 0x00080000
1253 #endif
1254 #if !defined(CONFIG_MPC8308)
1255 #define SDRAM_CFG_8_BE                  0x00040000
1256 #endif
1257 #define SDRAM_CFG_NCAP                  0x00020000
1258 #define SDRAM_CFG_2T_EN                 0x00008000
1259 #define SDRAM_CFG_HSE                   0x00000008
1260 #define SDRAM_CFG_BI                    0x00000001
1261
1262 /*
1263  * DDR_SDRAM_MODE - DDR SDRAM Mode Register
1264  */
1265 #define SDRAM_MODE_ESD                  0xFFFF0000
1266 #define SDRAM_MODE_ESD_SHIFT            16
1267 #define SDRAM_MODE_SD                   0x0000FFFF
1268 #define SDRAM_MODE_SD_SHIFT             0
1269 /* select extended mode reg */
1270 #define DDR_MODE_EXT_MODEREG            0x4000
1271 /* operating mode, mask */
1272 #define DDR_MODE_EXT_OPMODE             0x3FF8
1273 #define DDR_MODE_EXT_OP_NORMAL          0x0000          /* normal operation */
1274 /* QFC / compatibility, mask */
1275 #define DDR_MODE_QFC                    0x0004
1276 /* compatible to older SDRAMs */
1277 #define DDR_MODE_QFC_COMP               0x0000
1278 /* weak drivers */
1279 #define DDR_MODE_WEAK                   0x0002
1280 /* disable DLL */
1281 #define DDR_MODE_DLL_DIS                0x0001
1282 /* CAS latency, mask */
1283 #define DDR_MODE_CASLAT                 0x0070
1284 #define DDR_MODE_CASLAT_15              0x0010          /* CAS latency 1.5 */
1285 #define DDR_MODE_CASLAT_20              0x0020          /* CAS latency 2 */
1286 #define DDR_MODE_CASLAT_25              0x0060          /* CAS latency 2.5 */
1287 #define DDR_MODE_CASLAT_30              0x0030          /* CAS latency 3 */
1288 /* sequential burst */
1289 #define DDR_MODE_BTYPE_SEQ              0x0000
1290 /* interleaved burst */
1291 #define DDR_MODE_BTYPE_ILVD             0x0008
1292 #define DDR_MODE_BLEN_2                 0x0001          /* burst length 2 */
1293 #define DDR_MODE_BLEN_4                 0x0002          /* burst length 4 */
1294 /* exact value for 7.8125us */
1295 #define DDR_REFINT_166MHZ_7US           1302
1296 /* use 256 cycles as a starting point */
1297 #define DDR_BSTOPRE                     256
1298 /* select mode register */
1299 #define DDR_MODE_MODEREG                0x0000
1300
1301 /*
1302  * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
1303  */
1304 #define SDRAM_INTERVAL_REFINT           0x3FFF0000
1305 #define SDRAM_INTERVAL_REFINT_SHIFT     16
1306 #define SDRAM_INTERVAL_BSTOPRE          0x00003FFF
1307 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
1308
1309 /*
1310  * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
1311  */
1312 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
1313 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025       0x01000000
1314 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
1315 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075       0x03000000
1316 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1         0x04000000
1317
1318 /*
1319  * ECC_ERR_INJECT - Memory data path error injection mask ECC
1320  */
1321 /* ECC Mirror Byte */
1322 #define ECC_ERR_INJECT_EMB              (0x80000000 >> 22)
1323 /* Error Injection Enable */
1324 #define ECC_ERR_INJECT_EIEN             (0x80000000 >> 23)
1325 /* ECC Erroe Injection Enable */
1326 #define ECC_ERR_INJECT_EEIM             (0xff000000 >> 24)
1327 #define ECC_ERR_INJECT_EEIM_SHIFT       0
1328
1329 /*
1330  * CAPTURE_ECC - Memory data path read capture ECC
1331  */
1332 #define CAPTURE_ECC_ECE                 (0xff000000 >> 24)
1333 #define CAPTURE_ECC_ECE_SHIFT           0
1334
1335 /*
1336  * ERR_DETECT - Memory error detect
1337  */
1338 /* Multiple Memory Errors */
1339 #define ECC_ERROR_DETECT_MME            (0x80000000 >> 0)
1340 /* Multiple-Bit Error */
1341 #define ECC_ERROR_DETECT_MBE            (0x80000000 >> 28)
1342 /* Single-Bit ECC Error Pickup */
1343 #define ECC_ERROR_DETECT_SBE            (0x80000000 >> 29)
1344 /* Memory Select Error */
1345 #define ECC_ERROR_DETECT_MSE            (0x80000000 >> 31)
1346
1347 /*
1348  * ERR_DISABLE - Memory error disable
1349  */
1350 /* Multiple-Bit ECC Error Disable */
1351 #define ECC_ERROR_DISABLE_MBED          (0x80000000 >> 28)
1352 /* Sinle-Bit ECC Error disable */
1353 #define ECC_ERROR_DISABLE_SBED          (0x80000000 >> 29)
1354 /* Memory Select Error Disable */
1355 #define ECC_ERROR_DISABLE_MSED          (0x80000000 >> 31)
1356 #define ECC_ERROR_ENABLE                (~(ECC_ERROR_DISABLE_MSED | \
1357                                                 ECC_ERROR_DISABLE_SBED | \
1358                                                 ECC_ERROR_DISABLE_MBED))
1359
1360 /*
1361  * ERR_INT_EN - Memory error interrupt enable
1362  */
1363 /* Multiple-Bit ECC Error Interrupt Enable */
1364 #define ECC_ERR_INT_EN_MBEE             (0x80000000 >> 28)
1365 /* Single-Bit ECC Error Interrupt Enable */
1366 #define ECC_ERR_INT_EN_SBEE             (0x80000000 >> 29)
1367 /* Memory Select Error Interrupt Enable */
1368 #define ECC_ERR_INT_EN_MSEE             (0x80000000 >> 31)
1369 #define ECC_ERR_INT_DISABLE             (~(ECC_ERR_INT_EN_MBEE | \
1370                                                 ECC_ERR_INT_EN_SBEE | \
1371                                                 ECC_ERR_INT_EN_MSEE))
1372
1373 /*
1374  * CAPTURE_ATTRIBUTES - Memory error attributes capture
1375  */
1376 /* Data Beat Num */
1377 #define ECC_CAPT_ATTR_BNUM              (0xe0000000 >> 1)
1378 #define ECC_CAPT_ATTR_BNUM_SHIFT        28
1379 /* Transaction Size */
1380 #define ECC_CAPT_ATTR_TSIZ              (0xc0000000 >> 6)
1381 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW      0
1382 #define ECC_CAPT_ATTR_TSIZ_ONE_DW       1
1383 #define ECC_CAPT_ATTR_TSIZ_TWO_DW       2
1384 #define ECC_CAPT_ATTR_TSIZ_THREE_DW     3
1385 #define ECC_CAPT_ATTR_TSIZ_SHIFT        24
1386 /* Transaction Source */
1387 #define ECC_CAPT_ATTR_TSRC              (0xf8000000 >> 11)
1388 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1389 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1390 #define ECC_CAPT_ATTR_TSRC_TSEC1        0x4
1391 #define ECC_CAPT_ATTR_TSRC_TSEC2        0x5
1392 #define ECC_CAPT_ATTR_TSRC_USB          (0x06|0x07)
1393 #define ECC_CAPT_ATTR_TSRC_ENCRYPT      0x8
1394 #define ECC_CAPT_ATTR_TSRC_I2C          0x9
1395 #define ECC_CAPT_ATTR_TSRC_JTAG         0xA
1396 #define ECC_CAPT_ATTR_TSRC_PCI1         0xD
1397 #define ECC_CAPT_ATTR_TSRC_PCI2         0xE
1398 #define ECC_CAPT_ATTR_TSRC_DMA          0xF
1399 #define ECC_CAPT_ATTR_TSRC_SHIFT        16
1400 /* Transaction Type */
1401 #define ECC_CAPT_ATTR_TTYP              (0xe0000000 >> 18)
1402 #define ECC_CAPT_ATTR_TTYP_WRITE        0x1
1403 #define ECC_CAPT_ATTR_TTYP_READ         0x2
1404 #define ECC_CAPT_ATTR_TTYP_R_M_W        0x3
1405 #define ECC_CAPT_ATTR_TTYP_SHIFT        12
1406 #define ECC_CAPT_ATTR_VLD               (0x80000000 >> 31)      /* Valid */
1407
1408 /*
1409  * ERR_SBE - Single bit ECC memory error management
1410  */
1411 /* Single-Bit Error Threshold 0..255 */
1412 #define ECC_ERROR_MAN_SBET              (0xff000000 >> 8)
1413 #define ECC_ERROR_MAN_SBET_SHIFT        16
1414 /* Single Bit Error Counter 0..255 */
1415 #define ECC_ERROR_MAN_SBEC              (0xff000000 >> 24)
1416 #define ECC_ERROR_MAN_SBEC_SHIFT        0
1417
1418 /*
1419  * CONFIG_ADDRESS - PCI Config Address Register
1420  */
1421 #define PCI_CONFIG_ADDRESS_EN           0x80000000
1422 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
1423 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
1424 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
1425 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
1426 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
1427 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
1428 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
1429 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
1430
1431 /*
1432  * POTAR - PCI Outbound Translation Address Register
1433  */
1434 #define POTAR_TA_MASK                   0x000fffff
1435
1436 /*
1437  * POBAR - PCI Outbound Base Address Register
1438  */
1439 #define POBAR_BA_MASK                   0x000fffff
1440
1441 /*
1442  * POCMR - PCI Outbound Comparision Mask Register
1443  */
1444 #define POCMR_EN                        0x80000000
1445 /* 0-memory space 1-I/O space */
1446 #define POCMR_IO                        0x40000000
1447 #define POCMR_SE                        0x20000000      /* streaming enable */
1448 #define POCMR_DST                       0x10000000      /* 0-PCI1 1-PCI2 */
1449 #define POCMR_CM_MASK                   0x000fffff
1450 #define POCMR_CM_4G                     0x00000000
1451 #define POCMR_CM_2G                     0x00080000
1452 #define POCMR_CM_1G                     0x000C0000
1453 #define POCMR_CM_512M                   0x000E0000
1454 #define POCMR_CM_256M                   0x000F0000
1455 #define POCMR_CM_128M                   0x000F8000
1456 #define POCMR_CM_64M                    0x000FC000
1457 #define POCMR_CM_32M                    0x000FE000
1458 #define POCMR_CM_16M                    0x000FF000
1459 #define POCMR_CM_8M                     0x000FF800
1460 #define POCMR_CM_4M                     0x000FFC00
1461 #define POCMR_CM_2M                     0x000FFE00
1462 #define POCMR_CM_1M                     0x000FFF00
1463 #define POCMR_CM_512K                   0x000FFF80
1464 #define POCMR_CM_256K                   0x000FFFC0
1465 #define POCMR_CM_128K                   0x000FFFE0
1466 #define POCMR_CM_64K                    0x000FFFF0
1467 #define POCMR_CM_32K                    0x000FFFF8
1468 #define POCMR_CM_16K                    0x000FFFFC
1469 #define POCMR_CM_8K                     0x000FFFFE
1470 #define POCMR_CM_4K                     0x000FFFFF
1471
1472 /*
1473  * PITAR - PCI Inbound Translation Address Register
1474  */
1475 #define PITAR_TA_MASK                   0x000fffff
1476
1477 /*
1478  * PIBAR - PCI Inbound Base/Extended Address Register
1479  */
1480 #define PIBAR_MASK                      0xffffffff
1481 #define PIEBAR_EBA_MASK                 0x000fffff
1482
1483 /*
1484  * PIWAR - PCI Inbound Windows Attributes Register
1485  */
1486 #define PIWAR_EN                        0x80000000
1487 #define PIWAR_PF                        0x20000000
1488 #define PIWAR_RTT_MASK                  0x000f0000
1489 #define PIWAR_RTT_NO_SNOOP              0x00040000
1490 #define PIWAR_RTT_SNOOP                 0x00050000
1491 #define PIWAR_WTT_MASK                  0x0000f000
1492 #define PIWAR_WTT_NO_SNOOP              0x00004000
1493 #define PIWAR_WTT_SNOOP                 0x00005000
1494 #define PIWAR_IWS_MASK                  0x0000003F
1495 #define PIWAR_IWS_4K                    0x0000000B
1496 #define PIWAR_IWS_8K                    0x0000000C
1497 #define PIWAR_IWS_16K                   0x0000000D
1498 #define PIWAR_IWS_32K                   0x0000000E
1499 #define PIWAR_IWS_64K                   0x0000000F
1500 #define PIWAR_IWS_128K                  0x00000010
1501 #define PIWAR_IWS_256K                  0x00000011
1502 #define PIWAR_IWS_512K                  0x00000012
1503 #define PIWAR_IWS_1M                    0x00000013
1504 #define PIWAR_IWS_2M                    0x00000014
1505 #define PIWAR_IWS_4M                    0x00000015
1506 #define PIWAR_IWS_8M                    0x00000016
1507 #define PIWAR_IWS_16M                   0x00000017
1508 #define PIWAR_IWS_32M                   0x00000018
1509 #define PIWAR_IWS_64M                   0x00000019
1510 #define PIWAR_IWS_128M                  0x0000001A
1511 #define PIWAR_IWS_256M                  0x0000001B
1512 #define PIWAR_IWS_512M                  0x0000001C
1513 #define PIWAR_IWS_1G                    0x0000001D
1514 #define PIWAR_IWS_2G                    0x0000001E
1515
1516 /*
1517  * PMCCR1 - PCI Configuration Register 1
1518  */
1519 #define PMCCR1_POWER_OFF                0x00000020
1520
1521 /*
1522  * DDRCDR - DDR Control Driver Register
1523  */
1524 #define DDRCDR_DHC_EN           0x80000000
1525 #define DDRCDR_EN               0x40000000
1526 #define DDRCDR_PZ               0x3C000000
1527 #define DDRCDR_PZ_MAXZ          0x00000000
1528 #define DDRCDR_PZ_HIZ           0x20000000
1529 #define DDRCDR_PZ_NOMZ          0x30000000
1530 #define DDRCDR_PZ_LOZ           0x38000000
1531 #define DDRCDR_PZ_MINZ          0x3C000000
1532 #define DDRCDR_NZ               0x3C000000
1533 #define DDRCDR_NZ_MAXZ          0x00000000
1534 #define DDRCDR_NZ_HIZ           0x02000000
1535 #define DDRCDR_NZ_NOMZ          0x03000000
1536 #define DDRCDR_NZ_LOZ           0x03800000
1537 #define DDRCDR_NZ_MINZ          0x03C00000
1538 #define DDRCDR_ODT              0x00080000
1539 #define DDRCDR_DDR_CFG          0x00040000
1540 #define DDRCDR_M_ODR            0x00000002
1541 #define DDRCDR_Q_DRN            0x00000001
1542
1543 /*
1544  * PCIE Bridge Register
1545  */
1546 #define PEX_CSB_CTRL_OBPIOE     0x00000001
1547 #define PEX_CSB_CTRL_IBPIOE     0x00000002
1548 #define PEX_CSB_CTRL_WDMAE      0x00000004
1549 #define PEX_CSB_CTRL_RDMAE      0x00000008
1550
1551 #define PEX_CSB_OBCTRL_PIOE     0x00000001
1552 #define PEX_CSB_OBCTRL_MEMWE    0x00000002
1553 #define PEX_CSB_OBCTRL_IOWE     0x00000004
1554 #define PEX_CSB_OBCTRL_CFGWE    0x00000008
1555
1556 #define PEX_CSB_IBCTRL_PIOE     0x00000001
1557
1558 #define PEX_OWAR_EN             0x00000001
1559 #define PEX_OWAR_TYPE_CFG       0x00000000
1560 #define PEX_OWAR_TYPE_IO        0x00000002
1561 #define PEX_OWAR_TYPE_MEM       0x00000004
1562 #define PEX_OWAR_RLXO           0x00000008
1563 #define PEX_OWAR_NANP           0x00000010
1564 #define PEX_OWAR_SIZE           0xFFFFF000
1565
1566 #define PEX_IWAR_EN             0x00000001
1567 #define PEX_IWAR_TYPE_INT       0x00000000
1568 #define PEX_IWAR_TYPE_PF        0x00000004
1569 #define PEX_IWAR_TYPE_NO_PF     0x00000006
1570 #define PEX_IWAR_NSOV           0x00000008
1571 #define PEX_IWAR_NSNP           0x00000010
1572 #define PEX_IWAR_SIZE           0xFFFFF000
1573 #define PEX_IWAR_SIZE_1M        0x000FF000
1574 #define PEX_IWAR_SIZE_2M        0x001FF000
1575 #define PEX_IWAR_SIZE_4M        0x003FF000
1576 #define PEX_IWAR_SIZE_8M        0x007FF000
1577 #define PEX_IWAR_SIZE_16M       0x00FFF000
1578 #define PEX_IWAR_SIZE_32M       0x01FFF000
1579 #define PEX_IWAR_SIZE_64M       0x03FFF000
1580 #define PEX_IWAR_SIZE_128M      0x07FFF000
1581 #define PEX_IWAR_SIZE_256M      0x0FFFF000
1582
1583 #define PEX_GCLK_RATIO          0x440
1584
1585 #ifndef __ASSEMBLY__
1586 struct pci_region;
1587 void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
1588 void mpc83xx_pcislave_unlock(int bus);
1589 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
1590 #endif
1591
1592 #endif  /* __MPC83XX_H__ */