2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
17 #if defined(CONFIG_E300)
21 /* MPC83xx cpu provide RCR register to do reset thing specially
25 /* System reset offset (PowerPC standard)
27 #define EXC_OFF_SYS_RESET 0x0100
28 #define _START_OFFSET EXC_OFF_SYS_RESET
30 /* IMMRBAR - Internal Memory Register Base Address
32 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
33 #define IMMRBAR 0x0000 /* Register offset to immr */
34 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
35 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
37 /* LAWBAR - Local Access Window Base Address Register
39 #define LBLAWBAR0 0x0020 /* Register offset to immr */
40 #define LBLAWAR0 0x0024
41 #define LBLAWBAR1 0x0028
42 #define LBLAWAR1 0x002C
43 #define LBLAWBAR2 0x0030
44 #define LBLAWAR2 0x0034
45 #define LBLAWBAR3 0x0038
46 #define LBLAWAR3 0x003C
47 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
49 /* SPRIDR - System Part and Revision ID Register
51 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
52 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
54 #define SPR_8349E_REV10 0x80300100
55 #define SPR_8349_REV10 0x80310100
56 #define SPR_8347E_REV10_TBGA 0x80320100
57 #define SPR_8347_REV10_TBGA 0x80330100
58 #define SPR_8347E_REV10_PBGA 0x80340100
59 #define SPR_8347_REV10_PBGA 0x80350100
60 #define SPR_8343E_REV10 0x80360100
61 #define SPR_8343_REV10 0x80370100
63 #define SPR_8349E_REV11 0x80300101
64 #define SPR_8349_REV11 0x80310101
65 #define SPR_8347E_REV11_TBGA 0x80320101
66 #define SPR_8347_REV11_TBGA 0x80330101
67 #define SPR_8347E_REV11_PBGA 0x80340101
68 #define SPR_8347_REV11_PBGA 0x80350101
69 #define SPR_8343E_REV11 0x80360101
70 #define SPR_8343_REV11 0x80370101
72 #define SPR_8349E_REV31 0x80300300
73 #define SPR_8349_REV31 0x80310300
74 #define SPR_8347E_REV31_TBGA 0x80320300
75 #define SPR_8347_REV31_TBGA 0x80330300
76 #define SPR_8347E_REV31_PBGA 0x80340300
77 #define SPR_8347_REV31_PBGA 0x80350300
78 #define SPR_8343E_REV31 0x80360300
79 #define SPR_8343_REV31 0x80370300
81 #define SPR_8360E_REV10 0x80480010
82 #define SPR_8360_REV10 0x80490010
83 #define SPR_8360E_REV11 0x80480011
84 #define SPR_8360_REV11 0x80490011
85 #define SPR_8360E_REV12 0x80480012
86 #define SPR_8360_REV12 0x80490012
87 #define SPR_8360E_REV20 0x80480020
88 #define SPR_8360_REV20 0x80490020
89 #define SPR_8360E_REV21 0x80480021
90 #define SPR_8360_REV21 0x80490021
92 #define SPR_8323E_REV10 0x80620010
93 #define SPR_8323_REV10 0x80630010
94 #define SPR_8321E_REV10 0x80660010
95 #define SPR_8321_REV10 0x80670010
96 #define SPR_8323E_REV11 0x80620011
97 #define SPR_8323_REV11 0x80630011
98 #define SPR_8321E_REV11 0x80660011
99 #define SPR_8321_REV11 0x80670011
101 #define SPR_8313E_REV10 0x80B00010
102 #define SPR_8313_REV10 0x80B10010
103 #define SPR_8311E_REV10 0x80B20010
104 #define SPR_8311_REV10 0x80B30010
106 #define SPR_8379E_REV10 0x80C20010
107 #define SPR_8379_REV10 0x80C30010
108 #define SPR_8378E_REV10 0x80C40010
109 #define SPR_8378_REV10 0x80C50010
110 #define SPR_8377E_REV10 0x80C60010
111 #define SPR_8377_REV10 0x80C70010
113 /* SPCR - System Priority Configuration Register
115 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
116 #define SPCR_PCIHPE_SHIFT (31-3)
117 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
118 #define SPCR_PCIPR_SHIFT (31-7)
119 #define SPCR_OPT 0x00800000 /* Optimize */
120 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
121 #define SPCR_TBEN_SHIFT (31-9)
122 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
123 #define SPCR_COREPR_SHIFT (31-11)
125 #if defined(CONFIG_MPC834X)
126 /* SPCR bits - MPC8349 specific */
127 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
128 #define SPCR_TSEC1DP_SHIFT (31-19)
129 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
130 #define SPCR_TSEC1BDP_SHIFT (31-21)
131 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
132 #define SPCR_TSEC1EP_SHIFT (31-23)
133 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
134 #define SPCR_TSEC2DP_SHIFT (31-27)
135 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
136 #define SPCR_TSEC2BDP_SHIFT (31-29)
137 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
138 #define SPCR_TSEC2EP_SHIFT (31-31)
140 #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
141 /* SPCR bits - MPC831x and MPC837x specific */
142 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */
143 #define SPCR_TSECDP_SHIFT (31-19)
144 #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */
145 #define SPCR_TSECEP_SHIFT (31-21)
146 #define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */
147 #define SPCR_TSECBDP_SHIFT (31-23)
150 /* SICRL/H - System I/O Configuration Register Low/High
152 #if defined(CONFIG_MPC834X)
153 /* SICRL bits - MPC8349 specific */
154 #define SICRL_LDP_A 0x80000000
155 #define SICRL_USB1 0x40000000
156 #define SICRL_USB0 0x20000000
157 #define SICRL_UART 0x0C000000
158 #define SICRL_GPIO1_A 0x02000000
159 #define SICRL_GPIO1_B 0x01000000
160 #define SICRL_GPIO1_C 0x00800000
161 #define SICRL_GPIO1_D 0x00400000
162 #define SICRL_GPIO1_E 0x00200000
163 #define SICRL_GPIO1_F 0x00180000
164 #define SICRL_GPIO1_G 0x00040000
165 #define SICRL_GPIO1_H 0x00020000
166 #define SICRL_GPIO1_I 0x00010000
167 #define SICRL_GPIO1_J 0x00008000
168 #define SICRL_GPIO1_K 0x00004000
169 #define SICRL_GPIO1_L 0x00003000
171 /* SICRH bits - MPC8349 specific */
172 #define SICRH_DDR 0x80000000
173 #define SICRH_TSEC1_A 0x10000000
174 #define SICRH_TSEC1_B 0x08000000
175 #define SICRH_TSEC1_C 0x04000000
176 #define SICRH_TSEC1_D 0x02000000
177 #define SICRH_TSEC1_E 0x01000000
178 #define SICRH_TSEC1_F 0x00800000
179 #define SICRH_TSEC2_A 0x00400000
180 #define SICRH_TSEC2_B 0x00200000
181 #define SICRH_TSEC2_C 0x00100000
182 #define SICRH_TSEC2_D 0x00080000
183 #define SICRH_TSEC2_E 0x00040000
184 #define SICRH_TSEC2_F 0x00020000
185 #define SICRH_TSEC2_G 0x00010000
186 #define SICRH_TSEC2_H 0x00008000
187 #define SICRH_GPIO2_A 0x00004000
188 #define SICRH_GPIO2_B 0x00002000
189 #define SICRH_GPIO2_C 0x00001000
190 #define SICRH_GPIO2_D 0x00000800
191 #define SICRH_GPIO2_E 0x00000400
192 #define SICRH_GPIO2_F 0x00000200
193 #define SICRH_GPIO2_G 0x00000180
194 #define SICRH_GPIO2_H 0x00000060
195 #define SICRH_TSOBI1 0x00000002
196 #define SICRH_TSOBI2 0x00000001
198 #elif defined(CONFIG_MPC8360)
199 /* SICRL bits - MPC8360 specific */
200 #define SICRL_LDP_A 0xC0000000
201 #define SICRL_LCLK_1 0x10000000
202 #define SICRL_LCLK_2 0x08000000
203 #define SICRL_SRCID_A 0x03000000
204 #define SICRL_IRQ_CKSTP_A 0x00C00000
206 /* SICRH bits - MPC8360 specific */
207 #define SICRH_DDR 0x80000000
208 #define SICRH_SECONDARY_DDR 0x40000000
209 #define SICRH_SDDROE 0x20000000
210 #define SICRH_IRQ3 0x10000000
211 #define SICRH_UC1EOBI 0x00000004
212 #define SICRH_UC2E1OBI 0x00000002
213 #define SICRH_UC2E2OBI 0x00000001
215 #elif defined(CONFIG_MPC832X)
216 /* SICRL bits - MPC832X specific */
217 #define SICRL_LDP_LCS_A 0x80000000
218 #define SICRL_IRQ_CKS 0x20000000
219 #define SICRL_PCI_MSRC 0x10000000
220 #define SICRL_URT_CTPR 0x06000000
221 #define SICRL_IRQ_CTPR 0x00C00000
223 #elif defined(CONFIG_MPC831X)
224 /* SICRL bits - MPC831x specific */
225 #define SICRL_LBC 0x30000000
226 #define SICRL_UART 0x0C000000
227 #define SICRL_SPI_A 0x03000000
228 #define SICRL_SPI_B 0x00C00000
229 #define SICRL_SPI_C 0x00300000
230 #define SICRL_SPI_D 0x000C0000
231 #define SICRL_USBDR 0x00000C00
232 #define SICRL_ETSEC1_A 0x0000000C
233 #define SICRL_ETSEC2_A 0x00000003
235 /* SICRH bits - MPC831x specific */
236 #define SICRH_INTR_A 0x02000000
237 #define SICRH_INTR_B 0x00C00000
238 #define SICRH_IIC 0x00300000
239 #define SICRH_ETSEC2_B 0x000C0000
240 #define SICRH_ETSEC2_C 0x00030000
241 #define SICRH_ETSEC2_D 0x0000C000
242 #define SICRH_ETSEC2_E 0x00003000
243 #define SICRH_ETSEC2_F 0x00000C00
244 #define SICRH_ETSEC2_G 0x00000300
245 #define SICRH_ETSEC1_B 0x00000080
246 #define SICRH_ETSEC1_C 0x00000060
247 #define SICRH_GTX1_DLY 0x00000008
248 #define SICRH_GTX2_DLY 0x00000004
249 #define SICRH_TSOBI1 0x00000002
250 #define SICRH_TSOBI2 0x00000001
252 #elif defined(CONFIG_MPC837X)
253 /* SICRL bits - MPC837x specific */
254 #define SICRL_USB_A 0xC0000000
255 #define SICRL_USB_B 0x30000000
256 #define SICRL_UART 0x0C000000
257 #define SICRL_GPIO_A 0x02000000
258 #define SICRL_GPIO_B 0x01000000
259 #define SICRL_GPIO_C 0x00800000
260 #define SICRL_GPIO_D 0x00400000
261 #define SICRL_GPIO_E 0x00200000
262 #define SICRL_GPIO_F 0x00180000
263 #define SICRL_GPIO_G 0x00040000
264 #define SICRL_GPIO_H 0x00020000
265 #define SICRL_GPIO_I 0x00010000
266 #define SICRL_GPIO_J 0x00008000
267 #define SICRL_GPIO_K 0x00004000
268 #define SICRL_GPIO_L 0x00003000
269 #define SICRL_DMA_A 0x00000800
270 #define SICRL_DMA_B 0x00000400
271 #define SICRL_DMA_C 0x00000200
272 #define SICRL_DMA_D 0x00000100
273 #define SICRL_DMA_E 0x00000080
274 #define SICRL_DMA_F 0x00000040
275 #define SICRL_DMA_G 0x00000020
276 #define SICRL_DMA_H 0x00000010
277 #define SICRL_DMA_I 0x00000008
278 #define SICRL_DMA_J 0x00000004
279 #define SICRL_LDP_A 0x00000002
280 #define SICRL_LDP_B 0x00000001
282 /* SICRH bits - MPC837x specific */
283 #define SICRH_DDR 0x80000000
284 #define SICRH_TSEC1_A 0x10000000
285 #define SICRH_TSEC1_B 0x08000000
286 #define SICRH_TSEC2_A 0x00400000
287 #define SICRH_TSEC2_B 0x00200000
288 #define SICRH_TSEC2_C 0x00100000
289 #define SICRH_TSEC2_D 0x00080000
290 #define SICRH_TSEC2_E 0x00040000
291 #define SICRH_TMR 0x00010000
292 #define SICRH_GPIO2_A 0x00008000
293 #define SICRH_GPIO2_B 0x00004000
294 #define SICRH_GPIO2_C 0x00002000
295 #define SICRH_GPIO2_D 0x00001000
296 #define SICRH_GPIO2_E 0x00000C00
297 #define SICRH_GPIO2_F 0x00000300
298 #define SICRH_GPIO2_G 0x000000C0
299 #define SICRH_GPIO2_H 0x00000030
300 #define SICRH_SPI 0x00000003
303 /* SWCRR - System Watchdog Control Register
305 #define SWCRR 0x0204 /* Register offset to immr */
306 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
307 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
308 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
309 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
310 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
312 /* SWCNR - System Watchdog Counter Register
314 #define SWCNR 0x0208 /* Register offset to immr */
315 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
316 #define SWCNR_RES ~(SWCNR_SWCN)
318 /* SWSRR - System Watchdog Service Register
320 #define SWSRR 0x020E /* Register offset to immr */
322 /* ACR - Arbiter Configuration Register
324 #define ACR_COREDIS 0x10000000 /* Core disable */
325 #define ACR_COREDIS_SHIFT (31-7)
326 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
327 #define ACR_PIPE_DEP_SHIFT (31-15)
328 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
329 #define ACR_PCI_RPTCNT_SHIFT (31-19)
330 #define ACR_RPTCNT 0x00000700 /* Repeat count */
331 #define ACR_RPTCNT_SHIFT (31-23)
332 #define ACR_APARK 0x00000030 /* Address parking */
333 #define ACR_APARK_SHIFT (31-27)
334 #define ACR_PARKM 0x0000000F /* Parking master */
335 #define ACR_PARKM_SHIFT (31-31)
337 /* ATR - Arbiter Timers Register
339 #define ATR_DTO 0x00FF0000 /* Data time out */
340 #define ATR_ATO 0x000000FF /* Address time out */
342 /* AER - Arbiter Event Register
344 #define AER_ETEA 0x00000020 /* Transfer error */
345 #define AER_RES 0x00000010 /* Reserved transfer type */
346 #define AER_ECW 0x00000008 /* External control word transfer type */
347 #define AER_AO 0x00000004 /* Address Only transfer type */
348 #define AER_DTO 0x00000002 /* Data time out */
349 #define AER_ATO 0x00000001 /* Address time out */
351 /* AEATR - Arbiter Event Address Register
353 #define AEATR_EVENT 0x07000000 /* Event type */
354 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
355 #define AEATR_TBST 0x00000800 /* Transfer burst */
356 #define AEATR_TSIZE 0x00000700 /* Transfer Size */
357 #define AEATR_TTYPE 0x0000001F /* Transfer Type */
359 /* HRCWL - Hard Reset Configuration Word Low
361 #define HRCWL_LBIUCM 0x80000000
362 #define HRCWL_LBIUCM_SHIFT 31
363 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
364 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
366 #define HRCWL_DDRCM 0x40000000
367 #define HRCWL_DDRCM_SHIFT 30
368 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
369 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
371 #define HRCWL_SPMF 0x0f000000
372 #define HRCWL_SPMF_SHIFT 24
373 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
374 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
375 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
376 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
377 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
378 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
379 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
380 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
381 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
382 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
383 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
384 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
385 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
386 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
387 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
388 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
390 #define HRCWL_VCO_BYPASS 0x00000000
391 #define HRCWL_VCO_1X2 0x00000000
392 #define HRCWL_VCO_1X4 0x00200000
393 #define HRCWL_VCO_1X8 0x00400000
395 #define HRCWL_COREPLL 0x007F0000
396 #define HRCWL_COREPLL_SHIFT 16
397 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
398 #define HRCWL_CORE_TO_CSB_1X1 0x00020000
399 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
400 #define HRCWL_CORE_TO_CSB_2X1 0x00040000
401 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
402 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
404 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
405 #define HRCWL_CEVCOD 0x000000C0
406 #define HRCWL_CEVCOD_SHIFT 6
407 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
408 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
409 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
411 #define HRCWL_CEPDF 0x00000020
412 #define HRCWL_CEPDF_SHIFT 5
413 #define HRCWL_CE_PLL_DIV_1X1 0x00000000
414 #define HRCWL_CE_PLL_DIV_2X1 0x00000020
416 #define HRCWL_CEPMF 0x0000001F
417 #define HRCWL_CEPMF_SHIFT 0
418 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
419 #define HRCWL_CE_TO_PLL_1X2 0x00000002
420 #define HRCWL_CE_TO_PLL_1X3 0x00000003
421 #define HRCWL_CE_TO_PLL_1X4 0x00000004
422 #define HRCWL_CE_TO_PLL_1X5 0x00000005
423 #define HRCWL_CE_TO_PLL_1X6 0x00000006
424 #define HRCWL_CE_TO_PLL_1X7 0x00000007
425 #define HRCWL_CE_TO_PLL_1X8 0x00000008
426 #define HRCWL_CE_TO_PLL_1X9 0x00000009
427 #define HRCWL_CE_TO_PLL_1X10 0x0000000A
428 #define HRCWL_CE_TO_PLL_1X11 0x0000000B
429 #define HRCWL_CE_TO_PLL_1X12 0x0000000C
430 #define HRCWL_CE_TO_PLL_1X13 0x0000000D
431 #define HRCWL_CE_TO_PLL_1X14 0x0000000E
432 #define HRCWL_CE_TO_PLL_1X15 0x0000000F
433 #define HRCWL_CE_TO_PLL_1X16 0x00000010
434 #define HRCWL_CE_TO_PLL_1X17 0x00000011
435 #define HRCWL_CE_TO_PLL_1X18 0x00000012
436 #define HRCWL_CE_TO_PLL_1X19 0x00000013
437 #define HRCWL_CE_TO_PLL_1X20 0x00000014
438 #define HRCWL_CE_TO_PLL_1X21 0x00000015
439 #define HRCWL_CE_TO_PLL_1X22 0x00000016
440 #define HRCWL_CE_TO_PLL_1X23 0x00000017
441 #define HRCWL_CE_TO_PLL_1X24 0x00000018
442 #define HRCWL_CE_TO_PLL_1X25 0x00000019
443 #define HRCWL_CE_TO_PLL_1X26 0x0000001A
444 #define HRCWL_CE_TO_PLL_1X27 0x0000001B
445 #define HRCWL_CE_TO_PLL_1X28 0x0000001C
446 #define HRCWL_CE_TO_PLL_1X29 0x0000001D
447 #define HRCWL_CE_TO_PLL_1X30 0x0000001E
448 #define HRCWL_CE_TO_PLL_1X31 0x0000001F
450 #elif defined(CONFIG_MPC837X)
451 #define HRCWL_SVCOD 0x30000000
452 #define HRCWL_SVCOD_SHIFT 28
453 #define HRCWL_SVCOD_DIV_4 0x00000000
454 #define HRCWL_SVCOD_DIV_8 0x10000000
455 #define HRCWL_SVCOD_DIV_2 0x20000000
456 #define HRCWL_SVCOD_DIV_1 0x30000000
459 /* HRCWH - Hardware Reset Configuration Word High
461 #define HRCWH_PCI_HOST 0x80000000
462 #define HRCWH_PCI_HOST_SHIFT 31
463 #define HRCWH_PCI_AGENT 0x00000000
465 #if defined(CONFIG_MPC834X)
466 #define HRCWH_32_BIT_PCI 0x00000000
467 #define HRCWH_64_BIT_PCI 0x40000000
470 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
471 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
473 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
474 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
476 #if defined(CONFIG_MPC834X)
477 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
478 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
480 #elif defined(CONFIG_MPC8360)
481 #define HRCWH_PCICKDRV_DISABLE 0x00000000
482 #define HRCWH_PCICKDRV_ENABLE 0x10000000
485 #define HRCWH_CORE_DISABLE 0x08000000
486 #define HRCWH_CORE_ENABLE 0x00000000
488 #define HRCWH_FROM_0X00000100 0x00000000
489 #define HRCWH_FROM_0XFFF00100 0x04000000
491 #define HRCWH_BOOTSEQ_DISABLE 0x00000000
492 #define HRCWH_BOOTSEQ_NORMAL 0x01000000
493 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
495 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
496 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
498 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
499 #define HRCWH_ROM_LOC_PCI1 0x00100000
500 #if defined(CONFIG_MPC834X)
501 #define HRCWH_ROM_LOC_PCI2 0x00200000
503 #if defined(CONIFG_MPC837X)
504 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
506 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
507 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
508 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
510 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
511 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
512 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
513 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
514 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
516 #define HRCWH_RL_EXT_LEGACY 0x00000000
517 #define HRCWH_RL_EXT_NAND 0x00040000
519 #define HRCWH_TSEC1M_IN_MII 0x00000000
520 #define HRCWH_TSEC1M_IN_RMII 0x00002000
521 #define HRCWH_TSEC1M_IN_RGMII 0x00006000
522 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000
523 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000
525 #define HRCWH_TSEC2M_IN_MII 0x00000000
526 #define HRCWH_TSEC2M_IN_RMII 0x00000400
527 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00
528 #define HRCWH_TSEC2M_IN_RTBI 0x00001400
529 #define HRCWH_TSEC2M_IN_SGMII 0x00001800
532 #if defined(CONFIG_MPC834X)
533 #define HRCWH_TSEC1M_IN_RGMII 0x00000000
534 #define HRCWH_TSEC1M_IN_RTBI 0x00004000
535 #define HRCWH_TSEC1M_IN_GMII 0x00008000
536 #define HRCWH_TSEC1M_IN_TBI 0x0000C000
537 #define HRCWH_TSEC2M_IN_RGMII 0x00000000
538 #define HRCWH_TSEC2M_IN_RTBI 0x00001000
539 #define HRCWH_TSEC2M_IN_GMII 0x00002000
540 #define HRCWH_TSEC2M_IN_TBI 0x00003000
543 #if defined(CONFIG_MPC8360)
544 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
545 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
548 #define HRCWH_BIG_ENDIAN 0x00000000
549 #define HRCWH_LITTLE_ENDIAN 0x00000008
551 #define HRCWH_LALE_NORMAL 0x00000000
552 #define HRCWH_LALE_EARLY 0x00000004
554 #define HRCWH_LDP_SET 0x00000000
555 #define HRCWH_LDP_CLEAR 0x00000002
557 /* RSR - Reset Status Register
559 #if defined(CONFIG_MPC837X)
560 #define RSR_RSTSRC 0xF0000000 /* Reset source */
561 #define RSR_RSTSRC_SHIFT 28
563 #define RSR_RSTSRC 0xE0000000 /* Reset source */
564 #define RSR_RSTSRC_SHIFT 29
566 #define RSR_BSF 0x00010000 /* Boot seq. fail */
567 #define RSR_BSF_SHIFT 16
568 #define RSR_SWSR 0x00002000 /* software soft reset */
569 #define RSR_SWSR_SHIFT 13
570 #define RSR_SWHR 0x00001000 /* software hard reset */
571 #define RSR_SWHR_SHIFT 12
572 #define RSR_JHRS 0x00000200 /* jtag hreset */
573 #define RSR_JHRS_SHIFT 9
574 #define RSR_JSRS 0x00000100 /* jtag sreset status */
575 #define RSR_JSRS_SHIFT 8
576 #define RSR_CSHR 0x00000010 /* checkstop reset status */
577 #define RSR_CSHR_SHIFT 4
578 #define RSR_SWRS 0x00000008 /* software watchdog reset status */
579 #define RSR_SWRS_SHIFT 3
580 #define RSR_BMRS 0x00000004 /* bus monitop reset status */
581 #define RSR_BMRS_SHIFT 2
582 #define RSR_SRS 0x00000002 /* soft reset status */
583 #define RSR_SRS_SHIFT 1
584 #define RSR_HRS 0x00000001 /* hard reset status */
585 #define RSR_HRS_SHIFT 0
586 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
587 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
588 RSR_BMRS | RSR_SRS | RSR_HRS)
589 /* RMR - Reset Mode Register
591 #define RMR_CSRE 0x00000001 /* checkstop reset enable */
592 #define RMR_CSRE_SHIFT 0
593 #define RMR_RES ~(RMR_CSRE)
595 /* RCR - Reset Control Register
597 #define RCR_SWHR 0x00000002 /* software hard reset */
598 #define RCR_SWSR 0x00000001 /* software soft reset */
599 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
601 /* RCER - Reset Control Enable Register
603 #define RCER_CRE 0x00000001 /* software hard reset */
604 #define RCER_RES ~(RCER_CRE)
606 /* SPMR - System PLL Mode Register
608 #define SPMR_LBIUCM 0x80000000
609 #define SPMR_DDRCM 0x40000000
610 #define SPMR_SPMF 0x0F000000
611 #define SPMR_CKID 0x00800000
612 #define SPMR_CKID_SHIFT 23
613 #define SPMR_COREPLL 0x007F0000
614 #define SPMR_CEVCOD 0x000000C0
615 #define SPMR_CEPDF 0x00000020
616 #define SPMR_CEPMF 0x0000001F
618 /* OCCR - Output Clock Control Register
620 #define OCCR_PCICOE0 0x80000000
621 #define OCCR_PCICOE1 0x40000000
622 #define OCCR_PCICOE2 0x20000000
623 #define OCCR_PCICOE3 0x10000000
624 #define OCCR_PCICOE4 0x08000000
625 #define OCCR_PCICOE5 0x04000000
626 #define OCCR_PCICOE6 0x02000000
627 #define OCCR_PCICOE7 0x01000000
628 #define OCCR_PCICD0 0x00800000
629 #define OCCR_PCICD1 0x00400000
630 #define OCCR_PCICD2 0x00200000
631 #define OCCR_PCICD3 0x00100000
632 #define OCCR_PCICD4 0x00080000
633 #define OCCR_PCICD5 0x00040000
634 #define OCCR_PCICD6 0x00020000
635 #define OCCR_PCICD7 0x00010000
636 #define OCCR_PCI1CR 0x00000002
637 #define OCCR_PCI2CR 0x00000001
638 #define OCCR_PCICR OCCR_PCI1CR
640 /* SCCR - System Clock Control Register
642 #define SCCR_ENCCM 0x03000000
643 #define SCCR_ENCCM_SHIFT 24
644 #define SCCR_ENCCM_0 0x00000000
645 #define SCCR_ENCCM_1 0x01000000
646 #define SCCR_ENCCM_2 0x02000000
647 #define SCCR_ENCCM_3 0x03000000
649 #define SCCR_PCICM 0x00010000
650 #define SCCR_PCICM_SHIFT 16
652 #if defined(CONFIG_MPC834X)
653 /* SCCR bits - MPC834x specific */
654 #define SCCR_TSEC1CM 0xc0000000
655 #define SCCR_TSEC1CM_SHIFT 30
656 #define SCCR_TSEC1CM_0 0x00000000
657 #define SCCR_TSEC1CM_1 0x40000000
658 #define SCCR_TSEC1CM_2 0x80000000
659 #define SCCR_TSEC1CM_3 0xC0000000
661 #define SCCR_TSEC2CM 0x30000000
662 #define SCCR_TSEC2CM_SHIFT 28
663 #define SCCR_TSEC2CM_0 0x00000000
664 #define SCCR_TSEC2CM_1 0x10000000
665 #define SCCR_TSEC2CM_2 0x20000000
666 #define SCCR_TSEC2CM_3 0x30000000
668 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
669 #define SCCR_USBMPHCM 0x00c00000
670 #define SCCR_USBMPHCM_SHIFT 22
671 #define SCCR_USBDRCM 0x00300000
672 #define SCCR_USBDRCM_SHIFT 20
673 #define SCCR_USBCM 0x00f00000
674 #define SCCR_USBCM_SHIFT 20
675 #define SCCR_USBCM_0 0x00000000
676 #define SCCR_USBCM_1 0x00500000
677 #define SCCR_USBCM_2 0x00A00000
678 #define SCCR_USBCM_3 0x00F00000
680 #elif defined(CONFIG_MPC831X)
681 /* TSEC1 bits are for TSEC2 as well */
682 #define SCCR_TSEC1CM 0xc0000000
683 #define SCCR_TSEC1CM_SHIFT 30
684 #define SCCR_TSEC1CM_1 0x40000000
685 #define SCCR_TSEC1CM_2 0x80000000
686 #define SCCR_TSEC1CM_3 0xC0000000
688 #define SCCR_TSEC1ON 0x20000000
689 #define SCCR_TSEC1ON_SHIFT 29
690 #define SCCR_TSEC2ON 0x10000000
691 #define SCCR_TSEC2ON_SHIFT 28
693 #define SCCR_USBDRCM 0x00300000
694 #define SCCR_USBDRCM_SHIFT 20
695 #define SCCR_USBDRCM_0 0x00000000
696 #define SCCR_USBDRCM_1 0x00100000
697 #define SCCR_USBDRCM_2 0x00200000
698 #define SCCR_USBDRCM_3 0x00300000
700 #elif defined(CONFIG_MPC837X)
701 /* SCCR bits - MPC837x specific */
702 #define SCCR_TSEC1CM 0xc0000000
703 #define SCCR_TSEC1CM_SHIFT 30
704 #define SCCR_TSEC1CM_0 0x00000000
705 #define SCCR_TSEC1CM_1 0x40000000
706 #define SCCR_TSEC1CM_2 0x80000000
707 #define SCCR_TSEC1CM_3 0xC0000000
709 #define SCCR_TSEC2CM 0x30000000
710 #define SCCR_TSEC2CM_SHIFT 28
711 #define SCCR_TSEC2CM_0 0x00000000
712 #define SCCR_TSEC2CM_1 0x10000000
713 #define SCCR_TSEC2CM_2 0x20000000
714 #define SCCR_TSEC2CM_3 0x30000000
716 #define SCCR_SDHCCM 0x0c000000
717 #define SCCR_SDHCCM_SHIFT 26
718 #define SCCR_SDHCCM_0 0x00000000
719 #define SCCR_SDHCCM_1 0x04000000
720 #define SCCR_SDHCCM_2 0x08000000
721 #define SCCR_SDHCCM_3 0x0c000000
723 #define SCCR_USBDRCM 0x00c00000
724 #define SCCR_USBDRCM_SHIFT 22
725 #define SCCR_USBDRCM_0 0x00000000
726 #define SCCR_USBDRCM_1 0x00400000
727 #define SCCR_USBDRCM_2 0x00800000
728 #define SCCR_USBDRCM_3 0x00c00000
730 #define SCCR_PCIEXP1CM 0x00300000
731 #define SCCR_PCIEXP1CM_SHIFT 20
732 #define SCCR_PCIEXP1CM_0 0x00000000
733 #define SCCR_PCIEXP1CM_1 0x00100000
734 #define SCCR_PCIEXP1CM_2 0x00200000
735 #define SCCR_PCIEXP1CM_3 0x00300000
737 #define SCCR_PCIEXP2CM 0x000c0000
738 #define SCCR_PCIEXP2CM_SHIFT 18
739 #define SCCR_PCIEXP2CM_0 0x00000000
740 #define SCCR_PCIEXP2CM_1 0x00040000
741 #define SCCR_PCIEXP2CM_2 0x00080000
742 #define SCCR_PCIEXP2CM_3 0x000c0000
744 /* All of the four SATA controllers must have the same clock ratio */
745 #define SCCR_SATA1CM 0x000000c0
746 #define SCCR_SATA1CM_SHIFT 6
747 #define SCCR_SATACM 0x000000ff
748 #define SCCR_SATACM_SHIFT 0
749 #define SCCR_SATACM_0 0x00000000
750 #define SCCR_SATACM_1 0x00000055
751 #define SCCR_SATACM_2 0x000000aa
752 #define SCCR_SATACM_3 0x000000ff
755 /* CSn_BDNS - Chip Select memory Bounds Register
757 #define CSBNDS_SA 0x00FF0000
758 #define CSBNDS_SA_SHIFT 8
759 #define CSBNDS_EA 0x000000FF
760 #define CSBNDS_EA_SHIFT 24
762 /* CSn_CONFIG - Chip Select Configuration Register
764 #define CSCONFIG_EN 0x80000000
765 #define CSCONFIG_AP 0x00800000
766 #define CSCONFIG_ROW_BIT 0x00000700
767 #define CSCONFIG_ROW_BIT_12 0x00000000
768 #define CSCONFIG_ROW_BIT_13 0x00000100
769 #define CSCONFIG_ROW_BIT_14 0x00000200
770 #define CSCONFIG_COL_BIT 0x00000007
771 #define CSCONFIG_COL_BIT_8 0x00000000
772 #define CSCONFIG_COL_BIT_9 0x00000001
773 #define CSCONFIG_COL_BIT_10 0x00000002
774 #define CSCONFIG_COL_BIT_11 0x00000003
776 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
778 #define TIMING_CFG0_RWT 0xC0000000
779 #define TIMING_CFG0_RWT_SHIFT 30
780 #define TIMING_CFG0_WRT 0x30000000
781 #define TIMING_CFG0_WRT_SHIFT 28
782 #define TIMING_CFG0_RRT 0x0C000000
783 #define TIMING_CFG0_RRT_SHIFT 26
784 #define TIMING_CFG0_WWT 0x03000000
785 #define TIMING_CFG0_WWT_SHIFT 24
786 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000
787 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
788 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000
789 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
790 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
791 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
792 #define TIMING_CFG0_MRS_CYC 0x00000F00
793 #define TIMING_CFG0_MRS_CYC_SHIFT 0
795 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
797 #define TIMING_CFG1_PRETOACT 0x70000000
798 #define TIMING_CFG1_PRETOACT_SHIFT 28
799 #define TIMING_CFG1_ACTTOPRE 0x0F000000
800 #define TIMING_CFG1_ACTTOPRE_SHIFT 24
801 #define TIMING_CFG1_ACTTORW 0x00700000
802 #define TIMING_CFG1_ACTTORW_SHIFT 20
803 #define TIMING_CFG1_CASLAT 0x00070000
804 #define TIMING_CFG1_CASLAT_SHIFT 16
805 #define TIMING_CFG1_REFREC 0x0000F000
806 #define TIMING_CFG1_REFREC_SHIFT 12
807 #define TIMING_CFG1_WRREC 0x00000700
808 #define TIMING_CFG1_WRREC_SHIFT 8
809 #define TIMING_CFG1_ACTTOACT 0x00000070
810 #define TIMING_CFG1_ACTTOACT_SHIFT 4
811 #define TIMING_CFG1_WRTORD 0x00000007
812 #define TIMING_CFG1_WRTORD_SHIFT 0
813 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
814 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
816 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
818 #define TIMING_CFG2_CPO 0x0F800000
819 #define TIMING_CFG2_CPO_SHIFT 23
820 #define TIMING_CFG2_ACSM 0x00080000
821 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
822 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
823 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
825 #define TIMING_CFG2_ADD_LAT 0x70000000
826 #define TIMING_CFG2_ADD_LAT_SHIFT 28
827 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000
828 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
829 #define TIMING_CFG2_RD_TO_PRE 0x0000E000
830 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13
831 #define TIMING_CFG2_CKE_PLS 0x000001C0
832 #define TIMING_CFG2_CKE_PLS_SHIFT 6
833 #define TIMING_CFG2_FOUR_ACT 0x0000003F
834 #define TIMING_CFG2_FOUR_ACT_SHIFT 0
836 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
838 #define SDRAM_CFG_MEM_EN 0x80000000
839 #define SDRAM_CFG_SREN 0x40000000
840 #define SDRAM_CFG_ECC_EN 0x20000000
841 #define SDRAM_CFG_RD_EN 0x10000000
842 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
843 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
844 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
845 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
846 #define SDRAM_CFG_DYN_PWR 0x00200000
847 #define SDRAM_CFG_32_BE 0x00080000
848 #define SDRAM_CFG_8_BE 0x00040000
849 #define SDRAM_CFG_NCAP 0x00020000
850 #define SDRAM_CFG_2T_EN 0x00008000
851 #define SDRAM_CFG_BI 0x00000001
853 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
855 #define SDRAM_MODE_ESD 0xFFFF0000
856 #define SDRAM_MODE_ESD_SHIFT 16
857 #define SDRAM_MODE_SD 0x0000FFFF
858 #define SDRAM_MODE_SD_SHIFT 0
859 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
860 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
861 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
862 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
863 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
864 #define DDR_MODE_WEAK 0x0002 /* weak drivers */
865 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
866 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
867 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
868 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
869 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
870 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
871 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
872 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
873 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
874 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
875 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
876 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
877 #define DDR_MODE_MODEREG 0x0000 /* select mode register */
879 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
881 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
882 #define SDRAM_INTERVAL_REFINT_SHIFT 16
883 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
884 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
886 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
888 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
889 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
890 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
891 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
892 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
894 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
896 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
897 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
898 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
899 #define ECC_ERR_INJECT_EEIM_SHIFT 0
901 /* CAPTURE_ECC - Memory data path read capture ECC
903 #define CAPTURE_ECC_ECE (0xff000000>>24)
904 #define CAPTURE_ECC_ECE_SHIFT 0
906 /* ERR_DETECT - Memory error detect
908 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
909 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
910 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
911 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
913 /* ERR_DISABLE - Memory error disable
915 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
916 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
917 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
918 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
919 ECC_ERROR_DISABLE_MBED)
920 /* ERR_INT_EN - Memory error interrupt enable
922 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
923 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
924 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
925 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
927 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
929 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
930 #define ECC_CAPT_ATTR_BNUM_SHIFT 28
931 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
932 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
933 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
934 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
935 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
936 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
937 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
938 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
939 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
940 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
941 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
942 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
943 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
944 #define ECC_CAPT_ATTR_TSRC_I2C 0x9
945 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
946 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
947 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
948 #define ECC_CAPT_ATTR_TSRC_DMA 0xF
949 #define ECC_CAPT_ATTR_TSRC_SHIFT 16
950 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
951 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
952 #define ECC_CAPT_ATTR_TTYP_READ 0x2
953 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
954 #define ECC_CAPT_ATTR_TTYP_SHIFT 12
955 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
957 /* ERR_SBE - Single bit ECC memory error management
959 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
960 #define ECC_ERROR_MAN_SBET_SHIFT 16
961 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
962 #define ECC_ERROR_MAN_SBEC_SHIFT 0
964 /* BR - Base Registers
966 #define BR0 0x5000 /* Register offset to immr */
975 #define BR_BA 0xFFFF8000
976 #define BR_BA_SHIFT 15
977 #define BR_PS 0x00001800
978 #define BR_PS_SHIFT 11
979 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
980 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
981 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
982 #define BR_DECC 0x00000600
983 #define BR_DECC_SHIFT 9
984 #define BR_DECC_OFF 0x00000000
985 #define BR_DECC_CHK 0x00000200
986 #define BR_DECC_CHK_GEN 0x00000400
987 #define BR_WP 0x00000100
988 #define BR_WP_SHIFT 8
989 #define BR_MSEL 0x000000E0
990 #define BR_MSEL_SHIFT 5
991 #define BR_MS_GPCM 0x00000000 /* GPCM */
992 #define BR_MS_FCM 0x00000020 /* FCM */
993 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
994 #define BR_MS_UPMA 0x00000080 /* UPMA */
995 #define BR_MS_UPMB 0x000000A0 /* UPMB */
996 #define BR_MS_UPMC 0x000000C0 /* UPMC */
997 #if !defined(CONFIG_MPC834X)
998 #define BR_ATOM 0x0000000C
999 #define BR_ATOM_SHIFT 2
1001 #define BR_V 0x00000001
1002 #define BR_V_SHIFT 0
1004 #if defined(CONFIG_MPC834X)
1005 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
1007 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
1010 /* OR - Option Registers
1012 #define OR0 0x5004 /* Register offset to immr */
1021 #define OR_GPCM_AM 0xFFFF8000
1022 #define OR_GPCM_AM_SHIFT 15
1023 #define OR_GPCM_BCTLD 0x00001000
1024 #define OR_GPCM_BCTLD_SHIFT 12
1025 #define OR_GPCM_CSNT 0x00000800
1026 #define OR_GPCM_CSNT_SHIFT 11
1027 #define OR_GPCM_ACS 0x00000600
1028 #define OR_GPCM_ACS_SHIFT 9
1029 #define OR_GPCM_ACS_0b10 0x00000400
1030 #define OR_GPCM_ACS_0b11 0x00000600
1031 #define OR_GPCM_XACS 0x00000100
1032 #define OR_GPCM_XACS_SHIFT 8
1033 #define OR_GPCM_SCY 0x000000F0
1034 #define OR_GPCM_SCY_SHIFT 4
1035 #define OR_GPCM_SCY_1 0x00000010
1036 #define OR_GPCM_SCY_2 0x00000020
1037 #define OR_GPCM_SCY_3 0x00000030
1038 #define OR_GPCM_SCY_4 0x00000040
1039 #define OR_GPCM_SCY_5 0x00000050
1040 #define OR_GPCM_SCY_6 0x00000060
1041 #define OR_GPCM_SCY_7 0x00000070
1042 #define OR_GPCM_SCY_8 0x00000080
1043 #define OR_GPCM_SCY_9 0x00000090
1044 #define OR_GPCM_SCY_10 0x000000a0
1045 #define OR_GPCM_SCY_11 0x000000b0
1046 #define OR_GPCM_SCY_12 0x000000c0
1047 #define OR_GPCM_SCY_13 0x000000d0
1048 #define OR_GPCM_SCY_14 0x000000e0
1049 #define OR_GPCM_SCY_15 0x000000f0
1050 #define OR_GPCM_SETA 0x00000008
1051 #define OR_GPCM_SETA_SHIFT 3
1052 #define OR_GPCM_TRLX 0x00000004
1053 #define OR_GPCM_TRLX_SHIFT 2
1054 #define OR_GPCM_EHTR 0x00000002
1055 #define OR_GPCM_EHTR_SHIFT 1
1056 #define OR_GPCM_EAD 0x00000001
1057 #define OR_GPCM_EAD_SHIFT 0
1059 #define OR_FCM_AM 0xFFFF8000
1060 #define OR_FCM_AM_SHIFT 15
1061 #define OR_FCM_BCTLD 0x00001000
1062 #define OR_FCM_BCTLD_SHIFT 12
1063 #define OR_FCM_PGS 0x00000400
1064 #define OR_FCM_PGS_SHIFT 10
1065 #define OR_FCM_CSCT 0x00000200
1066 #define OR_FCM_CSCT_SHIFT 9
1067 #define OR_FCM_CST 0x00000100
1068 #define OR_FCM_CST_SHIFT 8
1069 #define OR_FCM_CHT 0x00000080
1070 #define OR_FCM_CHT_SHIFT 7
1071 #define OR_FCM_SCY 0x00000070
1072 #define OR_FCM_SCY_SHIFT 4
1073 #define OR_FCM_SCY_1 0x00000010
1074 #define OR_FCM_SCY_2 0x00000020
1075 #define OR_FCM_SCY_3 0x00000030
1076 #define OR_FCM_SCY_4 0x00000040
1077 #define OR_FCM_SCY_5 0x00000050
1078 #define OR_FCM_SCY_6 0x00000060
1079 #define OR_FCM_SCY_7 0x00000070
1080 #define OR_FCM_RST 0x00000008
1081 #define OR_FCM_RST_SHIFT 3
1082 #define OR_FCM_TRLX 0x00000004
1083 #define OR_FCM_TRLX_SHIFT 2
1084 #define OR_FCM_EHTR 0x00000002
1085 #define OR_FCM_EHTR_SHIFT 1
1087 #define OR_UPM_AM 0xFFFF8000
1088 #define OR_UPM_AM_SHIFT 15
1089 #define OR_UPM_XAM 0x00006000
1090 #define OR_UPM_XAM_SHIFT 13
1091 #define OR_UPM_BCTLD 0x00001000
1092 #define OR_UPM_BCTLD_SHIFT 12
1093 #define OR_UPM_BI 0x00000100
1094 #define OR_UPM_BI_SHIFT 8
1095 #define OR_UPM_TRLX 0x00000004
1096 #define OR_UPM_TRLX_SHIFT 2
1097 #define OR_UPM_EHTR 0x00000002
1098 #define OR_UPM_EHTR_SHIFT 1
1099 #define OR_UPM_EAD 0x00000001
1100 #define OR_UPM_EAD_SHIFT 0
1102 #define OR_SDRAM_AM 0xFFFF8000
1103 #define OR_SDRAM_AM_SHIFT 15
1104 #define OR_SDRAM_XAM 0x00006000
1105 #define OR_SDRAM_XAM_SHIFT 13
1106 #define OR_SDRAM_COLS 0x00001C00
1107 #define OR_SDRAM_COLS_SHIFT 10
1108 #define OR_SDRAM_ROWS 0x000001C0
1109 #define OR_SDRAM_ROWS_SHIFT 6
1110 #define OR_SDRAM_PMSEL 0x00000020
1111 #define OR_SDRAM_PMSEL_SHIFT 5
1112 #define OR_SDRAM_EAD 0x00000001
1113 #define OR_SDRAM_EAD_SHIFT 0
1115 #define OR_AM_32KB 0xFFFF8000
1116 #define OR_AM_64KB 0xFFFF0000
1117 #define OR_AM_128KB 0xFFFE0000
1118 #define OR_AM_256KB 0xFFFC0000
1119 #define OR_AM_512KB 0xFFF80000
1120 #define OR_AM_1MB 0xFFF00000
1121 #define OR_AM_2MB 0xFFE00000
1122 #define OR_AM_4MB 0xFFC00000
1123 #define OR_AM_8MB 0xFF800000
1124 #define OR_AM_16MB 0xFF000000
1125 #define OR_AM_32MB 0xFE000000
1126 #define OR_AM_64MB 0xFC000000
1127 #define OR_AM_128MB 0xF8000000
1128 #define OR_AM_256MB 0xF0000000
1129 #define OR_AM_512MB 0xE0000000
1130 #define OR_AM_1GB 0xC0000000
1131 #define OR_AM_2GB 0x80000000
1132 #define OR_AM_4GB 0x00000000
1134 #define LBLAWAR_EN 0x80000000
1135 #define LBLAWAR_4KB 0x0000000B
1136 #define LBLAWAR_8KB 0x0000000C
1137 #define LBLAWAR_16KB 0x0000000D
1138 #define LBLAWAR_32KB 0x0000000E
1139 #define LBLAWAR_64KB 0x0000000F
1140 #define LBLAWAR_128KB 0x00000010
1141 #define LBLAWAR_256KB 0x00000011
1142 #define LBLAWAR_512KB 0x00000012
1143 #define LBLAWAR_1MB 0x00000013
1144 #define LBLAWAR_2MB 0x00000014
1145 #define LBLAWAR_4MB 0x00000015
1146 #define LBLAWAR_8MB 0x00000016
1147 #define LBLAWAR_16MB 0x00000017
1148 #define LBLAWAR_32MB 0x00000018
1149 #define LBLAWAR_64MB 0x00000019
1150 #define LBLAWAR_128MB 0x0000001A
1151 #define LBLAWAR_256MB 0x0000001B
1152 #define LBLAWAR_512MB 0x0000001C
1153 #define LBLAWAR_1GB 0x0000001D
1154 #define LBLAWAR_2GB 0x0000001E
1156 /* LBCR - Local Bus Configuration Register
1158 #define LBCR_LDIS 0x80000000
1159 #define LBCR_LDIS_SHIFT 31
1160 #define LBCR_BCTLC 0x00C00000
1161 #define LBCR_BCTLC_SHIFT 22
1162 #define LBCR_LPBSE 0x00020000
1163 #define LBCR_LPBSE_SHIFT 17
1164 #define LBCR_EPAR 0x00010000
1165 #define LBCR_EPAR_SHIFT 16
1166 #define LBCR_BMT 0x0000FF00
1167 #define LBCR_BMT_SHIFT 8
1169 /* LCRR - Clock Ratio Register
1171 #define LCRR_DBYP 0x80000000
1172 #define LCRR_DBYP_SHIFT 31
1173 #define LCRR_BUFCMDC 0x30000000
1174 #define LCRR_BUFCMDC_SHIFT 28
1175 #define LCRR_BUFCMDC_1 0x10000000
1176 #define LCRR_BUFCMDC_2 0x20000000
1177 #define LCRR_BUFCMDC_3 0x30000000
1178 #define LCRR_BUFCMDC_4 0x00000000
1179 #define LCRR_ECL 0x03000000
1180 #define LCRR_ECL_SHIFT 24
1181 #define LCRR_ECL_4 0x00000000
1182 #define LCRR_ECL_5 0x01000000
1183 #define LCRR_ECL_6 0x02000000
1184 #define LCRR_ECL_7 0x03000000
1185 #define LCRR_EADC 0x00030000
1186 #define LCRR_EADC_SHIFT 16
1187 #define LCRR_EADC_1 0x00010000
1188 #define LCRR_EADC_2 0x00020000
1189 #define LCRR_EADC_3 0x00030000
1190 #define LCRR_EADC_4 0x00000000
1191 #define LCRR_CLKDIV 0x0000000F
1192 #define LCRR_CLKDIV_SHIFT 0
1193 #define LCRR_CLKDIV_2 0x00000002
1194 #define LCRR_CLKDIV_4 0x00000004
1195 #define LCRR_CLKDIV_8 0x00000008
1197 /* DMAMR - DMA Mode Register
1199 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
1200 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
1201 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
1202 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
1203 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
1204 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
1205 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
1206 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
1208 /* DMASR - DMA Status Register
1210 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
1211 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
1213 /* CONFIG_ADDRESS - PCI Config Address Register
1215 #define PCI_CONFIG_ADDRESS_EN 0x80000000
1216 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1217 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1218 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1219 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1220 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1221 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1222 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1223 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
1225 /* POTAR - PCI Outbound Translation Address Register
1227 #define POTAR_TA_MASK 0x000fffff
1229 /* POBAR - PCI Outbound Base Address Register
1231 #define POBAR_BA_MASK 0x000fffff
1233 /* POCMR - PCI Outbound Comparision Mask Register
1235 #define POCMR_EN 0x80000000
1236 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
1237 #define POCMR_SE 0x20000000 /* streaming enable */
1238 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1239 #define POCMR_CM_MASK 0x000fffff
1240 #define POCMR_CM_4G 0x00000000
1241 #define POCMR_CM_2G 0x00080000
1242 #define POCMR_CM_1G 0x000C0000
1243 #define POCMR_CM_512M 0x000E0000
1244 #define POCMR_CM_256M 0x000F0000
1245 #define POCMR_CM_128M 0x000F8000
1246 #define POCMR_CM_64M 0x000FC000
1247 #define POCMR_CM_32M 0x000FE000
1248 #define POCMR_CM_16M 0x000FF000
1249 #define POCMR_CM_8M 0x000FF800
1250 #define POCMR_CM_4M 0x000FFC00
1251 #define POCMR_CM_2M 0x000FFE00
1252 #define POCMR_CM_1M 0x000FFF00
1253 #define POCMR_CM_512K 0x000FFF80
1254 #define POCMR_CM_256K 0x000FFFC0
1255 #define POCMR_CM_128K 0x000FFFE0
1256 #define POCMR_CM_64K 0x000FFFF0
1257 #define POCMR_CM_32K 0x000FFFF8
1258 #define POCMR_CM_16K 0x000FFFFC
1259 #define POCMR_CM_8K 0x000FFFFE
1260 #define POCMR_CM_4K 0x000FFFFF
1262 /* PITAR - PCI Inbound Translation Address Register
1264 #define PITAR_TA_MASK 0x000fffff
1266 /* PIBAR - PCI Inbound Base/Extended Address Register
1268 #define PIBAR_MASK 0xffffffff
1269 #define PIEBAR_EBA_MASK 0x000fffff
1271 /* PIWAR - PCI Inbound Windows Attributes Register
1273 #define PIWAR_EN 0x80000000
1274 #define PIWAR_PF 0x20000000
1275 #define PIWAR_RTT_MASK 0x000f0000
1276 #define PIWAR_RTT_NO_SNOOP 0x00040000
1277 #define PIWAR_RTT_SNOOP 0x00050000
1278 #define PIWAR_WTT_MASK 0x0000f000
1279 #define PIWAR_WTT_NO_SNOOP 0x00004000
1280 #define PIWAR_WTT_SNOOP 0x00005000
1281 #define PIWAR_IWS_MASK 0x0000003F
1282 #define PIWAR_IWS_4K 0x0000000B
1283 #define PIWAR_IWS_8K 0x0000000C
1284 #define PIWAR_IWS_16K 0x0000000D
1285 #define PIWAR_IWS_32K 0x0000000E
1286 #define PIWAR_IWS_64K 0x0000000F
1287 #define PIWAR_IWS_128K 0x00000010
1288 #define PIWAR_IWS_256K 0x00000011
1289 #define PIWAR_IWS_512K 0x00000012
1290 #define PIWAR_IWS_1M 0x00000013
1291 #define PIWAR_IWS_2M 0x00000014
1292 #define PIWAR_IWS_4M 0x00000015
1293 #define PIWAR_IWS_8M 0x00000016
1294 #define PIWAR_IWS_16M 0x00000017
1295 #define PIWAR_IWS_32M 0x00000018
1296 #define PIWAR_IWS_64M 0x00000019
1297 #define PIWAR_IWS_128M 0x0000001A
1298 #define PIWAR_IWS_256M 0x0000001B
1299 #define PIWAR_IWS_512M 0x0000001C
1300 #define PIWAR_IWS_1G 0x0000001D
1301 #define PIWAR_IWS_2G 0x0000001E
1303 /* PMCCR1 - PCI Configuration Register 1
1305 #define PMCCR1_POWER_OFF 0x00000020
1307 /* FMR - Flash Mode Register
1309 #define FMR_CWTO 0x0000F000
1310 #define FMR_CWTO_SHIFT 12
1311 #define FMR_BOOT 0x00000800
1312 #define FMR_ECCM 0x00000100
1313 #define FMR_AL 0x00000030
1314 #define FMR_AL_SHIFT 4
1315 #define FMR_OP 0x00000003
1316 #define FMR_OP_SHIFT 0
1318 /* FIR - Flash Instruction Register
1320 #define FIR_OP0 0xF0000000
1321 #define FIR_OP0_SHIFT 28
1322 #define FIR_OP1 0x0F000000
1323 #define FIR_OP1_SHIFT 24
1324 #define FIR_OP2 0x00F00000
1325 #define FIR_OP2_SHIFT 20
1326 #define FIR_OP3 0x000F0000
1327 #define FIR_OP3_SHIFT 16
1328 #define FIR_OP4 0x0000F000
1329 #define FIR_OP4_SHIFT 12
1330 #define FIR_OP5 0x00000F00
1331 #define FIR_OP5_SHIFT 8
1332 #define FIR_OP6 0x000000F0
1333 #define FIR_OP6_SHIFT 4
1334 #define FIR_OP7 0x0000000F
1335 #define FIR_OP7_SHIFT 0
1336 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
1337 #define FIR_OP_CA 0x1 /* Issue current column address */
1338 #define FIR_OP_PA 0x2 /* Issue current block+page address */
1339 #define FIR_OP_UA 0x3 /* Issue user defined address */
1340 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
1341 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
1342 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
1343 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
1344 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
1345 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
1346 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
1347 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
1348 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
1349 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
1350 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
1351 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
1353 /* FCR - Flash Command Register
1355 #define FCR_CMD0 0xFF000000
1356 #define FCR_CMD0_SHIFT 24
1357 #define FCR_CMD1 0x00FF0000
1358 #define FCR_CMD1_SHIFT 16
1359 #define FCR_CMD2 0x0000FF00
1360 #define FCR_CMD2_SHIFT 8
1361 #define FCR_CMD3 0x000000FF
1362 #define FCR_CMD3_SHIFT 0
1364 /* FBAR - Flash Block Address Register
1366 #define FBAR_BLK 0x00FFFFFF
1368 /* FPAR - Flash Page Address Register
1370 #define FPAR_SP_PI 0x00007C00
1371 #define FPAR_SP_PI_SHIFT 10
1372 #define FPAR_SP_MS 0x00000200
1373 #define FPAR_SP_CI 0x000001FF
1374 #define FPAR_SP_CI_SHIFT 0
1375 #define FPAR_LP_PI 0x0003F000
1376 #define FPAR_LP_PI_SHIFT 12
1377 #define FPAR_LP_MS 0x00000800
1378 #define FPAR_LP_CI 0x000007FF
1379 #define FPAR_LP_CI_SHIFT 0
1381 /* LTESR - Transfer Error Status Register
1383 #define LTESR_BM 0x80000000
1384 #define LTESR_FCT 0x40000000
1385 #define LTESR_PAR 0x20000000
1386 #define LTESR_WP 0x04000000
1387 #define LTESR_ATMW 0x00800000
1388 #define LTESR_ATMR 0x00400000
1389 #define LTESR_CS 0x00080000
1390 #define LTESR_CC 0x00000001
1392 /* DDRCDR - DDR Control Driver Register
1394 #define DDRCDR_EN 0x40000000
1395 #define DDRCDR_PZ 0x3C000000
1396 #define DDRCDR_PZ_MAXZ 0x00000000
1397 #define DDRCDR_PZ_HIZ 0x20000000
1398 #define DDRCDR_PZ_NOMZ 0x30000000
1399 #define DDRCDR_PZ_LOZ 0x38000000
1400 #define DDRCDR_PZ_MINZ 0x3C000000
1401 #define DDRCDR_NZ 0x3C000000
1402 #define DDRCDR_NZ_MAXZ 0x00000000
1403 #define DDRCDR_NZ_HIZ 0x02000000
1404 #define DDRCDR_NZ_NOMZ 0x03000000
1405 #define DDRCDR_NZ_LOZ 0x03800000
1406 #define DDRCDR_NZ_MINZ 0x03C00000
1407 #define DDRCDR_ODT 0x00080000
1408 #define DDRCDR_DDR_CFG 0x00040000
1409 #define DDRCDR_M_ODR 0x00000002
1410 #define DDRCDR_Q_DRN 0x00000001
1412 #ifndef __ASSEMBLY__
1414 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
1417 #endif /* __MPC83XX_H__ */