2 * Copyright 2008,2010 Freescale Semiconductor, Inc
5 * Based (loosely) on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/list.h>
14 #include <linux/sizes.h>
15 #include <linux/compiler.h>
18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
19 #define SD_VERSION_SD (1U << 31)
20 #define MMC_VERSION_MMC (1U << 30)
22 #define MAKE_SDMMC_VERSION(a, b, c) \
23 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
24 #define MAKE_SD_VERSION(a, b, c) \
25 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
26 #define MAKE_MMC_VERSION(a, b, c) \
27 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
29 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
30 (((u32)(x) >> 16) & 0xff)
31 #define EXTRACT_SDMMC_MINOR_VERSION(x) \
32 (((u32)(x) >> 8) & 0xff)
33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
36 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
37 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
38 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
39 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
41 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
42 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
43 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
44 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
45 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
46 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
47 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
48 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
49 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
50 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
51 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
52 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
53 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
55 #define MMC_CAP(mode) (1 << mode)
56 #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
57 #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
58 #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
59 #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
61 #define MMC_MODE_8BIT BIT(30)
62 #define MMC_MODE_4BIT BIT(29)
63 #define MMC_MODE_1BIT BIT(28)
64 #define MMC_MODE_SPI BIT(27)
67 #define SD_DATA_4BIT 0x00040000
69 #define IS_SD(x) ((x)->version & SD_VERSION_SD)
70 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
72 #define MMC_DATA_READ 1
73 #define MMC_DATA_WRITE 2
75 #define MMC_CMD_GO_IDLE_STATE 0
76 #define MMC_CMD_SEND_OP_COND 1
77 #define MMC_CMD_ALL_SEND_CID 2
78 #define MMC_CMD_SET_RELATIVE_ADDR 3
79 #define MMC_CMD_SET_DSR 4
80 #define MMC_CMD_SWITCH 6
81 #define MMC_CMD_SELECT_CARD 7
82 #define MMC_CMD_SEND_EXT_CSD 8
83 #define MMC_CMD_SEND_CSD 9
84 #define MMC_CMD_SEND_CID 10
85 #define MMC_CMD_STOP_TRANSMISSION 12
86 #define MMC_CMD_SEND_STATUS 13
87 #define MMC_CMD_SET_BLOCKLEN 16
88 #define MMC_CMD_READ_SINGLE_BLOCK 17
89 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
90 #define MMC_CMD_SEND_TUNING_BLOCK 19
91 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
92 #define MMC_CMD_SET_BLOCK_COUNT 23
93 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
94 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
95 #define MMC_CMD_ERASE_GROUP_START 35
96 #define MMC_CMD_ERASE_GROUP_END 36
97 #define MMC_CMD_ERASE 38
98 #define MMC_CMD_APP_CMD 55
99 #define MMC_CMD_SPI_READ_OCR 58
100 #define MMC_CMD_SPI_CRC_ON_OFF 59
101 #define MMC_CMD_RES_MAN 62
103 #define MMC_CMD62_ARG1 0xefac62ec
104 #define MMC_CMD62_ARG2 0xcbaea7
107 #define SD_CMD_SEND_RELATIVE_ADDR 3
108 #define SD_CMD_SWITCH_FUNC 6
109 #define SD_CMD_SEND_IF_COND 8
110 #define SD_CMD_SWITCH_UHS18V 11
112 #define SD_CMD_APP_SET_BUS_WIDTH 6
113 #define SD_CMD_APP_SD_STATUS 13
114 #define SD_CMD_ERASE_WR_BLK_START 32
115 #define SD_CMD_ERASE_WR_BLK_END 33
116 #define SD_CMD_APP_SEND_OP_COND 41
117 #define SD_CMD_APP_SEND_SCR 51
119 static inline bool mmc_is_tuning_cmd(uint cmdidx)
121 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
122 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
127 /* SCR definitions in different words */
128 #define SD_HIGHSPEED_BUSY 0x00020000
129 #define SD_HIGHSPEED_SUPPORTED 0x00020000
131 #define UHS_SDR12_BUS_SPEED 0
132 #define HIGH_SPEED_BUS_SPEED 1
133 #define UHS_SDR25_BUS_SPEED 1
134 #define UHS_SDR50_BUS_SPEED 2
135 #define UHS_SDR104_BUS_SPEED 3
136 #define UHS_DDR50_BUS_SPEED 4
138 #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
139 #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
140 #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
141 #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
142 #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
144 #define OCR_BUSY 0x80000000
145 #define OCR_HCS 0x40000000
146 #define OCR_S18R 0x1000000
147 #define OCR_VOLTAGE_MASK 0x007FFF80
148 #define OCR_ACCESS_MODE 0x60000000
150 #define MMC_ERASE_ARG 0x00000000
151 #define MMC_SECURE_ERASE_ARG 0x80000000
152 #define MMC_TRIM_ARG 0x00000001
153 #define MMC_DISCARD_ARG 0x00000003
154 #define MMC_SECURE_TRIM1_ARG 0x80000001
155 #define MMC_SECURE_TRIM2_ARG 0x80008000
157 #define MMC_STATUS_MASK (~0x0206BF7F)
158 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
159 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
160 #define MMC_STATUS_CURR_STATE (0xf << 9)
161 #define MMC_STATUS_ERROR (1 << 19)
163 #define MMC_STATE_PRG (7 << 9)
165 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
166 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
167 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
168 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
169 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
170 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
171 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
172 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
173 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
174 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
175 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
176 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
177 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
178 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
179 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
180 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
181 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
183 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
184 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
185 addressed by index which are
187 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
188 addressed by index, which are
190 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
192 #define SD_SWITCH_CHECK 0
193 #define SD_SWITCH_SWITCH 1
198 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
199 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
200 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
201 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
202 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
203 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
204 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
205 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
206 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
207 #define EXT_CSD_WR_REL_PARAM 166 /* R */
208 #define EXT_CSD_WR_REL_SET 167 /* R/W */
209 #define EXT_CSD_RPMB_MULT 168 /* RO */
210 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
211 #define EXT_CSD_BOOT_BUS_WIDTH 177
212 #define EXT_CSD_PART_CONF 179 /* R/W */
213 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
214 #define EXT_CSD_HS_TIMING 185 /* R/W */
215 #define EXT_CSD_REV 192 /* RO */
216 #define EXT_CSD_CARD_TYPE 196 /* RO */
217 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
218 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
219 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
220 #define EXT_CSD_BOOT_MULT 226 /* RO */
221 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
224 * EXT_CSD field definitions
227 #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
228 #define EXT_CSD_CMD_SET_SECURE (1 << 1)
229 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
231 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
232 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
233 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
234 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
235 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
236 | EXT_CSD_CARD_TYPE_DDR_1_2V)
238 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
239 /* SDR mode @1.8V I/O */
240 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
241 /* SDR mode @1.2V I/O */
242 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
243 EXT_CSD_CARD_TYPE_HS200_1_2V)
245 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
246 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
247 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
248 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
249 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
250 #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
252 #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
253 #define EXT_CSD_TIMING_HS 1 /* HS */
254 #define EXT_CSD_TIMING_HS200 2 /* HS200 */
256 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
257 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
258 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
259 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
261 #define EXT_CSD_BOOT_ACK(x) (x << 6)
262 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
263 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
265 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
266 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
267 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
269 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
270 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
271 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
273 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
275 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
276 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
278 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
280 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
281 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
283 #define R1_ILLEGAL_COMMAND (1 << 22)
284 #define R1_APP_CMD (1 << 5)
286 #define MMC_RSP_PRESENT (1 << 0)
287 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
288 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
289 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
290 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
292 #define MMC_RSP_NONE (0)
293 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
294 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
296 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
297 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
298 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
299 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
300 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
301 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
303 #define MMCPART_NOAVAILABLE (0xff)
304 #define PART_ACCESS_MASK (0x7)
305 #define PART_SUPPORT (0x1)
306 #define ENHNCD_SUPPORT (0x2)
307 #define PART_ENH_ATTRIB (0x1f)
309 #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
310 #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
313 MMC_SIGNAL_VOLTAGE_000 = 0,
314 MMC_SIGNAL_VOLTAGE_120 = 1,
315 MMC_SIGNAL_VOLTAGE_180 = 2,
316 MMC_SIGNAL_VOLTAGE_330 = 4,
319 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
320 MMC_SIGNAL_VOLTAGE_180 |\
321 MMC_SIGNAL_VOLTAGE_330)
323 /* Maximum block size for MMC */
324 #define MMC_MAX_BLOCK_LEN 512
326 /* The number of MMC physical partitions. These consist of:
327 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
329 #define MMC_NUM_BOOT_PARTITION 2
330 #define MMC_PART_RPMB 3 /* RPMB partition number */
332 /* Driver model support */
335 * struct mmc_uclass_priv - Holds information about a device used by the uclass
337 struct mmc_uclass_priv {
342 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
344 * Provided that the device is already probed and ready for use, this value
348 * @return associated mmc struct pointer if available, else NULL
350 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
352 /* End of driver model support */
373 const char *src; /* src buffers don't get written to */
383 #if CONFIG_IS_ENABLED(DM_MMC)
386 * send_cmd() - Send a command to the MMC device
388 * @dev: Device to receive the command
389 * @cmd: Command to send
390 * @data: Additional data to send/receive
391 * @return 0 if OK, -ve on error
393 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
394 struct mmc_data *data);
397 * set_ios() - Set the I/O speed/width for an MMC device
399 * @dev: Device to update
400 * @return 0 if OK, -ve on error
402 int (*set_ios)(struct udevice *dev);
405 * send_init_stream() - send the initialization stream: 74 clock cycles
406 * This is used after power up before sending the first command
408 * @dev: Device to update
410 void (*send_init_stream)(struct udevice *dev);
413 * get_cd() - See whether a card is present
415 * @dev: Device to check
416 * @return 0 if not present, 1 if present, -ve on error
418 int (*get_cd)(struct udevice *dev);
421 * get_wp() - See whether a card has write-protect enabled
423 * @dev: Device to check
424 * @return 0 if write-enabled, 1 if write-protected, -ve on error
426 int (*get_wp)(struct udevice *dev);
429 * execute_tuning() - Start the tuning process
431 * @dev: Device to start the tuning
432 * @opcode: Command opcode to send
433 * @return 0 if OK, -ve on error
435 int (*execute_tuning)(struct udevice *dev, uint opcode);
438 * wait_dat0() - wait until dat0 is in the target state
439 * (CLK must be running during the wait)
441 * @dev: Device to check
442 * @state: target state
443 * @timeout: timeout in us
444 * @return 0 if dat0 is in the target state, -ve on error
446 int (*wait_dat0)(struct udevice *dev, int state, int timeout);
449 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
451 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
452 struct mmc_data *data);
453 int dm_mmc_set_ios(struct udevice *dev);
454 void dm_mmc_send_init_stream(struct udevice *dev);
455 int dm_mmc_get_cd(struct udevice *dev);
456 int dm_mmc_get_wp(struct udevice *dev);
457 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
458 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
460 /* Transition functions for compatibility */
461 int mmc_set_ios(struct mmc *mmc);
462 void mmc_send_init_stream(struct mmc *mmc);
463 int mmc_getcd(struct mmc *mmc);
464 int mmc_getwp(struct mmc *mmc);
465 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
466 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
470 int (*send_cmd)(struct mmc *mmc,
471 struct mmc_cmd *cmd, struct mmc_data *data);
472 int (*set_ios)(struct mmc *mmc);
473 int (*init)(struct mmc *mmc);
474 int (*getcd)(struct mmc *mmc);
475 int (*getwp)(struct mmc *mmc);
481 #if !CONFIG_IS_ENABLED(DM_MMC)
482 const struct mmc_ops *ops;
489 unsigned char part_type;
493 unsigned int au; /* In sectors */
494 unsigned int erase_timeout; /* In milliseconds */
495 unsigned int erase_offset; /* In milliseconds */
514 const char *mmc_mode_name(enum bus_mode mode);
515 void mmc_dump_capabilities(const char *text, uint caps);
517 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
519 if ((mode == MMC_DDR_52) || (mode == UHS_DDR50))
525 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
526 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
529 static inline bool supports_uhs(uint caps)
531 return (caps & UHS_CAPS) ? true : false;
535 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
536 * with mmc_get_mmc_dev().
538 * TODO struct mmc should be in mmc_private but it's hard to fix right now
541 #if !CONFIG_IS_ENABLED(BLK)
542 struct list_head link;
544 const struct mmc_config *cfg; /* provided configuration */
549 bool clk_disable; /* true if the clock can be turned off */
552 enum mmc_voltage signal_voltage;
567 uint legacy_speed; /* speed for the legacy mode provided by the card */
570 uint erase_grp_size; /* in 512-byte sectors */
571 uint hc_wp_grp_size; /* in 512-byte sectors */
572 struct sd_ssr ssr; /* SD status register */
580 #if !CONFIG_IS_ENABLED(BLK)
581 struct blk_desc block_dev;
583 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
584 char init_in_progress; /* 1 if we have done mmc_start_init() */
585 char preinit; /* start init as early as possible */
587 #if CONFIG_IS_ENABLED(DM_MMC)
588 struct udevice *dev; /* Device for this MMC controller */
589 #if CONFIG_IS_ENABLED(DM_REGULATOR)
590 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
591 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
595 u32 cardtype; /* cardtype read from the MMC */
596 enum mmc_voltage current_voltage;
597 enum bus_mode selected_mode; /* mode currently used */
598 enum bus_mode best_mode; /* best mode is the supported mode with the
599 * highest bandwidth. It may not always be the
600 * operating mode due to limitations when
601 * accessing the boot partitions
606 struct mmc_hwpart_conf {
608 uint enh_start; /* in 512-byte sectors */
609 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
610 unsigned wr_rel_change : 1;
611 unsigned wr_rel_set : 1;
614 uint size; /* in 512-byte sectors */
615 unsigned enhanced : 1;
616 unsigned wr_rel_change : 1;
617 unsigned wr_rel_set : 1;
621 enum mmc_hwpart_conf_mode {
622 MMC_HWPART_CONF_CHECK,
624 MMC_HWPART_CONF_COMPLETE,
627 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
630 * mmc_bind() - Set up a new MMC device ready for probing
632 * A child block device is bound with the IF_TYPE_MMC interface type. This
633 * allows the device to be used with CONFIG_BLK
635 * @dev: MMC device to set up
637 * @cfg: MMC configuration
638 * @return 0 if OK, -ve on error
640 int mmc_bind(struct udevice *dev, struct mmc *mmc,
641 const struct mmc_config *cfg);
642 void mmc_destroy(struct mmc *mmc);
645 * mmc_unbind() - Unbind a MMC device's child block device
648 * @return 0 if OK, -ve on error
650 int mmc_unbind(struct udevice *dev);
651 int mmc_initialize(bd_t *bis);
652 int mmc_init(struct mmc *mmc);
653 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
656 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
659 * @cfg: MMC configuration
660 * @return 0 if OK, -ve on error
662 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
664 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
667 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
669 * @voltage: The mmc_voltage to convert
670 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
672 int mmc_voltage_to_mv(enum mmc_voltage voltage);
675 * mmc_set_clock() - change the bus clock
677 * @clock: bus frequency in Hz
678 * @disable: flag indicating if the clock must on or off
679 * @return 0 if OK, -ve on error
681 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
683 struct mmc *find_mmc_device(int dev_num);
684 int mmc_set_dev(int dev_num);
685 void print_mmc_devices(char separator);
688 * get_mmc_num() - get the total MMC device number
690 * @return 0 if there is no MMC device, else the number of devices
692 int get_mmc_num(void);
693 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
694 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
695 enum mmc_hwpart_conf_mode mode);
697 #if !CONFIG_IS_ENABLED(DM_MMC)
698 int mmc_getcd(struct mmc *mmc);
699 int board_mmc_getcd(struct mmc *mmc);
700 int mmc_getwp(struct mmc *mmc);
701 int board_mmc_getwp(struct mmc *mmc);
704 int mmc_set_dsr(struct mmc *mmc, u16 val);
705 /* Function to change the size of boot partition and rpmb partitions */
706 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
707 unsigned long rpmbsize);
708 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
709 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
710 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
711 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
712 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
713 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
714 /* Functions to read / write the RPMB partition */
715 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
716 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
717 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
718 unsigned short cnt, unsigned char *key);
719 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
720 unsigned short cnt, unsigned char *key);
721 #ifdef CONFIG_CMD_BKOPS_ENABLE
722 int mmc_set_bkops_enable(struct mmc *mmc);
726 * Start device initialization and return immediately; it does not block on
727 * polling OCR (operation condition register) status. Then you should call
728 * mmc_init, which would block on polling OCR status and complete the device
731 * @param mmc Pointer to a MMC device struct
732 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
734 int mmc_start_init(struct mmc *mmc);
737 * Set preinit flag of mmc device.
739 * This will cause the device to be pre-inited during mmc_initialize(),
740 * which may save boot time if the device is not accessed until later.
741 * Some eMMC devices take 200-300ms to init, but unfortunately they
742 * must be sent a series of commands to even get them to start preparing
745 * @param mmc Pointer to a MMC device struct
746 * @param preinit preinit flag value
748 void mmc_set_preinit(struct mmc *mmc, int preinit);
750 #ifdef CONFIG_MMC_SPI
751 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
753 #define mmc_host_is_spi(mmc) 0
755 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
757 void board_mmc_power_init(void);
758 int board_mmc_init(bd_t *bis);
759 int cpu_mmc_init(bd_t *bis);
760 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
761 int mmc_get_env_dev(void);
763 /* Set block count limit because of 16 bit register limit on some hardware*/
764 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
765 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
769 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
772 * @return block device if found, else NULL
774 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);