1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2008,2010 Freescale Semiconductor, Inc
6 * Based (loosely) on the Linux code
12 #include <linux/list.h>
13 #include <linux/sizes.h>
14 #include <linux/compiler.h>
15 #include <linux/dma-direction.h>
20 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
21 #define MMC_SUPPORTS_TUNING
23 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
24 #define MMC_SUPPORTS_TUNING
27 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
28 #define SD_VERSION_SD (1U << 31)
29 #define MMC_VERSION_MMC (1U << 30)
31 #define MAKE_SDMMC_VERSION(a, b, c) \
32 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
33 #define MAKE_SD_VERSION(a, b, c) \
34 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
35 #define MAKE_MMC_VERSION(a, b, c) \
36 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
38 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
39 (((u32)(x) >> 16) & 0xff)
40 #define EXTRACT_SDMMC_MINOR_VERSION(x) \
41 (((u32)(x) >> 8) & 0xff)
42 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
45 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
46 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
47 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
48 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
50 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
51 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
52 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
53 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
54 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
55 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
56 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
57 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
58 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
59 #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
60 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
61 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
62 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
63 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
65 #define MMC_CAP(mode) (1 << mode)
66 #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
67 #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
68 #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
69 #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
70 #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
71 #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
73 #define MMC_CAP_NONREMOVABLE BIT(14)
74 #define MMC_CAP_NEEDS_POLL BIT(15)
75 #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
77 #define MMC_MODE_8BIT BIT(30)
78 #define MMC_MODE_4BIT BIT(29)
79 #define MMC_MODE_1BIT BIT(28)
80 #define MMC_MODE_SPI BIT(27)
83 #define SD_DATA_4BIT 0x00040000
85 #define IS_SD(x) ((x)->version & SD_VERSION_SD)
86 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
88 #define MMC_DATA_READ 1
89 #define MMC_DATA_WRITE 2
91 #define MMC_CMD_GO_IDLE_STATE 0
92 #define MMC_CMD_SEND_OP_COND 1
93 #define MMC_CMD_ALL_SEND_CID 2
94 #define MMC_CMD_SET_RELATIVE_ADDR 3
95 #define MMC_CMD_SET_DSR 4
96 #define MMC_CMD_SWITCH 6
97 #define MMC_CMD_SELECT_CARD 7
98 #define MMC_CMD_SEND_EXT_CSD 8
99 #define MMC_CMD_SEND_CSD 9
100 #define MMC_CMD_SEND_CID 10
101 #define MMC_CMD_STOP_TRANSMISSION 12
102 #define MMC_CMD_SEND_STATUS 13
103 #define MMC_CMD_SET_BLOCKLEN 16
104 #define MMC_CMD_READ_SINGLE_BLOCK 17
105 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
106 #define MMC_CMD_SEND_TUNING_BLOCK 19
107 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
108 #define MMC_CMD_SET_BLOCK_COUNT 23
109 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
110 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
111 #define MMC_CMD_ERASE_GROUP_START 35
112 #define MMC_CMD_ERASE_GROUP_END 36
113 #define MMC_CMD_ERASE 38
114 #define MMC_CMD_APP_CMD 55
115 #define MMC_CMD_SPI_READ_OCR 58
116 #define MMC_CMD_SPI_CRC_ON_OFF 59
117 #define MMC_CMD_RES_MAN 62
119 #define MMC_CMD62_ARG1 0xefac62ec
120 #define MMC_CMD62_ARG2 0xcbaea7
123 #define SD_CMD_SEND_RELATIVE_ADDR 3
124 #define SD_CMD_SWITCH_FUNC 6
125 #define SD_CMD_SEND_IF_COND 8
126 #define SD_CMD_SWITCH_UHS18V 11
128 #define SD_CMD_APP_SET_BUS_WIDTH 6
129 #define SD_CMD_APP_SD_STATUS 13
130 #define SD_CMD_ERASE_WR_BLK_START 32
131 #define SD_CMD_ERASE_WR_BLK_END 33
132 #define SD_CMD_APP_SEND_OP_COND 41
133 #define SD_CMD_APP_SEND_SCR 51
135 static inline bool mmc_is_tuning_cmd(uint cmdidx)
137 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
138 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
143 /* SCR definitions in different words */
144 #define SD_HIGHSPEED_BUSY 0x00020000
145 #define SD_HIGHSPEED_SUPPORTED 0x00020000
147 #define UHS_SDR12_BUS_SPEED 0
148 #define HIGH_SPEED_BUS_SPEED 1
149 #define UHS_SDR25_BUS_SPEED 1
150 #define UHS_SDR50_BUS_SPEED 2
151 #define UHS_SDR104_BUS_SPEED 3
152 #define UHS_DDR50_BUS_SPEED 4
154 #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
155 #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
156 #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
157 #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
158 #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
160 #define OCR_BUSY 0x80000000
161 #define OCR_HCS 0x40000000
162 #define OCR_S18R 0x1000000
163 #define OCR_VOLTAGE_MASK 0x007FFF80
164 #define OCR_ACCESS_MODE 0x60000000
166 #define MMC_ERASE_ARG 0x00000000
167 #define MMC_SECURE_ERASE_ARG 0x80000000
168 #define MMC_TRIM_ARG 0x00000001
169 #define MMC_DISCARD_ARG 0x00000003
170 #define MMC_SECURE_TRIM1_ARG 0x80000001
171 #define MMC_SECURE_TRIM2_ARG 0x80008000
173 #define MMC_STATUS_MASK (~0x0206BF7F)
174 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
175 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
176 #define MMC_STATUS_CURR_STATE (0xf << 9)
177 #define MMC_STATUS_ERROR (1 << 19)
179 #define MMC_STATE_PRG (7 << 9)
181 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
182 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
183 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
184 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
185 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
186 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
187 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
188 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
189 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
190 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
191 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
192 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
193 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
194 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
195 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
196 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
197 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
199 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
200 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
201 addressed by index which are
203 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
204 addressed by index, which are
206 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
208 #define SD_SWITCH_CHECK 0
209 #define SD_SWITCH_SWITCH 1
214 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
215 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
216 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
217 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
218 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
219 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
220 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
221 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
222 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
223 #define EXT_CSD_WR_REL_PARAM 166 /* R */
224 #define EXT_CSD_WR_REL_SET 167 /* R/W */
225 #define EXT_CSD_RPMB_MULT 168 /* RO */
226 #define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
227 #define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
228 #define EXT_CSD_BOOT_WP_STATUS 174 /* R */
229 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
230 #define EXT_CSD_BOOT_BUS_WIDTH 177
231 #define EXT_CSD_PART_CONF 179 /* R/W */
232 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
233 #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
234 #define EXT_CSD_HS_TIMING 185 /* R/W */
235 #define EXT_CSD_REV 192 /* RO */
236 #define EXT_CSD_CARD_TYPE 196 /* RO */
237 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
238 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
239 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
240 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
241 #define EXT_CSD_BOOT_MULT 226 /* RO */
242 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
243 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
246 * EXT_CSD field definitions
249 #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
250 #define EXT_CSD_CMD_SET_SECURE (1 << 1)
251 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
253 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
254 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
255 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
256 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
257 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
258 | EXT_CSD_CARD_TYPE_DDR_1_2V)
260 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
261 /* SDR mode @1.8V I/O */
262 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
263 /* SDR mode @1.2V I/O */
264 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
265 EXT_CSD_CARD_TYPE_HS200_1_2V)
266 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
267 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
268 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
269 EXT_CSD_CARD_TYPE_HS400_1_2V)
271 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
272 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
273 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
274 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
275 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
276 #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
277 #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
279 #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
280 #define EXT_CSD_TIMING_HS 1 /* HS */
281 #define EXT_CSD_TIMING_HS200 2 /* HS200 */
282 #define EXT_CSD_TIMING_HS400 3 /* HS400 */
283 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
285 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
286 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
287 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
288 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
290 #define EXT_CSD_BOOT_ACK(x) (x << 6)
291 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
292 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
294 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
295 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
296 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
298 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
299 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
300 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
302 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
304 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
305 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
307 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
309 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
310 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
312 #define R1_ILLEGAL_COMMAND (1 << 22)
313 #define R1_APP_CMD (1 << 5)
315 #define MMC_RSP_PRESENT (1 << 0)
316 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
317 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
318 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
319 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
321 #define MMC_RSP_NONE (0)
322 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
323 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
325 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
326 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
327 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
328 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
329 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
330 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
332 #define MMCPART_NOAVAILABLE (0xff)
333 #define PART_ACCESS_MASK (0x7)
334 #define PART_SUPPORT (0x1)
335 #define ENHNCD_SUPPORT (0x2)
336 #define PART_ENH_ATTRIB (0x1f)
338 #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
339 #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
340 #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
343 MMC_SIGNAL_VOLTAGE_000 = 0,
344 MMC_SIGNAL_VOLTAGE_120 = 1,
345 MMC_SIGNAL_VOLTAGE_180 = 2,
346 MMC_SIGNAL_VOLTAGE_330 = 4,
349 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
350 MMC_SIGNAL_VOLTAGE_180 |\
351 MMC_SIGNAL_VOLTAGE_330)
353 /* Maximum block size for MMC */
354 #define MMC_MAX_BLOCK_LEN 512
356 /* The number of MMC physical partitions. These consist of:
357 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
359 #define MMC_NUM_BOOT_PARTITION 2
360 #define MMC_PART_RPMB 3 /* RPMB partition number */
362 /* Driver model support */
365 * struct mmc_uclass_priv - Holds information about a device used by the uclass
367 struct mmc_uclass_priv {
372 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
374 * Provided that the device is already probed and ready for use, this value
378 * @return associated mmc struct pointer if available, else NULL
380 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
382 /* End of driver model support */
403 const char *src; /* src buffers don't get written to */
413 #if CONFIG_IS_ENABLED(DM_MMC)
416 * deferred_probe() - Some configurations that need to be deferred
417 * to just before enumerating the device
419 * @dev: Device to init
420 * @return 0 if Ok, -ve if error
422 int (*deferred_probe)(struct udevice *dev);
424 * send_cmd() - Send a command to the MMC device
426 * @dev: Device to receive the command
427 * @cmd: Command to send
428 * @data: Additional data to send/receive
429 * @return 0 if OK, -ve on error
431 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
432 struct mmc_data *data);
435 * set_ios() - Set the I/O speed/width for an MMC device
437 * @dev: Device to update
438 * @return 0 if OK, -ve on error
440 int (*set_ios)(struct udevice *dev);
443 * get_cd() - See whether a card is present
445 * @dev: Device to check
446 * @return 0 if not present, 1 if present, -ve on error
448 int (*get_cd)(struct udevice *dev);
451 * get_wp() - See whether a card has write-protect enabled
453 * @dev: Device to check
454 * @return 0 if write-enabled, 1 if write-protected, -ve on error
456 int (*get_wp)(struct udevice *dev);
458 #ifdef MMC_SUPPORTS_TUNING
460 * execute_tuning() - Start the tuning process
462 * @dev: Device to start the tuning
463 * @opcode: Command opcode to send
464 * @return 0 if OK, -ve on error
466 int (*execute_tuning)(struct udevice *dev, uint opcode);
470 * wait_dat0() - wait until dat0 is in the target state
471 * (CLK must be running during the wait)
473 * @dev: Device to check
474 * @state: target state
475 * @timeout_us: timeout in us
476 * @return 0 if dat0 is in the target state, -ve on error
478 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
480 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
481 /* set_enhanced_strobe() - set HS400 enhanced strobe */
482 int (*set_enhanced_strobe)(struct udevice *dev);
486 * host_power_cycle - host specific tasks in power cycle sequence
487 * Called between mmc_power_off() and
490 * @dev: Device to check
491 * @return 0 if not present, 1 if present, -ve on error
493 int (*host_power_cycle)(struct udevice *dev);
496 * get_b_max - get maximum length of single transfer
497 * Called before reading blocks from the card,
498 * useful for system which have e.g. DMA limits
499 * on various memory ranges.
501 * @dev: Device to check
502 * @dst: Destination buffer in memory
503 * @blkcnt: Total number of blocks in this transfer
504 * @return maximum number of blocks for this transfer
506 int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
509 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
511 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
512 struct mmc_data *data);
513 int dm_mmc_set_ios(struct udevice *dev);
514 int dm_mmc_get_cd(struct udevice *dev);
515 int dm_mmc_get_wp(struct udevice *dev);
516 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
517 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
518 int dm_mmc_host_power_cycle(struct udevice *dev);
519 int dm_mmc_deferred_probe(struct udevice *dev);
520 int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
522 /* Transition functions for compatibility */
523 int mmc_set_ios(struct mmc *mmc);
524 int mmc_getcd(struct mmc *mmc);
525 int mmc_getwp(struct mmc *mmc);
526 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
527 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
528 int mmc_set_enhanced_strobe(struct mmc *mmc);
529 int mmc_host_power_cycle(struct mmc *mmc);
530 int mmc_deferred_probe(struct mmc *mmc);
531 int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
535 int (*send_cmd)(struct mmc *mmc,
536 struct mmc_cmd *cmd, struct mmc_data *data);
537 int (*set_ios)(struct mmc *mmc);
538 int (*init)(struct mmc *mmc);
539 int (*getcd)(struct mmc *mmc);
540 int (*getwp)(struct mmc *mmc);
541 int (*host_power_cycle)(struct mmc *mmc);
542 int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
548 #if !CONFIG_IS_ENABLED(DM_MMC)
549 const struct mmc_ops *ops;
556 unsigned char part_type;
560 unsigned int au; /* In sectors */
561 unsigned int erase_timeout; /* In milliseconds */
562 unsigned int erase_offset; /* In milliseconds */
582 const char *mmc_mode_name(enum bus_mode mode);
583 void mmc_dump_capabilities(const char *text, uint caps);
585 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
587 if (mode == MMC_DDR_52)
589 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
590 else if (mode == UHS_DDR50)
593 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
594 else if (mode == MMC_HS_400)
597 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
598 else if (mode == MMC_HS_400_ES)
605 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
606 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
609 static inline bool supports_uhs(uint caps)
611 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
612 return (caps & UHS_CAPS) ? true : false;
619 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
620 * with mmc_get_mmc_dev().
622 * TODO struct mmc should be in mmc_private but it's hard to fix right now
625 #if !CONFIG_IS_ENABLED(BLK)
626 struct list_head link;
628 const struct mmc_config *cfg; /* provided configuration */
633 bool clk_disable; /* true if the clock can be turned off */
637 enum mmc_voltage signal_voltage;
651 u8 gen_cmd6_time; /* units: 10 ms */
652 u8 part_switch_time; /* units: 10 ms */
654 uint legacy_speed; /* speed for the legacy mode provided by the card */
656 #if CONFIG_IS_ENABLED(MMC_WRITE)
658 uint erase_grp_size; /* in 512-byte sectors */
660 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
661 uint hc_wp_grp_size; /* in 512-byte sectors */
663 #if CONFIG_IS_ENABLED(MMC_WRITE)
664 struct sd_ssr ssr; /* SD status register */
671 #ifndef CONFIG_SPL_BUILD
675 #if !CONFIG_IS_ENABLED(BLK)
676 struct blk_desc block_dev;
678 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
679 char init_in_progress; /* 1 if we have done mmc_start_init() */
680 char preinit; /* start init as early as possible */
682 #if CONFIG_IS_ENABLED(DM_MMC)
683 struct udevice *dev; /* Device for this MMC controller */
684 #if CONFIG_IS_ENABLED(DM_REGULATOR)
685 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
686 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
690 u32 cardtype; /* cardtype read from the MMC */
691 enum mmc_voltage current_voltage;
692 enum bus_mode selected_mode; /* mode currently used */
693 enum bus_mode best_mode; /* best mode is the supported mode with the
694 * highest bandwidth. It may not always be the
695 * operating mode due to limitations when
696 * accessing the boot partitions
701 struct mmc_hwpart_conf {
703 uint enh_start; /* in 512-byte sectors */
704 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
705 unsigned wr_rel_change : 1;
706 unsigned wr_rel_set : 1;
709 uint size; /* in 512-byte sectors */
710 unsigned enhanced : 1;
711 unsigned wr_rel_change : 1;
712 unsigned wr_rel_set : 1;
716 enum mmc_hwpart_conf_mode {
717 MMC_HWPART_CONF_CHECK,
719 MMC_HWPART_CONF_COMPLETE,
722 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
725 * mmc_bind() - Set up a new MMC device ready for probing
727 * A child block device is bound with the IF_TYPE_MMC interface type. This
728 * allows the device to be used with CONFIG_BLK
730 * @dev: MMC device to set up
732 * @cfg: MMC configuration
733 * @return 0 if OK, -ve on error
735 int mmc_bind(struct udevice *dev, struct mmc *mmc,
736 const struct mmc_config *cfg);
737 void mmc_destroy(struct mmc *mmc);
740 * mmc_unbind() - Unbind a MMC device's child block device
743 * @return 0 if OK, -ve on error
745 int mmc_unbind(struct udevice *dev);
746 int mmc_initialize(struct bd_info *bis);
747 int mmc_init_device(int num);
748 int mmc_init(struct mmc *mmc);
749 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
751 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
752 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
753 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
754 int mmc_deinit(struct mmc *mmc);
758 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
761 * @cfg: MMC configuration
762 * @return 0 if OK, -ve on error
764 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
766 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
769 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
771 * @voltage: The mmc_voltage to convert
772 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
774 int mmc_voltage_to_mv(enum mmc_voltage voltage);
777 * mmc_set_clock() - change the bus clock
779 * @clock: bus frequency in Hz
780 * @disable: flag indicating if the clock must on or off
781 * @return 0 if OK, -ve on error
783 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
785 #define MMC_CLK_ENABLE false
786 #define MMC_CLK_DISABLE true
788 struct mmc *find_mmc_device(int dev_num);
789 int mmc_set_dev(int dev_num);
790 void print_mmc_devices(char separator);
793 * get_mmc_num() - get the total MMC device number
795 * @return 0 if there is no MMC device, else the number of devices
797 int get_mmc_num(void);
798 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
799 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
800 enum mmc_hwpart_conf_mode mode);
802 #if !CONFIG_IS_ENABLED(DM_MMC)
803 int mmc_getcd(struct mmc *mmc);
804 int board_mmc_getcd(struct mmc *mmc);
805 int mmc_getwp(struct mmc *mmc);
806 int board_mmc_getwp(struct mmc *mmc);
809 int mmc_set_dsr(struct mmc *mmc, u16 val);
810 /* Function to change the size of boot partition and rpmb partitions */
811 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
812 unsigned long rpmbsize);
813 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
814 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
815 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
816 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
817 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
818 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
819 /* Functions to read / write the RPMB partition */
820 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
821 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
822 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
823 unsigned short cnt, unsigned char *key);
824 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
825 unsigned short cnt, unsigned char *key);
828 * mmc_rpmb_route_frames() - route RPMB data frames
829 * @mmc Pointer to a MMC device struct
830 * @req Request data frames
831 * @reqlen Length of data frames in bytes
832 * @rsp Supplied buffer for response data frames
833 * @rsplen Length of supplied buffer for response data frames
835 * The RPMB data frames are routed to/from some external entity, for
836 * example a Trusted Exectuion Environment in an arm TrustZone protected
837 * secure world. It's expected that it's the external entity who is in
838 * control of the RPMB key.
840 * Returns 0 on success, < 0 on error.
842 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
843 void *rsp, unsigned long rsplen);
845 #ifdef CONFIG_CMD_BKOPS_ENABLE
846 int mmc_set_bkops_enable(struct mmc *mmc);
850 * Start device initialization and return immediately; it does not block on
851 * polling OCR (operation condition register) status. Useful for checking
852 * the presence of SD/eMMC when no card detect logic is available.
854 * @param mmc Pointer to a MMC device struct
855 * @return 0 on success, <0 on error.
857 int mmc_get_op_cond(struct mmc *mmc);
860 * Start device initialization and return immediately; it does not block on
861 * polling OCR (operation condition register) status. Then you should call
862 * mmc_init, which would block on polling OCR status and complete the device
865 * @param mmc Pointer to a MMC device struct
866 * @return 0 on success, <0 on error.
868 int mmc_start_init(struct mmc *mmc);
871 * Set preinit flag of mmc device.
873 * This will cause the device to be pre-inited during mmc_initialize(),
874 * which may save boot time if the device is not accessed until later.
875 * Some eMMC devices take 200-300ms to init, but unfortunately they
876 * must be sent a series of commands to even get them to start preparing
879 * @param mmc Pointer to a MMC device struct
880 * @param preinit preinit flag value
882 void mmc_set_preinit(struct mmc *mmc, int preinit);
884 #ifdef CONFIG_MMC_SPI
885 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
887 #define mmc_host_is_spi(mmc) 0
890 void board_mmc_power_init(void);
891 int board_mmc_init(struct bd_info *bis);
892 int cpu_mmc_init(struct bd_info *bis);
893 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
894 # ifdef CONFIG_SYS_MMC_ENV_PART
895 extern uint mmc_get_env_part(struct mmc *mmc);
897 int mmc_get_env_dev(void);
899 /* Minimum partition switch timeout in units of 10-milliseconds */
900 #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
902 /* Set block count limit because of 16 bit register limit on some hardware*/
903 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
904 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
908 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
911 * @return block device if found, else NULL
913 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
916 * mmc_send_ext_csd() - read the extended CSD register
919 * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
920 * the caller, e.g. using
921 * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
922 * Return: 0 for success
924 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
927 * mmc_boot_wp() - power on write protect boot partitions
929 * The boot partitions are write protected until the next power cycle.
931 * Return: 0 for success
933 int mmc_boot_wp(struct mmc *mmc);
935 static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
937 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;