1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* include/linux/usb/dwc3.h
4 * Copyright (c) 2012 Samsung Electronics Co. Ltd
6 * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
12 /* Global constants */
13 #define DWC3_ENDPOINTS_NUM 32
15 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
16 #define DWC3_EVENT_TYPE_MASK 0xfe
18 #define DWC3_EVENT_TYPE_DEV 0
19 #define DWC3_EVENT_TYPE_CARKIT 3
20 #define DWC3_EVENT_TYPE_I2C 4
22 #define DWC3_DEVICE_EVENT_DISCONNECT 0
23 #define DWC3_DEVICE_EVENT_RESET 1
24 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
25 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
26 #define DWC3_DEVICE_EVENT_WAKEUP 4
27 #define DWC3_DEVICE_EVENT_EOPF 6
28 #define DWC3_DEVICE_EVENT_SOF 7
29 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
30 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
31 #define DWC3_DEVICE_EVENT_OVERFLOW 11
33 #define DWC3_GEVNTCOUNT_MASK 0xfffc
34 #define DWC3_GSNPSID_MASK 0xffff0000
35 #define DWC3_GSNPSID_SHIFT 16
36 #define DWC3_GSNPSREV_MASK 0xffff
38 #define DWC3_REVISION_MASK 0xffff
40 #define DWC3_REG_OFFSET 0xC100
42 struct g_event_buffer {
49 struct d_physical_endpoint {
56 struct dwc3 { /* offset: 0xC100 */
100 u32 g_usb2i2cctl[16];
101 u32 g_usb2phyacc[16];
102 u32 g_usb3pipectl[16];
107 struct g_event_buffer g_evnt_buf[32];
130 struct d_physical_endpoint d_phy_ep_cmd[32];
155 /* Global Configuration Register */
156 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
157 #define DWC3_GCTL_U2RSTECN (1 << 16)
158 #define DWC3_GCTL_RAMCLKSEL(x) \
159 (((x) & DWC3_GCTL_CLK_MASK) << 6)
160 #define DWC3_GCTL_CLK_BUS (0)
161 #define DWC3_GCTL_CLK_PIPE (1)
162 #define DWC3_GCTL_CLK_PIPEHALF (2)
163 #define DWC3_GCTL_CLK_MASK (3)
164 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
165 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
166 #define DWC3_GCTL_PRTCAP_HOST 1
167 #define DWC3_GCTL_PRTCAP_DEVICE 2
168 #define DWC3_GCTL_PRTCAP_OTG 3
169 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
170 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
171 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
172 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
173 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
175 /* Global HWPARAMS1 Register */
176 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
177 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
178 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
180 /* Global USB2 PHY Configuration Register */
181 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
182 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
183 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
184 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
185 #define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
187 /* Global USB2 PHY Configuration Mask */
188 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
190 /* Global USB2 PHY Configuration Offset */
191 #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
193 #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
194 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
195 #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
196 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
198 /* Global USB3 PIPE Control Register */
199 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
200 #define DWC3_GUSB3PIPECTL_DISRXDETP3 (1 << 28)
201 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
203 /* Global TX Fifo Size Register */
204 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
205 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
207 /* Device Control Register */
208 #define DWC3_DCTL_RUN_STOP (1 << 31)
209 #define DWC3_DCTL_CSFTRST (1 << 30)
210 #define DWC3_DCTL_LSFTRST (1 << 29)
212 /* Global Frame Length Adjustment Register */
213 #define GFLADJ_30MHZ_REG_SEL (1 << 7)
214 #define GFLADJ_30MHZ(n) ((n) & 0x3f)
215 #define GFLADJ_30MHZ_DEFAULT 0x20
217 #ifdef CONFIG_USB_XHCI_DWC3
218 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
219 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
220 int dwc3_core_init(struct dwc3 *dwc3_reg);
221 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
223 #endif /* __DWC3_H_ */