1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
10 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
12 /* SDW Broadcast Device Number */
13 #define SDW_BROADCAST_DEV_NUM 15
15 /* SDW Enumeration Device Number */
16 #define SDW_ENUM_DEV_NUM 0
18 /* SDW Group Device Numbers */
19 #define SDW_GROUP12_DEV_NUM 12
20 #define SDW_GROUP13_DEV_NUM 13
22 /* SDW Master Device Number, not supported yet */
23 #define SDW_MASTER_DEV_NUM 14
25 #define SDW_NUM_DEV_ID_REGISTERS 6
26 /* frame shape defines */
29 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
30 * fill hole with 0, one more dummy entry is added
32 #define SDW_FRAME_ROWS 24
33 #define SDW_FRAME_COLS 8
34 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
36 #define SDW_FRAME_CTRL_BITS 48
37 #define SDW_MAX_DEVICES 11
39 #define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1)
41 #define SDW_DAI_ID_RANGE_START 100
42 #define SDW_DAI_ID_RANGE_END 200
45 SDW_PORT_DIRN_SINK = 0,
51 * constants for flow control, ports and transport
53 * these are bit masks as devices can have multiple capabilities
57 * flow modes for SDW port. These can be isochronous, tx controlled,
58 * rx controlled or async
60 #define SDW_PORT_FLOW_MODE_ISOCH 0
61 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
62 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
63 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
65 /* sample packaging for block. It can be per port or per channel */
66 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
67 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
70 * enum sdw_slave_status - Slave status
71 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
72 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
73 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
74 * @SDW_SLAVE_RESERVED: Reserved for future use
76 enum sdw_slave_status {
77 SDW_SLAVE_UNATTACHED = 0,
78 SDW_SLAVE_ATTACHED = 1,
80 SDW_SLAVE_RESERVED = 3,
84 * enum sdw_command_response - Command response as defined by SDW spec
85 * @SDW_CMD_OK: cmd was successful
86 * @SDW_CMD_IGNORED: cmd was ignored
87 * @SDW_CMD_FAIL: cmd was NACKed
88 * @SDW_CMD_TIMEOUT: cmd timedout
89 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
91 * NOTE: The enum is different than actual Spec as response in the Spec is
92 * combination of ACK/NAK bits
94 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
96 enum sdw_command_response {
101 SDW_CMD_FAIL_OTHER = 4,
104 /* block group count enum */
105 enum sdw_dpn_grouping {
106 SDW_BLK_GRP_CNT_1 = 0,
107 SDW_BLK_GRP_CNT_2 = 1,
108 SDW_BLK_GRP_CNT_3 = 2,
109 SDW_BLK_GRP_CNT_4 = 3,
113 * enum sdw_stream_type: data stream type
115 * @SDW_STREAM_PCM: PCM data stream
116 * @SDW_STREAM_PDM: PDM data stream
118 * spec doesn't define this, but is used in implementation
120 enum sdw_stream_type {
126 * enum sdw_data_direction: Data direction
128 * @SDW_DATA_DIR_RX: Data into Port
129 * @SDW_DATA_DIR_TX: Data out of Port
131 enum sdw_data_direction {
137 * enum sdw_port_data_mode: Data Port mode
139 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
141 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
142 * logic 1. The encoding will result in signal transitions at every bitslot
144 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
145 * logic 0. The encoding will result in no signal transitions
146 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
147 * a pseudo random data pattern that is transferred
149 enum sdw_port_data_mode {
150 SDW_PORT_DATA_MODE_NORMAL = 0,
151 SDW_PORT_DATA_MODE_STATIC_1 = 1,
152 SDW_PORT_DATA_MODE_STATIC_0 = 2,
153 SDW_PORT_DATA_MODE_PRBS = 3,
157 * SDW properties, defined in MIPI DisCo spec v1.0
159 enum sdw_clk_stop_reset_behave {
160 SDW_CLK_STOP_KEEP_STATUS = 1,
164 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
166 * @SDW_P15_READ_IGNORED: Read is ignored
167 * @SDW_P15_CMD_OK: Command is ok
169 enum sdw_p15_behave {
170 SDW_P15_READ_IGNORED = 0,
175 * enum sdw_dpn_type - Data port types
176 * @SDW_DPN_FULL: Full Data Port is supported
177 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
178 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
179 * are not implemented.
180 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
181 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
190 * enum sdw_clk_stop_mode - Clock Stop modes
191 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
193 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
194 * not capable of continuing operation seamlessly when the clock restarts
196 enum sdw_clk_stop_mode {
197 SDW_CLK_STOP_MODE0 = 0,
198 SDW_CLK_STOP_MODE1 = 1,
202 * struct sdw_dp0_prop - DP0 properties
203 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
205 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
207 * @num_words: number of wordlengths supported
208 * @words: wordlengths supported
209 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
211 * @simple_ch_prep_sm: If channel prepare sequence is required
212 * @imp_def_interrupts: If set, each bit corresponds to support for
213 * implementation-defined interrupts
215 * The wordlengths are specified by Spec as max, min AND number of
216 * discrete values, implementation can define based on the wordlengths they
219 struct sdw_dp0_prop {
224 bool BRA_flow_controlled;
225 bool simple_ch_prep_sm;
226 bool imp_def_interrupts;
230 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
231 * @bus_min_freq: Minimum bus frequency, in Hz
232 * @bus_max_freq: Maximum bus frequency, in Hz
233 * @bus_num_freq: Number of discrete frequencies supported
234 * @bus_freq: Discrete bus frequencies, in Hz
235 * @min_freq: Minimum sampling frequency, in Hz
236 * @max_freq: Maximum sampling bus frequency, in Hz
237 * @num_freq: Number of discrete sampling frequency supported
238 * @freq: Discrete sampling frequencies, in Hz
239 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
240 * sequence and bus clock configuration
241 * If 0, Channel Prepare can happen at any Bus clock rate
242 * If 1, Channel Prepare sequence shall happen only after Bus clock is
243 * changed to a frequency supported by this mode or compatible modes
244 * described by the next field
245 * @glitchless: Bitmap describing possible glitchless transitions from this
246 * Audio Mode to other Audio Modes
248 struct sdw_dpn_audio_mode {
262 * struct sdw_dpn_prop - Data Port DPn properties
264 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
266 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
268 * @num_words: Number of discrete supported wordlengths
269 * @words: Discrete supported wordlength
270 * @type: Data port type. Full, Simplified or Reduced
271 * @max_grouping: Maximum number of samples that can be grouped together for
273 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
275 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
276 * @imp_def_interrupts: If set, each bit corresponds to support for
277 * implementation-defined interrupts
278 * @max_ch: Maximum channels supported
279 * @min_ch: Minimum channels supported
280 * @num_ch: Number of discrete channels supported
281 * @ch: Discrete channels supported
282 * @num_ch_combinations: Number of channel combinations supported
283 * @ch_combinations: Channel combinations supported
284 * @modes: SDW mode supported
285 * @max_async_buffer: Number of samples that this port can buffer in
287 * @block_pack_mode: Type of block port mode supported
288 * @port_encoding: Payload Channel Sample encoding schemes supported
289 * @audio_modes: Audio modes supported
291 struct sdw_dpn_prop {
297 enum sdw_dpn_type type;
299 bool simple_ch_prep_sm;
301 u32 imp_def_interrupts;
306 u32 num_ch_combinations;
307 u32 *ch_combinations;
309 u32 max_async_buffer;
310 bool block_pack_mode;
312 struct sdw_dpn_audio_mode *audio_modes;
316 * struct sdw_slave_prop - SoundWire Slave properties
317 * @mipi_revision: Spec version of the implementation
318 * @wake_capable: Wake-up events are supported
319 * @test_mode_capable: If test mode is supported
320 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
321 * @simple_clk_stop_capable: Simple clock mode is supported
322 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
323 * Machine transitions, in milliseconds
324 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
325 * transitions, in milliseconds
326 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
327 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
328 * @high_PHY_capable: Slave is HighPHY capable
329 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
331 * @bank_delay_support: Slave implements bank delay/bridge support registers
332 * SCP_BankDelay and SCP_NextFrame
333 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
335 * @lane_control_support: Slave supports lane control
336 * @master_count: Number of Masters present on this Slave
337 * @source_ports: Bitmap identifying source ports
338 * @sink_ports: Bitmap identifying sink ports
339 * @dp0_prop: Data Port 0 properties
340 * @src_dpn_prop: Source Data Port N properties
341 * @sink_dpn_prop: Sink Data Port N properties
343 struct sdw_slave_prop {
346 bool test_mode_capable;
348 bool simple_clk_stop_capable;
349 u32 clk_stop_timeout;
351 enum sdw_clk_stop_reset_behave reset_behave;
352 bool high_PHY_capable;
354 bool bank_delay_support;
355 enum sdw_p15_behave p15_behave;
356 bool lane_control_support;
360 struct sdw_dp0_prop *dp0_prop;
361 struct sdw_dpn_prop *src_dpn_prop;
362 struct sdw_dpn_prop *sink_dpn_prop;
366 * struct sdw_master_prop - Master properties
367 * @revision: MIPI spec version of the implementation
368 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
369 * @max_clk_freq: Maximum Bus clock frequency, in Hz
370 * @num_clk_gears: Number of clock gears supported
371 * @clk_gears: Clock gears supported
372 * @num_clk_freq: Number of clock frequencies supported, in Hz
373 * @clk_freq: Clock frequencies supported, in Hz
374 * @default_frame_rate: Controller default Frame rate, in Hz
375 * @default_row: Number of rows
376 * @default_col: Number of columns
377 * @dynamic_frame: Dynamic frame shape supported
378 * @err_threshold: Number of times that software may retry sending a single
381 struct sdw_master_prop {
389 u32 default_frame_rate;
396 int sdw_master_read_prop(struct sdw_bus *bus);
397 int sdw_slave_read_prop(struct sdw_slave *slave);
400 * SDW Slave Structures and APIs
404 * struct sdw_slave_id - Slave ID
405 * @mfg_id: MIPI Manufacturer ID
406 * @part_id: Device Part ID
407 * @class_id: MIPI Class ID, unused now.
408 * Currently a placeholder in MIPI SoundWire Spec
409 * @unique_id: Device unique ID
410 * @sdw_version: SDW version implemented
412 * The order of the IDs here does not follow the DisCo spec definitions
414 struct sdw_slave_id {
423 * struct sdw_slave_intr_status - Slave interrupt status
424 * @control_port: control port status
425 * @port: data port status
427 struct sdw_slave_intr_status {
433 * sdw_reg_bank - SoundWire register banks
434 * @SDW_BANK0: Soundwire register bank 0
435 * @SDW_BANK1: Soundwire register bank 1
443 * struct sdw_bus_conf: Bus configuration
445 * @clk_freq: Clock frequency, in Hz
446 * @num_rows: Number of rows in frame
447 * @num_cols: Number of columns in frame
448 * @bank: Next register bank
450 struct sdw_bus_conf {
451 unsigned int clk_freq;
452 unsigned int num_rows;
453 unsigned int num_cols;
458 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
461 * @ch_mask: Active channel mask
462 * @prepare: Prepare (true) /de-prepare (false) channel
463 * @bank: Register bank, which bank Slave/Master driver should program for
464 * implementation defined registers. This is always updated to next_bank
465 * value read from bus params.
468 struct sdw_prepare_ch {
470 unsigned int ch_mask;
476 * enum sdw_port_prep_ops: Prepare operations for Data Port
478 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
479 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
480 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
482 enum sdw_port_prep_ops {
483 SDW_OPS_PORT_PRE_PREP = 0,
484 SDW_OPS_PORT_PREP = 1,
485 SDW_OPS_PORT_POST_PREP = 2,
489 * struct sdw_bus_params: Structure holding bus configuration
491 * @curr_bank: Current bank in use (BANK0/BANK1)
492 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
494 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
495 * @curr_dr_freq: Current double rate clock frequency, in Hz
496 * @bandwidth: Current bandwidth
497 * @col: Active columns
500 struct sdw_bus_params {
501 enum sdw_reg_bank curr_bank;
502 enum sdw_reg_bank next_bank;
503 unsigned int max_dr_freq;
504 unsigned int curr_dr_freq;
505 unsigned int bandwidth;
511 * struct sdw_slave_ops: Slave driver callback ops
513 * @read_prop: Read Slave properties
514 * @interrupt_callback: Device interrupt notification (invoked in thread
516 * @update_status: Update Slave status
517 * @bus_config: Update the bus config for Slave
518 * @port_prep: Prepare the port with parameters
520 struct sdw_slave_ops {
521 int (*read_prop)(struct sdw_slave *sdw);
522 int (*interrupt_callback)(struct sdw_slave *slave,
523 struct sdw_slave_intr_status *status);
524 int (*update_status)(struct sdw_slave *slave,
525 enum sdw_slave_status status);
526 int (*bus_config)(struct sdw_slave *slave,
527 struct sdw_bus_params *params);
528 int (*port_prep)(struct sdw_slave *slave,
529 struct sdw_prepare_ch *prepare_ch,
530 enum sdw_port_prep_ops pre_ops);
534 * struct sdw_slave - SoundWire Slave
535 * @id: MIPI device ID
537 * @status: Status reported by the Slave
539 * @ops: Slave callback ops
540 * @prop: Slave properties
541 * @node: node for bus list
542 * @port_ready: Port ready completion flag for each Slave port
543 * @dev_num: Device Number assigned by Bus
546 struct sdw_slave_id id;
548 enum sdw_slave_status status;
550 const struct sdw_slave_ops *ops;
551 struct sdw_slave_prop prop;
552 struct list_head node;
553 struct completion *port_ready;
557 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
562 int (*probe)(struct sdw_slave *sdw,
563 const struct sdw_device_id *id);
564 int (*remove)(struct sdw_slave *sdw);
565 void (*shutdown)(struct sdw_slave *sdw);
567 const struct sdw_device_id *id_table;
568 const struct sdw_slave_ops *ops;
570 struct device_driver driver;
573 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
574 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
575 .driver_data = (unsigned long)(_drv_data) }
577 int sdw_handle_slave_status(struct sdw_bus *bus,
578 enum sdw_slave_status status[]);
581 * SDW master structures and APIs
585 * struct sdw_port_params: Data Port parameters
588 * @bps: Word length of the Port
589 * @flow_mode: Port Data flow mode
590 * @data_mode: Test modes or normal mode
592 * This is used to program the Data Port based on Data Port stream
595 struct sdw_port_params {
598 unsigned int flow_mode;
599 unsigned int data_mode;
603 * struct sdw_transport_params: Data Port Transport Parameters
605 * @blk_grp_ctrl_valid: Port implements block group control
607 * @blk_grp_ctrl: Block group control value
608 * @sample_interval: Sample interval
609 * @offset1: Blockoffset of the payload data
610 * @offset2: Blockoffset of the payload data
611 * @hstart: Horizontal start of the payload data
612 * @hstop: Horizontal stop of the payload data
613 * @blk_pkg_mode: Block per channel or block per port
614 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
615 * data lane is supported in bus
617 * This is used to program the Data Port based on Data Port transport
618 * parameters. All these parameters are banked and can be modified
619 * during a bank switch without any artifacts in audio stream.
621 struct sdw_transport_params {
622 bool blk_grp_ctrl_valid;
623 unsigned int port_num;
624 unsigned int blk_grp_ctrl;
625 unsigned int sample_interval;
626 unsigned int offset1;
627 unsigned int offset2;
630 unsigned int blk_pkg_mode;
631 unsigned int lane_ctrl;
635 * struct sdw_enable_ch: Enable/disable Data Port channel
638 * @ch_mask: Active channel mask
639 * @enable: Enable (true) /disable (false) channel
641 struct sdw_enable_ch {
642 unsigned int port_num;
643 unsigned int ch_mask;
648 * struct sdw_master_port_ops: Callback functions from bus to Master
649 * driver to set Master Data ports.
651 * @dpn_set_port_params: Set the Port parameters for the Master Port.
653 * @dpn_set_port_transport_params: Set transport parameters for the Master
654 * Port. Mandatory callback
655 * @dpn_port_prep: Port prepare operations for the Master Data Port.
656 * @dpn_port_enable_ch: Enable the channels of Master Port.
658 struct sdw_master_port_ops {
659 int (*dpn_set_port_params)(struct sdw_bus *bus,
660 struct sdw_port_params *port_params,
662 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
663 struct sdw_transport_params *transport_params,
664 enum sdw_reg_bank bank);
665 int (*dpn_port_prep)(struct sdw_bus *bus,
666 struct sdw_prepare_ch *prepare_ch);
667 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
668 struct sdw_enable_ch *enable_ch, unsigned int bank);
674 * struct sdw_defer - SDW deffered message
675 * @length: message length
676 * @complete: message completion
681 struct completion complete;
686 * struct sdw_master_ops - Master driver ops
687 * @read_prop: Read Master properties
688 * @xfer_msg: Transfer message callback
689 * @xfer_msg_defer: Defer version of transfer message callback
690 * @reset_page_addr: Reset the SCP page address registers
691 * @set_bus_conf: Set the bus configuration
692 * @pre_bank_switch: Callback for pre bank switch
693 * @post_bank_switch: Callback for post bank switch
695 struct sdw_master_ops {
696 int (*read_prop)(struct sdw_bus *bus);
698 enum sdw_command_response (*xfer_msg)
699 (struct sdw_bus *bus, struct sdw_msg *msg);
700 enum sdw_command_response (*xfer_msg_defer)
701 (struct sdw_bus *bus, struct sdw_msg *msg,
702 struct sdw_defer *defer);
703 enum sdw_command_response (*reset_page_addr)
704 (struct sdw_bus *bus, unsigned int dev_num);
705 int (*set_bus_conf)(struct sdw_bus *bus,
706 struct sdw_bus_params *params);
707 int (*pre_bank_switch)(struct sdw_bus *bus);
708 int (*post_bank_switch)(struct sdw_bus *bus);
713 * struct sdw_bus - SoundWire bus
714 * @dev: Master linux device
715 * @link_id: Link id number, can be 0 to N, unique for each Master
716 * @slaves: list of Slaves on this bus
717 * @assigned: Bitmap for Slave device numbers.
718 * Bit set implies used number, bit clear implies unused number.
719 * @bus_lock: bus lock
720 * @msg_lock: message lock
721 * @ops: Master callback ops
722 * @port_ops: Master port callback ops
723 * @params: Current bus parameters
724 * @prop: Master properties
725 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
726 * is used to compute and program bus bandwidth, clock, frame shape,
727 * transport and port parameters
728 * @defer_msg: Defer message
729 * @clk_stop_timeout: Clock stop timeout computed
730 * @bank_switch_timeout: Bank switch timeout computed
731 * @multi_link: Store bus property that indicates if multi links
732 * are supported. This flag is populated by drivers after reading
733 * appropriate firmware (ACPI/DT).
737 unsigned int link_id;
738 struct list_head slaves;
739 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
740 struct mutex bus_lock;
741 struct mutex msg_lock;
742 const struct sdw_master_ops *ops;
743 const struct sdw_master_port_ops *port_ops;
744 struct sdw_bus_params params;
745 struct sdw_master_prop prop;
746 struct list_head m_rt_list;
747 struct sdw_defer defer_msg;
748 unsigned int clk_stop_timeout;
749 u32 bank_switch_timeout;
753 int sdw_add_bus_master(struct sdw_bus *bus);
754 void sdw_delete_bus_master(struct sdw_bus *bus);
757 * sdw_port_config: Master or Slave Port configuration
760 * @ch_mask: channels mask for port
762 struct sdw_port_config {
764 unsigned int ch_mask;
768 * sdw_stream_config: Master or Slave stream configuration
770 * @frame_rate: Audio frame rate of the stream, in Hz
771 * @ch_count: Channel count of the stream
772 * @bps: Number of bits per audio sample
773 * @direction: Data direction
774 * @type: Stream type PCM or PDM
776 struct sdw_stream_config {
777 unsigned int frame_rate;
778 unsigned int ch_count;
780 enum sdw_data_direction direction;
781 enum sdw_stream_type type;
785 * sdw_stream_state: Stream states
787 * @SDW_STREAM_ALLOCATED: New stream allocated.
788 * @SDW_STREAM_CONFIGURED: Stream configured
789 * @SDW_STREAM_PREPARED: Stream prepared
790 * @SDW_STREAM_ENABLED: Stream enabled
791 * @SDW_STREAM_DISABLED: Stream disabled
792 * @SDW_STREAM_DEPREPARED: Stream de-prepared
793 * @SDW_STREAM_RELEASED: Stream released
795 enum sdw_stream_state {
796 SDW_STREAM_ALLOCATED = 0,
797 SDW_STREAM_CONFIGURED = 1,
798 SDW_STREAM_PREPARED = 2,
799 SDW_STREAM_ENABLED = 3,
800 SDW_STREAM_DISABLED = 4,
801 SDW_STREAM_DEPREPARED = 5,
802 SDW_STREAM_RELEASED = 6,
806 * sdw_stream_params: Stream parameters
808 * @rate: Sampling frequency, in Hz
809 * @ch_count: Number of channels
810 * @bps: bits per channel sample
812 struct sdw_stream_params {
814 unsigned int ch_count;
819 * sdw_stream_runtime: Runtime stream parameters
821 * @name: SoundWire stream name
822 * @params: Stream parameters
823 * @state: Current state of the stream
824 * @type: Stream type PCM or PDM
825 * @master_list: List of Master runtime(s) in this stream.
826 * master_list can contain only one m_rt per Master instance
828 * @m_rt_count: Count of Master runtime(s) in this stream
830 struct sdw_stream_runtime {
832 struct sdw_stream_params params;
833 enum sdw_stream_state state;
834 enum sdw_stream_type type;
835 struct list_head master_list;
839 struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name);
840 void sdw_release_stream(struct sdw_stream_runtime *stream);
841 int sdw_stream_add_master(struct sdw_bus *bus,
842 struct sdw_stream_config *stream_config,
843 struct sdw_port_config *port_config,
844 unsigned int num_ports,
845 struct sdw_stream_runtime *stream);
846 int sdw_stream_add_slave(struct sdw_slave *slave,
847 struct sdw_stream_config *stream_config,
848 struct sdw_port_config *port_config,
849 unsigned int num_ports,
850 struct sdw_stream_runtime *stream);
851 int sdw_stream_remove_master(struct sdw_bus *bus,
852 struct sdw_stream_runtime *stream);
853 int sdw_stream_remove_slave(struct sdw_slave *slave,
854 struct sdw_stream_runtime *stream);
855 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
856 int sdw_enable_stream(struct sdw_stream_runtime *stream);
857 int sdw_disable_stream(struct sdw_stream_runtime *stream);
858 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
860 /* messaging and data APIs */
862 int sdw_read(struct sdw_slave *slave, u32 addr);
863 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
864 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
865 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
867 #endif /* __SOUNDWIRE_H */