1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
8 * Contains standard defines and IDs for NAND flash devices
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
18 #include <dm/device.h>
19 #include <linux/compat.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/flashchip.h>
22 #include <linux/mtd/bbm.h>
23 #include <asm/cache.h>
27 struct nand_flash_dev;
30 /* Get the flash and manufacturer id and lookup if the type is supported. */
31 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
32 struct nand_chip *chip,
33 int *maf_id, int *dev_id,
34 struct nand_flash_dev *type);
36 /* Scan and identify a NAND device */
37 int nand_scan(struct mtd_info *mtd, int max_chips);
39 * Separate phases of nand_scan(), allowing board driver to intervene
40 * and override command or ECC setup according to flash type.
42 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
43 struct nand_flash_dev *table);
44 int nand_scan_tail(struct mtd_info *mtd);
46 /* Free resources held by the NAND device */
47 void nand_release(struct mtd_info *mtd);
49 /* Internal helper for board drivers which need to override command function */
50 void nand_wait_ready(struct mtd_info *mtd);
53 * This constant declares the max. oobsize / page, which
54 * is supported now. If you add a chip with bigger oobsize/page
55 * adjust this accordingly.
57 #define NAND_MAX_OOBSIZE 1664
58 #define NAND_MAX_PAGESIZE 16384
61 * Constants for hardware specific CLE/ALE/NCE function
63 * These are bits which can be or'ed to set/clear multiple
66 /* Select the chip by setting nCE to low */
68 /* Select the command latch by setting CLE to high */
70 /* Select the address latch by setting ALE to high */
73 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
74 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
75 #define NAND_CTRL_CHANGE 0x80
78 * Standard NAND flash commands
80 #define NAND_CMD_READ0 0
81 #define NAND_CMD_READ1 1
82 #define NAND_CMD_RNDOUT 5
83 #define NAND_CMD_PAGEPROG 0x10
84 #define NAND_CMD_READOOB 0x50
85 #define NAND_CMD_ERASE1 0x60
86 #define NAND_CMD_STATUS 0x70
87 #define NAND_CMD_SEQIN 0x80
88 #define NAND_CMD_RNDIN 0x85
89 #define NAND_CMD_READID 0x90
90 #define NAND_CMD_ERASE2 0xd0
91 #define NAND_CMD_PARAM 0xec
92 #define NAND_CMD_GET_FEATURES 0xee
93 #define NAND_CMD_SET_FEATURES 0xef
94 #define NAND_CMD_RESET 0xff
96 #define NAND_CMD_LOCK 0x2a
97 #define NAND_CMD_UNLOCK1 0x23
98 #define NAND_CMD_UNLOCK2 0x24
100 /* Extended commands for large page devices */
101 #define NAND_CMD_READSTART 0x30
102 #define NAND_CMD_RNDOUTSTART 0xE0
103 #define NAND_CMD_CACHEDPROG 0x15
105 /* Extended commands for AG-AND device */
107 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
108 * there is no way to distinguish that from NAND_CMD_READ0
109 * until the remaining sequence of commands has been completed
110 * so add a high order bit and mask it off in the command.
112 #define NAND_CMD_DEPLETE1 0x100
113 #define NAND_CMD_DEPLETE2 0x38
114 #define NAND_CMD_STATUS_MULTI 0x71
115 #define NAND_CMD_STATUS_ERROR 0x72
116 /* multi-bank error status (banks 0-3) */
117 #define NAND_CMD_STATUS_ERROR0 0x73
118 #define NAND_CMD_STATUS_ERROR1 0x74
119 #define NAND_CMD_STATUS_ERROR2 0x75
120 #define NAND_CMD_STATUS_ERROR3 0x76
121 #define NAND_CMD_STATUS_RESET 0x7f
122 #define NAND_CMD_STATUS_CLEAR 0xff
124 #define NAND_CMD_NONE -1
127 #define NAND_STATUS_FAIL 0x01
128 #define NAND_STATUS_FAIL_N1 0x02
129 #define NAND_STATUS_TRUE_READY 0x20
130 #define NAND_STATUS_READY 0x40
131 #define NAND_STATUS_WP 0x80
133 #define NAND_DATA_IFACE_CHECK_ONLY -1
136 * Constants for ECC_MODES
142 NAND_ECC_HW_SYNDROME,
143 NAND_ECC_HW_OOB_FIRST,
154 * Constants for Hardware ECC
156 /* Reset Hardware ECC for read */
157 #define NAND_ECC_READ 0
158 /* Reset Hardware ECC for write */
159 #define NAND_ECC_WRITE 1
160 /* Enable Hardware ECC before syndrome is read back from flash */
161 #define NAND_ECC_READSYN 2
164 * Enable generic NAND 'page erased' check. This check is only done when
165 * ecc.correct() returns -EBADMSG.
166 * Set this flag if your implementation does not fix bitflips in erased
167 * pages and you want to rely on the default implementation.
169 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
170 #define NAND_ECC_MAXIMIZE BIT(1)
172 * If your controller already sends the required NAND commands when
173 * reading or writing a page, then the framework is not supposed to
174 * send READ0 and SEQIN/PAGEPROG respectively.
176 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
178 /* Bit mask for flags passed to do_nand_read_ecc */
179 #define NAND_GET_DEVICE 0x80
183 * Option constants for bizarre disfunctionality and real
186 /* Buswidth is 16 bit */
187 #define NAND_BUSWIDTH_16 0x00000002
188 /* Device supports partial programming without padding */
189 #define NAND_NO_PADDING 0x00000004
190 /* Chip has cache program function */
191 #define NAND_CACHEPRG 0x00000008
192 /* Chip has copy back function */
193 #define NAND_COPYBACK 0x00000010
195 * Chip requires ready check on read (for auto-incremented sequential read).
196 * True only for small page devices; large page devices do not support
199 #define NAND_NEED_READRDY 0x00000100
201 /* Chip does not allow subpage writes */
202 #define NAND_NO_SUBPAGE_WRITE 0x00000200
204 /* Device is one of 'new' xD cards that expose fake nand command set */
205 #define NAND_BROKEN_XD 0x00000400
207 /* Device behaves just like nand, but is readonly */
208 #define NAND_ROM 0x00000800
210 /* Device supports subpage reads */
211 #define NAND_SUBPAGE_READ 0x00001000
214 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
217 #define NAND_NEED_SCRAMBLING 0x00002000
219 /* Device needs 3rd row address cycle */
220 #define NAND_ROW_ADDR_3 0x00004000
222 /* Options valid for Samsung large page devices */
223 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
225 /* Macros to identify the above */
226 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
227 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
228 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
230 /* Non chip related options */
231 /* This option skips the bbt scan during initialization. */
232 #define NAND_SKIP_BBTSCAN 0x00010000
234 * This option is defined if the board driver allocates its own buffers
235 * (e.g. because it needs them DMA-coherent).
237 #define NAND_OWN_BUFFERS 0x00020000
238 /* Chip may not exist, so silence any errors in scan */
239 #define NAND_SCAN_SILENT_NODEV 0x00040000
241 * Autodetect nand buswidth with readid/onfi.
242 * This suppose the driver will configure the hardware in 8 bits mode
243 * when calling nand_scan_ident, and update its configuration
244 * before calling nand_scan_tail.
246 #define NAND_BUSWIDTH_AUTO 0x00080000
248 * This option could be defined by controller drivers to protect against
249 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
251 #define NAND_USE_BOUNCE_BUFFER 0x00100000
253 /* Options set by nand scan */
254 /* bbt has already been read */
255 #define NAND_BBT_SCANNED 0x40000000
256 /* Nand scan has allocated controller struct */
257 #define NAND_CONTROLLER_ALLOC 0x80000000
259 /* Cell info constants */
260 #define NAND_CI_CHIPNR_MSK 0x03
261 #define NAND_CI_CELLTYPE_MSK 0x0C
262 #define NAND_CI_CELLTYPE_SHIFT 2
265 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
266 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
268 /* ONFI timing mode, used in both asynchronous and synchronous mode */
269 #define ONFI_TIMING_MODE_0 (1 << 0)
270 #define ONFI_TIMING_MODE_1 (1 << 1)
271 #define ONFI_TIMING_MODE_2 (1 << 2)
272 #define ONFI_TIMING_MODE_3 (1 << 3)
273 #define ONFI_TIMING_MODE_4 (1 << 4)
274 #define ONFI_TIMING_MODE_5 (1 << 5)
275 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
277 /* ONFI feature address */
278 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
280 /* Vendor-specific feature address (Micron) */
281 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
283 /* ONFI subfeature parameters length */
284 #define ONFI_SUBFEATURE_PARAM_LEN 4
286 /* ONFI optional commands SET/GET FEATURES supported? */
287 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
289 struct nand_onfi_params {
290 /* rev info and features block */
291 /* 'O' 'N' 'F' 'I' */
297 __le16 ext_param_page_length; /* since ONFI 2.1 */
298 u8 num_of_param_pages; /* since ONFI 2.1 */
301 /* manufacturer information block */
302 char manufacturer[12];
308 /* memory organization block */
309 __le32 byte_per_page;
310 __le16 spare_bytes_per_page;
311 __le32 data_bytes_per_ppage;
312 __le16 spare_bytes_per_ppage;
313 __le32 pages_per_block;
314 __le32 blocks_per_lun;
319 __le16 block_endurance;
320 u8 guaranteed_good_blocks;
321 __le16 guaranteed_block_endurance;
322 u8 programs_per_page;
329 /* electrical parameter block */
330 u8 io_pin_capacitance_max;
331 __le16 async_timing_mode;
332 __le16 program_cache_timing_mode;
337 __le16 src_sync_timing_mode;
338 u8 src_ssync_features;
339 __le16 clk_pin_capacitance_typ;
340 __le16 io_pin_capacitance_typ;
341 __le16 input_pin_capacitance_typ;
342 u8 input_pin_capacitance_max;
343 u8 driver_strength_support;
349 __le16 vendor_revision;
355 #define ONFI_CRC_BASE 0x4F4E
357 /* Extended ECC information Block Definition (since ONFI 2.1) */
358 struct onfi_ext_ecc_info {
362 __le16 block_endurance;
366 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
367 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
368 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
369 struct onfi_ext_section {
374 #define ONFI_EXT_SECTION_MAX 8
376 /* Extended Parameter Page Definition (since ONFI 2.1) */
377 struct onfi_ext_param_page {
379 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
381 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
384 * The actual size of the Extended Parameter Page is in
385 * @ext_param_page_length of nand_onfi_params{}.
386 * The following are the variable length sections.
387 * So we do not add any fields below. Please see the ONFI spec.
391 struct nand_onfi_vendor_micron {
396 u8 dq_imped_num_settings;
397 u8 dq_imped_feat_addr;
398 u8 rb_pulldown_strength;
399 u8 rb_pulldown_strength_feat_addr;
400 u8 rb_pulldown_strength_num_settings;
403 u8 otp_data_prot_addr;
406 u8 read_retry_options;
411 struct jedec_ecc_info {
415 __le16 block_endurance;
420 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
422 struct nand_jedec_params {
423 /* rev info and features block */
424 /* 'J' 'E' 'S' 'D' */
430 u8 num_of_param_pages;
433 /* manufacturer information block */
434 char manufacturer[12];
439 /* memory organization block */
440 __le32 byte_per_page;
441 __le16 spare_bytes_per_page;
443 __le32 pages_per_block;
444 __le32 blocks_per_lun;
448 u8 programs_per_page;
450 u8 multi_plane_op_attr;
453 /* electrical parameter block */
454 __le16 async_sdr_speed_grade;
455 __le16 toggle_ddr_speed_grade;
456 __le16 sync_ddr_speed_grade;
457 u8 async_sdr_features;
458 u8 toggle_ddr_features;
459 u8 sync_ddr_features;
463 __le16 t_r_multi_plane;
465 __le16 io_pin_capacitance_typ;
466 __le16 input_pin_capacitance_typ;
467 __le16 clk_pin_capacitance_typ;
468 u8 driver_strength_support;
472 /* ECC and endurance block */
473 u8 guaranteed_good_blocks;
474 __le16 guaranteed_block_endurance;
475 struct jedec_ecc_info ecc_info[4];
482 __le16 vendor_rev_num;
485 /* CRC for Parameter Page */
490 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
491 * @lock: protection lock
492 * @active: the mtd device which holds the controller currently
493 * @wq: wait queue to sleep on if a NAND operation is in
494 * progress used instead of the per chip wait queue
495 * when a hw controller is available.
497 struct nand_hw_control {
499 struct nand_chip *active;
503 * struct nand_ecc_step_info - ECC step information of ECC engine
504 * @stepsize: data bytes per ECC step
505 * @strengths: array of supported strengths
506 * @nstrengths: number of supported strengths
508 struct nand_ecc_step_info {
510 const int *strengths;
515 * struct nand_ecc_caps - capability of ECC engine
516 * @stepinfos: array of ECC step information
517 * @nstepinfos: number of ECC step information
518 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
520 struct nand_ecc_caps {
521 const struct nand_ecc_step_info *stepinfos;
523 int (*calc_ecc_bytes)(int step_size, int strength);
526 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
527 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
528 static const int __name##_strengths[] = { __VA_ARGS__ }; \
529 static const struct nand_ecc_step_info __name##_stepinfo = { \
530 .stepsize = __step, \
531 .strengths = __name##_strengths, \
532 .nstrengths = ARRAY_SIZE(__name##_strengths), \
534 static const struct nand_ecc_caps __name = { \
535 .stepinfos = &__name##_stepinfo, \
537 .calc_ecc_bytes = __calc, \
541 * struct nand_ecc_ctrl - Control structure for ECC
543 * @algo: ECC algorithm
544 * @steps: number of ECC steps per page
545 * @size: data bytes per ECC step
546 * @bytes: ECC bytes per step
547 * @strength: max number of correctible bits per ECC step
548 * @total: total number of ECC bytes per page
549 * @prepad: padding information for syndrome based ECC generators
550 * @postpad: padding information for syndrome based ECC generators
551 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
552 * @layout: ECC layout control struct pointer
553 * @priv: pointer to private ECC control data
554 * @hwctl: function to control hardware ECC generator. Must only
555 * be provided if an hardware ECC is available
556 * @calculate: function for ECC calculation or readback from ECC hardware
557 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
558 * Should return a positive number representing the number of
559 * corrected bitflips, -EBADMSG if the number of bitflips exceed
560 * ECC strength, or any other error code if the error is not
561 * directly related to correction.
562 * If -EBADMSG is returned the input buffers should be left
564 * @read_page_raw: function to read a raw page without ECC. This function
565 * should hide the specific layout used by the ECC
566 * controller and always return contiguous in-band and
567 * out-of-band data even if they're not stored
568 * contiguously on the NAND chip (e.g.
569 * NAND_ECC_HW_SYNDROME interleaves in-band and
571 * @write_page_raw: function to write a raw page without ECC. This function
572 * should hide the specific layout used by the ECC
573 * controller and consider the passed data as contiguous
574 * in-band and out-of-band data. ECC controller is
575 * responsible for doing the appropriate transformations
576 * to adapt to its specific layout (e.g.
577 * NAND_ECC_HW_SYNDROME interleaves in-band and
579 * @read_page: function to read a page according to the ECC generator
580 * requirements; returns maximum number of bitflips corrected in
581 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
582 * @read_subpage: function to read parts of the page covered by ECC;
583 * returns same as read_page()
584 * @write_subpage: function to write parts of the page covered by ECC.
585 * @write_page: function to write a page according to the ECC generator
587 * @write_oob_raw: function to write chip OOB data without ECC
588 * @read_oob_raw: function to read chip OOB data without ECC
589 * @read_oob: function to read chip OOB data
590 * @write_oob: function to write chip OOB data
592 struct nand_ecc_ctrl {
593 nand_ecc_modes_t mode;
594 enum nand_ecc_algo algo;
602 unsigned int options;
603 struct nand_ecclayout *layout;
605 void (*hwctl)(struct mtd_info *mtd, int mode);
606 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
608 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
610 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
611 uint8_t *buf, int oob_required, int page);
612 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
613 const uint8_t *buf, int oob_required, int page);
614 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
615 uint8_t *buf, int oob_required, int page);
616 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
617 uint32_t offs, uint32_t len, uint8_t *buf, int page);
618 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
619 uint32_t offset, uint32_t data_len,
620 const uint8_t *data_buf, int oob_required, int page);
621 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
622 const uint8_t *buf, int oob_required, int page);
623 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
625 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
627 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
628 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
632 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
634 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
638 * struct nand_buffers - buffer structure for read/write
639 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
640 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
641 * @databuf: buffer pointer for data, size is (page size + oobsize).
643 * Do not change the order of buffers. databuf and oobrbuf must be in
646 struct nand_buffers {
647 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
648 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
649 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
654 * struct nand_sdr_timings - SDR NAND chip timings
656 * This struct defines the timing requirements of a SDR NAND chip.
657 * These information can be found in every NAND datasheets and the timings
658 * meaning are described in the ONFI specifications:
659 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
662 * All these timings are expressed in picoseconds.
664 * @tBERS_max: Block erase time
665 * @tCCS_min: Change column setup time
666 * @tPROG_max: Page program time
667 * @tR_max: Page read time
668 * @tALH_min: ALE hold time
669 * @tADL_min: ALE to data loading time
670 * @tALS_min: ALE setup time
671 * @tAR_min: ALE to RE# delay
672 * @tCEA_max: CE# access time
673 * @tCEH_min: CE# high hold time
674 * @tCH_min: CE# hold time
675 * @tCHZ_max: CE# high to output hi-Z
676 * @tCLH_min: CLE hold time
677 * @tCLR_min: CLE to RE# delay
678 * @tCLS_min: CLE setup time
679 * @tCOH_min: CE# high to output hold
680 * @tCS_min: CE# setup time
681 * @tDH_min: Data hold time
682 * @tDS_min: Data setup time
683 * @tFEAT_max: Busy time for Set Features and Get Features
684 * @tIR_min: Output hi-Z to RE# low
685 * @tITC_max: Interface and Timing Mode Change time
686 * @tRC_min: RE# cycle time
687 * @tREA_max: RE# access time
688 * @tREH_min: RE# high hold time
689 * @tRHOH_min: RE# high to output hold
690 * @tRHW_min: RE# high to WE# low
691 * @tRHZ_max: RE# high to output hi-Z
692 * @tRLOH_min: RE# low to output hold
693 * @tRP_min: RE# pulse width
694 * @tRR_min: Ready to RE# low (data only)
695 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
696 * rising edge of R/B#.
697 * @tWB_max: WE# high to SR[6] low
698 * @tWC_min: WE# cycle time
699 * @tWH_min: WE# high hold time
700 * @tWHR_min: WE# high to RE# low
701 * @tWP_min: WE# pulse width
702 * @tWW_min: WP# transition to WE# low
704 struct nand_sdr_timings {
746 * enum nand_data_interface_type - NAND interface timing type
747 * @NAND_SDR_IFACE: Single Data Rate interface
749 enum nand_data_interface_type {
754 * struct nand_data_interface - NAND interface timing
755 * @type: type of the timing
756 * @timings: The timing, type according to @type
758 struct nand_data_interface {
759 enum nand_data_interface_type type;
761 struct nand_sdr_timings sdr;
766 * nand_get_sdr_timings - get SDR timing from data interface
767 * @conf: The data interface
769 static inline const struct nand_sdr_timings *
770 nand_get_sdr_timings(const struct nand_data_interface *conf)
772 if (conf->type != NAND_SDR_IFACE)
773 return ERR_PTR(-EINVAL);
775 return &conf->timings.sdr;
779 * struct nand_chip - NAND Private Flash Chip Data
780 * @mtd: MTD device registered to the MTD framework
781 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
783 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
785 * @flash_node: [BOARDSPECIFIC] device node describing this instance
786 * @read_byte: [REPLACEABLE] read one byte from the chip
787 * @read_word: [REPLACEABLE] read one word from the chip
788 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
790 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
791 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
792 * @select_chip: [REPLACEABLE] select chip nr
793 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
794 * @block_markbad: [REPLACEABLE] mark a block bad
795 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
796 * ALE/CLE/nCE. Also used to write command and address
797 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
798 * device ready/busy line. If set to NULL no access to
799 * ready/busy is available and the ready/busy information
800 * is read from the chip status register.
801 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
802 * commands to the chip.
803 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
805 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
806 * setting the read-retry mode. Mostly needed for MLC NAND.
807 * @ecc: [BOARDSPECIFIC] ECC control structure
808 * @buffers: buffer structure for read/write
809 * @buf_align: minimum buffer alignment required by a platform
810 * @hwcontrol: platform-specific hardware control structure
811 * @erase: [REPLACEABLE] erase function
812 * @scan_bbt: [REPLACEABLE] function to scan bad block table
813 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
814 * data from array to read regs (tR).
815 * @state: [INTERN] the current state of the NAND device
816 * @oob_poi: "poison value buffer," used for laying out OOB data
818 * @page_shift: [INTERN] number of address bits in a page (column
820 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
821 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
822 * @chip_shift: [INTERN] number of address bits in one chip
823 * @options: [BOARDSPECIFIC] various chip options. They can partly
824 * be set to inform nand_scan about special functionality.
825 * See the defines for further explanation.
826 * @bbt_options: [INTERN] bad block specific options. All options used
827 * here must come from bbm.h. By default, these options
828 * will be copied to the appropriate nand_bbt_descr's.
829 * @badblockpos: [INTERN] position of the bad block marker in the oob
831 * @badblockbits: [INTERN] minimum number of set bits in a good block's
832 * bad block marker position; i.e., BBM == 11110111b is
833 * not bad when badblockbits == 7
834 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
835 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
836 * Minimum amount of bit errors per @ecc_step_ds guaranteed
837 * to be correctable. If unknown, set to zero.
838 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
839 * also from the datasheet. It is the recommended ECC step
840 * size, if known; if unknown, set to zero.
841 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
842 * set to the actually used ONFI mode if the chip is
843 * ONFI compliant or deduced from the datasheet if
844 * the NAND chip is not ONFI compliant.
845 * @numchips: [INTERN] number of physical chips
846 * @chipsize: [INTERN] the size of one chip for multichip arrays
847 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
848 * @pagebuf: [INTERN] holds the pagenumber which is currently in
850 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
851 * currently in data_buf.
852 * @subpagesize: [INTERN] holds the subpagesize
853 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
854 * non 0 if ONFI supported.
855 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
856 * non 0 if JEDEC supported.
857 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
858 * supported, 0 otherwise.
859 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
860 * supported, 0 otherwise.
861 * @read_retries: [INTERN] the number of read retry modes supported
862 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
863 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
864 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
865 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
866 * means the configuration should not be applied but
868 * @bbt: [INTERN] bad block table pointer
869 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
871 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
872 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
874 * @controller: [REPLACEABLE] a pointer to a hardware controller
875 * structure which is shared among multiple independent
877 * @priv: [OPTIONAL] pointer to private chip data
878 * @write_page: [REPLACEABLE] High-level page write function
883 void __iomem *IO_ADDR_R;
884 void __iomem *IO_ADDR_W;
888 uint8_t (*read_byte)(struct mtd_info *mtd);
889 u16 (*read_word)(struct mtd_info *mtd);
890 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
891 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
892 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
893 void (*select_chip)(struct mtd_info *mtd, int chip);
894 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
895 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
896 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
897 int (*dev_ready)(struct mtd_info *mtd);
898 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
900 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
901 int (*erase)(struct mtd_info *mtd, int page);
902 int (*scan_bbt)(struct mtd_info *mtd);
903 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
904 uint32_t offset, int data_len, const uint8_t *buf,
905 int oob_required, int page, int raw);
906 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
907 int feature_addr, uint8_t *subfeature_para);
908 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
909 int feature_addr, uint8_t *subfeature_para);
910 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
911 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
912 const struct nand_data_interface *conf);
916 unsigned int options;
917 unsigned int bbt_options;
920 int phys_erase_shift;
927 unsigned int pagebuf_bitflips;
929 uint8_t bits_per_cell;
930 uint16_t ecc_strength_ds;
931 uint16_t ecc_step_ds;
932 int onfi_timing_mode_default;
938 struct nand_onfi_params onfi_params;
939 struct nand_jedec_params jedec_params;
941 struct nand_data_interface *data_interface;
948 struct nand_hw_control *controller;
949 struct nand_ecclayout *ecclayout;
951 struct nand_ecc_ctrl ecc;
952 struct nand_buffers *buffers;
953 unsigned long buf_align;
954 struct nand_hw_control hwcontrol;
957 struct nand_bbt_descr *bbt_td;
958 struct nand_bbt_descr *bbt_md;
960 struct nand_bbt_descr *badblock_pattern;
965 static inline void nand_set_flash_node(struct nand_chip *chip,
968 chip->flash_node = ofnode_to_offset(node);
971 static inline ofnode nand_get_flash_node(struct nand_chip *chip)
973 return offset_to_ofnode(chip->flash_node);
976 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
978 return container_of(mtd, struct nand_chip, mtd);
981 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
986 static inline void *nand_get_controller_data(struct nand_chip *chip)
991 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
997 * NAND Flash Manufacturer ID Codes
999 #define NAND_MFR_TOSHIBA 0x98
1000 #define NAND_MFR_SAMSUNG 0xec
1001 #define NAND_MFR_FUJITSU 0x04
1002 #define NAND_MFR_NATIONAL 0x8f
1003 #define NAND_MFR_RENESAS 0x07
1004 #define NAND_MFR_STMICRO 0x20
1005 #define NAND_MFR_HYNIX 0xad
1006 #define NAND_MFR_MICRON 0x2c
1007 #define NAND_MFR_AMD 0x01
1008 #define NAND_MFR_MACRONIX 0xc2
1009 #define NAND_MFR_EON 0x92
1010 #define NAND_MFR_SANDISK 0x45
1011 #define NAND_MFR_INTEL 0x89
1012 #define NAND_MFR_ATO 0x9b
1014 /* The maximum expected count of bytes in the NAND ID sequence */
1015 #define NAND_MAX_ID_LEN 8
1018 * A helper for defining older NAND chips where the second ID byte fully
1019 * defined the chip, including the geometry (chip size, eraseblock size, page
1020 * size). All these chips have 512 bytes NAND page size.
1022 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1023 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1024 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1027 * A helper for defining newer chips which report their page size and
1028 * eraseblock size via the extended ID bytes.
1030 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1031 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1032 * device ID now only represented a particular total chip size (and voltage,
1033 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1034 * using the same device ID.
1036 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1037 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1040 #define NAND_ECC_INFO(_strength, _step) \
1041 { .strength_ds = (_strength), .step_ds = (_step) }
1042 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1043 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1046 * struct nand_flash_dev - NAND Flash Device ID Structure
1047 * @name: a human-readable name of the NAND chip
1048 * @dev_id: the device ID (the second byte of the full chip ID array)
1049 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1050 * memory address as @id[0])
1051 * @dev_id: device ID part of the full chip ID array (refers the same memory
1052 * address as @id[1])
1053 * @id: full device ID array
1054 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1055 * well as the eraseblock size) is determined from the extended NAND
1057 * @chipsize: total chip size in MiB
1058 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1059 * @options: stores various chip bit options
1060 * @id_len: The valid length of the @id.
1061 * @oobsize: OOB size
1062 * @ecc: ECC correctability and step information from the datasheet.
1063 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1064 * @ecc_strength_ds in nand_chip{}.
1065 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1066 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1067 * For example, the "4bit ECC for each 512Byte" can be set with
1068 * NAND_ECC_INFO(4, 512).
1069 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1070 * reset. Should be deduced from timings described
1074 struct nand_flash_dev {
1081 uint8_t id[NAND_MAX_ID_LEN];
1083 unsigned int pagesize;
1084 unsigned int chipsize;
1085 unsigned int erasesize;
1086 unsigned int options;
1090 uint16_t strength_ds;
1093 int onfi_timing_mode_default;
1097 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1098 * @name: Manufacturer name
1099 * @id: manufacturer ID code of device.
1101 struct nand_manufacturers {
1106 extern struct nand_flash_dev nand_flash_ids[];
1107 extern struct nand_manufacturers nand_manuf_ids[];
1109 int nand_default_bbt(struct mtd_info *mtd);
1110 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1111 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1112 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1113 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1115 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1116 size_t *retlen, uint8_t *buf);
1119 * Constants for oob configuration
1121 #define NAND_SMALL_BADBLOCK_POS 5
1122 #define NAND_LARGE_BADBLOCK_POS 0
1125 * struct platform_nand_chip - chip level device structure
1126 * @nr_chips: max. number of chips to scan for
1127 * @chip_offset: chip number offset
1128 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1129 * @partitions: mtd partition list
1130 * @chip_delay: R/B delay value in us
1131 * @options: Option flags, e.g. 16bit buswidth
1132 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1133 * @part_probe_types: NULL-terminated array of probe types
1135 struct platform_nand_chip {
1139 struct mtd_partition *partitions;
1141 unsigned int options;
1142 unsigned int bbt_options;
1143 const char **part_probe_types;
1146 /* Keep gcc happy */
1147 struct platform_device;
1150 * struct platform_nand_ctrl - controller level device structure
1151 * @probe: platform specific function to probe/setup hardware
1152 * @remove: platform specific function to remove/teardown hardware
1153 * @hwcontrol: platform specific hardware control structure
1154 * @dev_ready: platform specific function to read ready/busy pin
1155 * @select_chip: platform specific chip select function
1156 * @cmd_ctrl: platform specific function for controlling
1157 * ALE/CLE/nCE. Also used to write command and address
1158 * @write_buf: platform specific function for write buffer
1159 * @read_buf: platform specific function for read buffer
1160 * @read_byte: platform specific function to read one byte from chip
1161 * @priv: private data to transport driver specific settings
1163 * All fields are optional and depend on the hardware driver requirements
1165 struct platform_nand_ctrl {
1166 int (*probe)(struct platform_device *pdev);
1167 void (*remove)(struct platform_device *pdev);
1168 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1169 int (*dev_ready)(struct mtd_info *mtd);
1170 void (*select_chip)(struct mtd_info *mtd, int chip);
1171 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1172 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1173 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1174 unsigned char (*read_byte)(struct mtd_info *mtd);
1179 * struct platform_nand_data - container structure for platform-specific data
1180 * @chip: chip level chip structure
1181 * @ctrl: controller level device structure
1183 struct platform_nand_data {
1184 struct platform_nand_chip chip;
1185 struct platform_nand_ctrl ctrl;
1188 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1189 /* return the supported features. */
1190 static inline int onfi_feature(struct nand_chip *chip)
1192 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1195 /* return the supported asynchronous timing mode. */
1196 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1198 if (!chip->onfi_version)
1199 return ONFI_TIMING_MODE_UNKNOWN;
1200 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1203 /* return the supported synchronous timing mode. */
1204 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1206 if (!chip->onfi_version)
1207 return ONFI_TIMING_MODE_UNKNOWN;
1208 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1211 static inline int onfi_feature(struct nand_chip *chip)
1216 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1218 return ONFI_TIMING_MODE_UNKNOWN;
1221 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1223 return ONFI_TIMING_MODE_UNKNOWN;
1227 int onfi_init_data_interface(struct nand_chip *chip,
1228 struct nand_data_interface *iface,
1229 enum nand_data_interface_type type,
1233 * Check if it is a SLC nand.
1234 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1235 * We do not distinguish the MLC and TLC now.
1237 static inline bool nand_is_slc(struct nand_chip *chip)
1239 return chip->bits_per_cell == 1;
1243 * Check if the opcode's address should be sent only on the lower 8 bits
1244 * @command: opcode to check
1246 static inline int nand_opcode_8bits(unsigned int command)
1249 case NAND_CMD_READID:
1250 case NAND_CMD_PARAM:
1251 case NAND_CMD_GET_FEATURES:
1252 case NAND_CMD_SET_FEATURES:
1260 /* return the supported JEDEC features. */
1261 static inline int jedec_feature(struct nand_chip *chip)
1263 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1267 /* Standard NAND functions from nand_base.c */
1268 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1269 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1270 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1271 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1272 uint8_t nand_read_byte(struct mtd_info *mtd);
1274 /* get timing characteristics from ONFI timing mode. */
1275 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1276 /* get data interface from ONFI timing mode 0, used after reset. */
1277 const struct nand_data_interface *nand_get_default_data_interface(void);
1279 int nand_check_erased_ecc_chunk(void *data, int datalen,
1280 void *ecc, int ecclen,
1281 void *extraoob, int extraooblen,
1284 int nand_check_ecc_caps(struct nand_chip *chip,
1285 const struct nand_ecc_caps *caps, int oobavail);
1287 int nand_match_ecc_req(struct nand_chip *chip,
1288 const struct nand_ecc_caps *caps, int oobavail);
1290 int nand_maximize_ecc(struct nand_chip *chip,
1291 const struct nand_ecc_caps *caps, int oobavail);
1293 /* Reset and initialize a NAND device */
1294 int nand_reset(struct nand_chip *chip, int chipnr);
1295 #endif /* __LINUX_MTD_RAWNAND_H */