2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
25 #include <linux/wait.h>
26 #include <linux/spinlock.h>
27 #include <linux/mtd/mtd.h>
32 #include "linux/mtd/compat.h"
33 #include "linux/mtd/mtd.h"
37 /* Scan and identify a NAND device */
38 extern int nand_scan (struct mtd_info *mtd, int max_chips);
39 /* Separate phases of nand_scan(), allowing board driver to intervene
40 * and override command or ECC setup according to flash type */
41 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
42 extern int nand_scan_tail(struct mtd_info *mtd);
44 /* Free resources held by the NAND device */
45 extern void nand_release (struct mtd_info *mtd);
47 /* Internal helper for board drivers which need to override command function */
48 extern void nand_wait_ready(struct mtd_info *mtd);
50 /* The maximum number of NAND chips in an array */
51 #ifndef NAND_MAX_CHIPS
52 #define NAND_MAX_CHIPS 8
55 /* This constant declares the max. oobsize / page, which
56 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
59 #define NAND_MAX_OOBSIZE 128
60 #define NAND_MAX_PAGESIZE 4096
63 * Constants for hardware specific CLE/ALE/NCE function
65 * These are bits which can be or'ed to set/clear multiple
68 /* Select the chip by setting nCE to low */
70 /* Select the command latch by setting CLE to high */
72 /* Select the address latch by setting ALE to high */
75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77 #define NAND_CTRL_CHANGE 0x80
80 * Standard NAND flash commands
82 #define NAND_CMD_READ0 0
83 #define NAND_CMD_READ1 1
84 #define NAND_CMD_RNDOUT 5
85 #define NAND_CMD_PAGEPROG 0x10
86 #define NAND_CMD_READOOB 0x50
87 #define NAND_CMD_ERASE1 0x60
88 #define NAND_CMD_STATUS 0x70
89 #define NAND_CMD_STATUS_MULTI 0x71
90 #define NAND_CMD_SEQIN 0x80
91 #define NAND_CMD_RNDIN 0x85
92 #define NAND_CMD_READID 0x90
93 #define NAND_CMD_ERASE2 0xd0
94 #define NAND_CMD_RESET 0xff
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 /* Extended commands for AG-AND device */
103 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
104 * there is no way to distinguish that from NAND_CMD_READ0
105 * until the remaining sequence of commands has been completed
106 * so add a high order bit and mask it off in the command.
108 #define NAND_CMD_DEPLETE1 0x100
109 #define NAND_CMD_DEPLETE2 0x38
110 #define NAND_CMD_STATUS_MULTI 0x71
111 #define NAND_CMD_STATUS_ERROR 0x72
112 /* multi-bank error status (banks 0-3) */
113 #define NAND_CMD_STATUS_ERROR0 0x73
114 #define NAND_CMD_STATUS_ERROR1 0x74
115 #define NAND_CMD_STATUS_ERROR2 0x75
116 #define NAND_CMD_STATUS_ERROR3 0x76
117 #define NAND_CMD_STATUS_RESET 0x7f
118 #define NAND_CMD_STATUS_CLEAR 0xff
120 #define NAND_CMD_NONE -1
123 #define NAND_STATUS_FAIL 0x01
124 #define NAND_STATUS_FAIL_N1 0x02
125 #define NAND_STATUS_TRUE_READY 0x20
126 #define NAND_STATUS_READY 0x40
127 #define NAND_STATUS_WP 0x80
130 * Constants for ECC_MODES
136 NAND_ECC_HW_SYNDROME,
140 * Constants for Hardware ECC
142 /* Reset Hardware ECC for read */
143 #define NAND_ECC_READ 0
144 /* Reset Hardware ECC for write */
145 #define NAND_ECC_WRITE 1
146 /* Enable Hardware ECC before syndrom is read back from flash */
147 #define NAND_ECC_READSYN 2
149 /* Bit mask for flags passed to do_nand_read_ecc */
150 #define NAND_GET_DEVICE 0x80
153 /* Option constants for bizarre disfunctionality and real
156 /* Chip can not auto increment pages */
157 #define NAND_NO_AUTOINCR 0x00000001
158 /* Buswitdh is 16 bit */
159 #define NAND_BUSWIDTH_16 0x00000002
160 /* Device supports partial programming without padding */
161 #define NAND_NO_PADDING 0x00000004
162 /* Chip has cache program function */
163 #define NAND_CACHEPRG 0x00000008
164 /* Chip has copy back function */
165 #define NAND_COPYBACK 0x00000010
166 /* AND Chip which has 4 banks and a confusing page / block
167 * assignment. See Renesas datasheet for further information */
168 #define NAND_IS_AND 0x00000020
169 /* Chip has a array of 4 pages which can be read without
170 * additional ready /busy waits */
171 #define NAND_4PAGE_ARRAY 0x00000040
172 /* Chip requires that BBT is periodically rewritten to prevent
173 * bits from adjacent blocks from 'leaking' in altering data.
174 * This happens with the Renesas AG-AND chips, possibly others. */
175 #define BBT_AUTO_REFRESH 0x00000080
176 /* Chip does not require ready check on read. True
177 * for all large page devices, as they do not support
179 #define NAND_NO_READRDY 0x00000100
180 /* Chip does not allow subpage writes */
181 #define NAND_NO_SUBPAGE_WRITE 0x00000200
184 /* Options valid for Samsung large page devices */
185 #define NAND_SAMSUNG_LP_OPTIONS \
186 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
188 /* Macros to identify the above */
189 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
190 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
191 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
192 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
194 /* Mask to zero out the chip options, which come from the id table */
195 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
197 /* Non chip related options */
198 /* Use a flash based bad block table. This option is passed to the
199 * default bad block table function. */
200 #define NAND_USE_FLASH_BBT 0x00010000
201 /* This option skips the bbt scan during initialization. */
202 #define NAND_SKIP_BBTSCAN 0x00020000
203 /* This option is defined if the board driver allocates its own buffers
204 (e.g. because it needs them DMA-coherent */
205 #define NAND_OWN_BUFFERS 0x00040000
206 /* Options set by nand scan */
207 /* Nand scan has allocated controller struct */
208 #define NAND_CONTROLLER_ALLOC 0x80000000
210 /* Cell info constants */
211 #define NAND_CI_CHIPNR_MSK 0x03
212 #define NAND_CI_CELLTYPE_MSK 0x0C
215 * nand_state_t - chip states
216 * Enumeration for NAND flash chip state
232 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
233 * @lock: protection lock
234 * @active: the mtd device which holds the controller currently
235 * @wq: wait queue to sleep on if a NAND operation is in progress
236 * used instead of the per chip wait queue when a hw controller is available
238 struct nand_hw_control {
241 wait_queue_head_t wq;
243 struct nand_chip *active;
247 * struct nand_ecc_ctrl - Control structure for ecc
249 * @steps: number of ecc steps per page
250 * @size: data bytes per ecc step
251 * @bytes: ecc bytes per step
252 * @total: total number of ecc bytes per page
253 * @prepad: padding information for syndrome based ecc generators
254 * @postpad: padding information for syndrome based ecc generators
255 * @layout: ECC layout control struct pointer
256 * @hwctl: function to control hardware ecc generator. Must only
257 * be provided if an hardware ECC is available
258 * @calculate: function for ecc calculation or readback from ecc hardware
259 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
260 * @read_page_raw: function to read a raw page without ECC
261 * @write_page_raw: function to write a raw page without ECC
262 * @read_page: function to read a page according to the ecc generator requirements
263 * @write_page: function to write a page according to the ecc generator requirements
264 * @read_oob: function to read chip OOB data
265 * @write_oob: function to write chip OOB data
267 struct nand_ecc_ctrl {
268 nand_ecc_modes_t mode;
275 struct nand_ecclayout *layout;
276 void (*hwctl)(struct mtd_info *mtd, int mode);
277 int (*calculate)(struct mtd_info *mtd,
280 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
283 int (*read_page_raw)(struct mtd_info *mtd,
284 struct nand_chip *chip,
286 void (*write_page_raw)(struct mtd_info *mtd,
287 struct nand_chip *chip,
289 int (*read_page)(struct mtd_info *mtd,
290 struct nand_chip *chip,
292 void (*write_page)(struct mtd_info *mtd,
293 struct nand_chip *chip,
295 int (*read_oob)(struct mtd_info *mtd,
296 struct nand_chip *chip,
299 int (*write_oob)(struct mtd_info *mtd,
300 struct nand_chip *chip,
305 * struct nand_buffers - buffer structure for read/write
306 * @ecccalc: buffer for calculated ecc
307 * @ecccode: buffer for ecc read from flash
308 * @databuf: buffer for data - dynamically sized
310 * Do not change the order of buffers. databuf and oobrbuf must be in
313 struct nand_buffers {
314 uint8_t ecccalc[NAND_MAX_OOBSIZE];
315 uint8_t ecccode[NAND_MAX_OOBSIZE];
316 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
320 * struct nand_chip - NAND Private Flash Chip Data
321 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
322 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
323 * @read_byte: [REPLACEABLE] read one byte from the chip
324 * @read_word: [REPLACEABLE] read one word from the chip
325 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
326 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
327 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
328 * @select_chip: [REPLACEABLE] select chip nr
329 * @block_bad: [REPLACEABLE] check, if the block is bad
330 * @block_markbad: [REPLACEABLE] mark the block bad
331 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
332 * ALE/CLE/nCE. Also used to write command and address
333 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
334 * If set to NULL no access to ready/busy is available and the ready/busy information
335 * is read from the chip status register
336 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
337 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
338 * @ecc: [BOARDSPECIFIC] ecc control ctructure
339 * @buffers: buffer structure for read/write
340 * @hwcontrol: platform-specific hardware control structure
341 * @ops: oob operation operands
342 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
343 * @scan_bbt: [REPLACEABLE] function to scan bad block table
344 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
345 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
346 * @state: [INTERN] the current state of the NAND device
347 * @oob_poi: poison value buffer
348 * @page_shift: [INTERN] number of address bits in a page (column address bits)
349 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
350 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
351 * @chip_shift: [INTERN] number of address bits in one chip
352 * @datbuf: [INTERN] internal buffer for one page + oob
353 * @oobbuf: [INTERN] oob buffer for one eraseblock
354 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
355 * @data_poi: [INTERN] pointer to a data buffer
356 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
357 * special functionality. See the defines for further explanation
358 * @badblockpos: [INTERN] position of the bad block marker in the oob area
359 * @cellinfo: [INTERN] MLC/multichip data from chip ident
360 * @numchips: [INTERN] number of physical chips
361 * @chipsize: [INTERN] the size of one chip for multichip arrays
362 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
363 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
364 * @subpagesize: [INTERN] holds the subpagesize
365 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
366 * @bbt: [INTERN] bad block table pointer
367 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
368 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
369 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
370 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
371 * which is shared among multiple independend devices
372 * @priv: [OPTIONAL] pointer to private chip date
373 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
374 * (determine if errors are correctable)
375 * @write_page: [REPLACEABLE] High-level page write function
379 void __iomem *IO_ADDR_R;
380 void __iomem *IO_ADDR_W;
382 uint8_t (*read_byte)(struct mtd_info *mtd);
383 u16 (*read_word)(struct mtd_info *mtd);
384 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
385 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
386 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
387 void (*select_chip)(struct mtd_info *mtd, int chip);
388 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
389 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
390 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
392 int (*dev_ready)(struct mtd_info *mtd);
393 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
394 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
395 void (*erase_cmd)(struct mtd_info *mtd, int page);
396 int (*scan_bbt)(struct mtd_info *mtd);
397 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
398 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
399 const uint8_t *buf, int page, int cached, int raw);
402 unsigned int options;
405 int phys_erase_shift;
409 unsigned long chipsize;
419 struct nand_hw_control *controller;
420 struct nand_ecclayout *ecclayout;
422 struct nand_ecc_ctrl ecc;
423 struct nand_buffers *buffers;
425 struct nand_hw_control hwcontrol;
427 struct mtd_oob_ops ops;
430 struct nand_bbt_descr *bbt_td;
431 struct nand_bbt_descr *bbt_md;
433 struct nand_bbt_descr *badblock_pattern;
439 * NAND Flash Manufacturer ID Codes
441 #define NAND_MFR_TOSHIBA 0x98
442 #define NAND_MFR_SAMSUNG 0xec
443 #define NAND_MFR_FUJITSU 0x04
444 #define NAND_MFR_NATIONAL 0x8f
445 #define NAND_MFR_RENESAS 0x07
446 #define NAND_MFR_STMICRO 0x20
447 #define NAND_MFR_HYNIX 0xad
448 #define NAND_MFR_MICRON 0x2c
451 * struct nand_flash_dev - NAND Flash Device ID Structure
452 * @name: Identify the device type
453 * @id: device ID code
454 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
455 * If the pagesize is 0, then the real pagesize
456 * and the eraseize are determined from the
457 * extended id bytes in the chip
458 * @erasesize: Size of an erase block in the flash device.
459 * @chipsize: Total chipsize in Mega Bytes
460 * @options: Bitfield to store chip relevant options
462 struct nand_flash_dev {
465 unsigned long pagesize;
466 unsigned long chipsize;
467 unsigned long erasesize;
468 unsigned long options;
472 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
473 * @name: Manufacturer name
474 * @id: manufacturer ID code of device.
476 struct nand_manufacturers {
481 extern struct nand_flash_dev nand_flash_ids[];
482 extern struct nand_manufacturers nand_manuf_ids[];
484 #ifndef NAND_MAX_CHIPS
485 #define NAND_MAX_CHIPS 8
489 * struct nand_bbt_descr - bad block table descriptor
490 * @options: options for this descriptor
491 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
492 * when bbt is searched, then we store the found bbts pages here.
493 * Its an array and supports up to 8 chips now
494 * @offs: offset of the pattern in the oob area of the page
495 * @veroffs: offset of the bbt version counter in the oob are of the page
496 * @version: version read from the bbt page during scan
497 * @len: length of the pattern, if 0 no pattern check is performed
498 * @maxblocks: maximum number of blocks to search for a bbt. This number of
499 * blocks is reserved at the end of the device where the tables are
501 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
502 * bad) block in the stored bbt
503 * @pattern: pattern to identify bad block table or factory marked good /
504 * bad blocks, can be NULL, if len = 0
506 * Descriptor for the bad block table marker and the descriptor for the
507 * pattern which identifies good and bad blocks. The assumption is made
508 * that the pattern and the version count are always located in the oob area
509 * of the first block.
511 struct nand_bbt_descr {
513 int pages[NAND_MAX_CHIPS];
516 uint8_t version[NAND_MAX_CHIPS];
519 int reserved_block_code;
523 /* Options for the bad block table descriptors */
525 /* The number of bits used per block in the bbt on the device */
526 #define NAND_BBT_NRBITS_MSK 0x0000000F
527 #define NAND_BBT_1BIT 0x00000001
528 #define NAND_BBT_2BIT 0x00000002
529 #define NAND_BBT_4BIT 0x00000004
530 #define NAND_BBT_8BIT 0x00000008
531 /* The bad block table is in the last good block of the device */
532 #define NAND_BBT_LASTBLOCK 0x00000010
533 /* The bbt is at the given page, else we must scan for the bbt */
534 #define NAND_BBT_ABSPAGE 0x00000020
535 /* The bbt is at the given page, else we must scan for the bbt */
536 #define NAND_BBT_SEARCH 0x00000040
537 /* bbt is stored per chip on multichip devices */
538 #define NAND_BBT_PERCHIP 0x00000080
539 /* bbt has a version counter at offset veroffs */
540 #define NAND_BBT_VERSION 0x00000100
541 /* Create a bbt if none axists */
542 #define NAND_BBT_CREATE 0x00000200
543 /* Search good / bad pattern through all pages of a block */
544 #define NAND_BBT_SCANALLPAGES 0x00000400
545 /* Scan block empty during good / bad block scan */
546 #define NAND_BBT_SCANEMPTY 0x00000800
547 /* Write bbt if neccecary */
548 #define NAND_BBT_WRITE 0x00001000
549 /* Read and write back block contents when writing bbt */
550 #define NAND_BBT_SAVECONTENT 0x00002000
551 /* Search good / bad pattern on the first and the second page */
552 #define NAND_BBT_SCAN2NDPAGE 0x00004000
554 /* The maximum number of blocks to scan for a bbt */
555 #define NAND_BBT_SCAN_MAXBLOCKS 4
557 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
558 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
559 extern int nand_default_bbt(struct mtd_info *mtd);
560 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
561 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
563 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
564 size_t * retlen, uint8_t * buf);
567 * Constants for oob configuration
569 #define NAND_SMALL_BADBLOCK_POS 5
570 #define NAND_LARGE_BADBLOCK_POS 0
573 * struct platform_nand_chip - chip level device structure
574 * @nr_chips: max. number of chips to scan for
575 * @chip_offset: chip number offset
576 * @nr_partitions: number of partitions pointed to by partitions (or zero)
577 * @partitions: mtd partition list
578 * @chip_delay: R/B delay value in us
579 * @options: Option flags, e.g. 16bit buswidth
580 * @ecclayout: ecc layout info structure
581 * @part_probe_types: NULL-terminated array of probe types
582 * @priv: hardware controller specific settings
584 struct platform_nand_chip {
588 struct mtd_partition *partitions;
589 struct nand_ecclayout *ecclayout;
591 unsigned int options;
592 const char **part_probe_types;
597 * struct platform_nand_ctrl - controller level device structure
598 * @hwcontrol: platform specific hardware control structure
599 * @dev_ready: platform specific function to read ready/busy pin
600 * @select_chip: platform specific chip select function
601 * @cmd_ctrl: platform specific function for controlling
602 * ALE/CLE/nCE. Also used to write command and address
603 * @priv: private data to transport driver specific settings
605 * All fields are optional and depend on the hardware driver requirements
607 struct platform_nand_ctrl {
608 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
609 int (*dev_ready)(struct mtd_info *mtd);
610 void (*select_chip)(struct mtd_info *mtd, int chip);
611 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
617 * struct platform_nand_data - container structure for platform-specific data
618 * @chip: chip level chip structure
619 * @ctrl: controller level device structure
621 struct platform_nand_data {
622 struct platform_nand_chip chip;
623 struct platform_nand_ctrl ctrl;
626 /* Some helpers to access the data structures */
628 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
630 struct nand_chip *chip = mtd->priv;
635 #endif /* __LINUX_MTD_NAND_H */