2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
23 #include "linux/compat.h"
24 #include "linux/mtd/mtd.h"
25 #include "linux/mtd/bbm.h"
29 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 extern int nand_scan (struct mtd_info *mtd, int max_chips);
32 /* Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type */
34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
35 const struct nand_flash_dev *table);
36 extern int nand_scan_tail(struct mtd_info *mtd);
38 /* Free resources held by the NAND device */
39 extern void nand_release(struct mtd_info *mtd);
41 /* Internal helper for board drivers which need to override command function */
42 extern void nand_wait_ready(struct mtd_info *mtd);
45 * This constant declares the max. oobsize / page, which
46 * is supported now. If you add a chip with bigger oobsize/page
47 * adjust this accordingly.
49 #define NAND_MAX_OOBSIZE 576
50 #define NAND_MAX_PAGESIZE 8192
53 * Constants for hardware specific CLE/ALE/NCE function
55 * These are bits which can be or'ed to set/clear multiple
58 /* Select the chip by setting nCE to low */
60 /* Select the command latch by setting CLE to high */
62 /* Select the address latch by setting ALE to high */
65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
67 #define NAND_CTRL_CHANGE 0x80
70 * Standard NAND flash commands
72 #define NAND_CMD_READ0 0
73 #define NAND_CMD_READ1 1
74 #define NAND_CMD_RNDOUT 5
75 #define NAND_CMD_PAGEPROG 0x10
76 #define NAND_CMD_READOOB 0x50
77 #define NAND_CMD_ERASE1 0x60
78 #define NAND_CMD_STATUS 0x70
79 #define NAND_CMD_STATUS_MULTI 0x71
80 #define NAND_CMD_SEQIN 0x80
81 #define NAND_CMD_RNDIN 0x85
82 #define NAND_CMD_READID 0x90
83 #define NAND_CMD_ERASE2 0xd0
84 #define NAND_CMD_PARAM 0xec
85 #define NAND_CMD_RESET 0xff
87 #define NAND_CMD_LOCK 0x2a
88 #define NAND_CMD_LOCK_TIGHT 0x2c
89 #define NAND_CMD_UNLOCK1 0x23
90 #define NAND_CMD_UNLOCK2 0x24
91 #define NAND_CMD_LOCK_STATUS 0x7a
93 /* Extended commands for large page devices */
94 #define NAND_CMD_READSTART 0x30
95 #define NAND_CMD_RNDOUTSTART 0xE0
96 #define NAND_CMD_CACHEDPROG 0x15
98 /* Extended commands for AG-AND device */
100 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
101 * there is no way to distinguish that from NAND_CMD_READ0
102 * until the remaining sequence of commands has been completed
103 * so add a high order bit and mask it off in the command.
105 #define NAND_CMD_DEPLETE1 0x100
106 #define NAND_CMD_DEPLETE2 0x38
107 #define NAND_CMD_STATUS_MULTI 0x71
108 #define NAND_CMD_STATUS_ERROR 0x72
109 /* multi-bank error status (banks 0-3) */
110 #define NAND_CMD_STATUS_ERROR0 0x73
111 #define NAND_CMD_STATUS_ERROR1 0x74
112 #define NAND_CMD_STATUS_ERROR2 0x75
113 #define NAND_CMD_STATUS_ERROR3 0x76
114 #define NAND_CMD_STATUS_RESET 0x7f
115 #define NAND_CMD_STATUS_CLEAR 0xff
117 #define NAND_CMD_NONE -1
120 #define NAND_STATUS_FAIL 0x01
121 #define NAND_STATUS_FAIL_N1 0x02
122 #define NAND_STATUS_TRUE_READY 0x20
123 #define NAND_STATUS_READY 0x40
124 #define NAND_STATUS_WP 0x80
127 * Constants for ECC_MODES
133 NAND_ECC_HW_SYNDROME,
134 NAND_ECC_HW_OOB_FIRST,
139 * Constants for Hardware ECC
141 /* Reset Hardware ECC for read */
142 #define NAND_ECC_READ 0
143 /* Reset Hardware ECC for write */
144 #define NAND_ECC_WRITE 1
145 /* Enable Hardware ECC before syndrom is read back from flash */
146 #define NAND_ECC_READSYN 2
148 /* Bit mask for flags passed to do_nand_read_ecc */
149 #define NAND_GET_DEVICE 0x80
153 * Option constants for bizarre disfunctionality and real
156 /* Chip can not auto increment pages */
157 #define NAND_NO_AUTOINCR 0x00000001
158 /* Buswitdh is 16 bit */
159 #define NAND_BUSWIDTH_16 0x00000002
160 /* Device supports partial programming without padding */
161 #define NAND_NO_PADDING 0x00000004
162 /* Chip has cache program function */
163 #define NAND_CACHEPRG 0x00000008
164 /* Chip has copy back function */
165 #define NAND_COPYBACK 0x00000010
167 * AND Chip which has 4 banks and a confusing page / block
168 * assignment. See Renesas datasheet for further information.
170 #define NAND_IS_AND 0x00000020
172 * Chip has a array of 4 pages which can be read without
173 * additional ready /busy waits.
175 #define NAND_4PAGE_ARRAY 0x00000040
177 * Chip requires that BBT is periodically rewritten to prevent
178 * bits from adjacent blocks from 'leaking' in altering data.
179 * This happens with the Renesas AG-AND chips, possibly others.
181 #define BBT_AUTO_REFRESH 0x00000080
183 * Chip does not require ready check on read. True
184 * for all large page devices, as they do not support
187 #define NAND_NO_READRDY 0x00000100
188 /* Chip does not allow subpage writes */
189 #define NAND_NO_SUBPAGE_WRITE 0x00000200
191 /* Device is one of 'new' xD cards that expose fake nand command set */
192 #define NAND_BROKEN_XD 0x00000400
194 /* Device behaves just like nand, but is readonly */
195 #define NAND_ROM 0x00000800
197 /* Options valid for Samsung large page devices */
198 #define NAND_SAMSUNG_LP_OPTIONS \
199 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
201 /* Macros to identify the above */
202 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
203 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
204 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
205 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
206 /* Large page NAND with SOFT_ECC should support subpage reads */
207 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
208 && (chip->page_shift > 9))
210 /* Mask to zero out the chip options, which come from the id table */
211 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
213 /* Non chip related options */
215 * Use a flash based bad block table. OOB identifier is saved in OOB area.
216 * This option is passed to the default bad block table function.
218 #define NAND_USE_FLASH_BBT 0x00010000
219 /* This option skips the bbt scan during initialization. */
220 #define NAND_SKIP_BBTSCAN 0x00020000
222 * This option is defined if the board driver allocates its own buffers
223 * (e.g. because it needs them DMA-coherent).
225 #define NAND_OWN_BUFFERS 0x00040000
226 /* Chip may not exist, so silence any errors in scan */
227 #define NAND_SCAN_SILENT_NODEV 0x00080000
229 * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
232 #define NAND_USE_FLASH_BBT_NO_OOB 0x00800000
233 /* Create an empty BBT with no vendor information if the BBT is available */
234 #define NAND_CREATE_EMPTY_BBT 0x01000000
236 /* Options set by nand scan */
237 /* bbt has already been read */
238 #define NAND_BBT_SCANNED 0x40000000
239 /* Nand scan has allocated controller struct */
240 #define NAND_CONTROLLER_ALLOC 0x80000000
242 /* Cell info constants */
243 #define NAND_CI_CHIPNR_MSK 0x03
244 #define NAND_CI_CELLTYPE_MSK 0x0C
249 struct nand_onfi_params {
250 /* rev info and features block */
251 /* 'O' 'N' 'F' 'I' */
258 /* manufacturer information block */
259 char manufacturer[12];
265 /* memory organization block */
266 __le32 byte_per_page;
267 __le16 spare_bytes_per_page;
268 __le32 data_bytes_per_ppage;
269 __le16 spare_bytes_per_ppage;
270 __le32 pages_per_block;
271 __le32 blocks_per_lun;
276 __le16 block_endurance;
277 u8 guaranteed_good_blocks;
278 __le16 guaranteed_block_endurance;
279 u8 programs_per_page;
286 /* electrical parameter block */
287 u8 io_pin_capacitance_max;
288 __le16 async_timing_mode;
289 __le16 program_cache_timing_mode;
294 __le16 src_sync_timing_mode;
295 __le16 src_ssync_features;
296 __le16 clk_pin_capacitance_typ;
297 __le16 io_pin_capacitance_typ;
298 __le16 input_pin_capacitance_typ;
299 u8 input_pin_capacitance_max;
300 u8 driver_strenght_support;
309 } __attribute__((packed));
311 #define ONFI_CRC_BASE 0x4F4E
314 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
315 * @lock: protection lock
316 * @active: the mtd device which holds the controller currently
317 * @wq: wait queue to sleep on if a NAND operation is in
318 * progress used instead of the per chip wait queue
319 * when a hw controller is available.
321 struct nand_hw_control {
325 wait_queue_head_t wq;
327 struct nand_chip *active;
331 * struct nand_ecc_ctrl - Control structure for ecc
333 * @steps: number of ecc steps per page
334 * @size: data bytes per ecc step
335 * @bytes: ecc bytes per step
336 * @total: total number of ecc bytes per page
337 * @prepad: padding information for syndrome based ecc generators
338 * @postpad: padding information for syndrome based ecc generators
339 * @layout: ECC layout control struct pointer
340 * @priv: pointer to private ecc control data
341 * @hwctl: function to control hardware ecc generator. Must only
342 * be provided if an hardware ECC is available
343 * @calculate: function for ecc calculation or readback from ecc hardware
344 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
345 * @read_page_raw: function to read a raw page without ECC
346 * @write_page_raw: function to write a raw page without ECC
347 * @read_page: function to read a page according to the ecc generator
349 * @read_subpage: function to read parts of the page covered by ECC.
350 * @write_page: function to write a page according to the ecc generator
352 * @read_oob: function to read chip OOB data
353 * @write_oob: function to write chip OOB data
355 struct nand_ecc_ctrl {
356 nand_ecc_modes_t mode;
363 struct nand_ecclayout *layout;
365 void (*hwctl)(struct mtd_info *mtd, int mode);
366 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
368 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
370 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
371 uint8_t *buf, int page);
372 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
374 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
375 uint8_t *buf, int page);
376 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
377 uint32_t offs, uint32_t len, uint8_t *buf);
378 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
380 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
382 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
387 * struct nand_buffers - buffer structure for read/write
388 * @ecccalc: buffer for calculated ecc
389 * @ecccode: buffer for ecc read from flash
390 * @databuf: buffer for data - dynamically sized
392 * Do not change the order of buffers. databuf and oobrbuf must be in
395 struct nand_buffers {
396 uint8_t ecccalc[NAND_MAX_OOBSIZE];
397 uint8_t ecccode[NAND_MAX_OOBSIZE];
398 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
402 * struct nand_chip - NAND Private Flash Chip Data
403 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
405 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
407 * @read_byte: [REPLACEABLE] read one byte from the chip
408 * @read_word: [REPLACEABLE] read one word from the chip
409 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
410 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
411 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip
413 * @select_chip: [REPLACEABLE] select chip nr
414 * @block_bad: [REPLACEABLE] check, if the block is bad
415 * @block_markbad: [REPLACEABLE] mark the block bad
416 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
417 * ALE/CLE/nCE. Also used to write command and address
418 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
419 * mtd->oobsize, mtd->writesize and so on.
420 * @id_data contains the 8 bytes values of NAND_CMD_READID.
421 * Return with the bus width.
422 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
423 * device ready/busy line. If set to NULL no access to
424 * ready/busy is available and the ready/busy information
425 * is read from the chip status register.
426 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
427 * commands to the chip.
428 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
430 * @ecc: [BOARDSPECIFIC] ecc control ctructure
431 * @buffers: buffer structure for read/write
432 * @hwcontrol: platform-specific hardware control structure
433 * @ops: oob operation operands
434 * @erase_cmd: [INTERN] erase command write function, selectable due
436 * @scan_bbt: [REPLACEABLE] function to scan bad block table
437 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
438 * data from array to read regs (tR).
439 * @state: [INTERN] the current state of the NAND device
440 * @oob_poi: poison value buffer
441 * @page_shift: [INTERN] number of address bits in a page (column
443 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
444 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
445 * @chip_shift: [INTERN] number of address bits in one chip
446 * @options: [BOARDSPECIFIC] various chip options. They can partly
447 * be set to inform nand_scan about special functionality.
448 * See the defines for further explanation.
449 * @badblockpos: [INTERN] position of the bad block marker in the oob
451 * @badblockbits: [INTERN] number of bits to left-shift the bad block
453 * @cellinfo: [INTERN] MLC/multichip data from chip ident
454 * @numchips: [INTERN] number of physical chips
455 * @chipsize: [INTERN] the size of one chip for multichip arrays
456 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
457 * @pagebuf: [INTERN] holds the pagenumber which is currently in
459 * @subpagesize: [INTERN] holds the subpagesize
460 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
461 * non 0 if ONFI supported.
462 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
463 * supported, 0 otherwise.
464 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
465 * @bbt: [INTERN] bad block table pointer
466 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
468 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
469 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
471 * @controller: [REPLACEABLE] a pointer to a hardware controller
472 * structure which is shared among multiple independend
474 * @priv: [OPTIONAL] pointer to private chip date
475 * @errstat: [OPTIONAL] hardware specific function to perform
476 * additional error status checks (determine if errors are
478 * @write_page: [REPLACEABLE] High-level page write function
482 void __iomem *IO_ADDR_R;
483 void __iomem *IO_ADDR_W;
485 uint8_t (*read_byte)(struct mtd_info *mtd);
486 u16 (*read_word)(struct mtd_info *mtd);
487 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
488 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
489 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
490 void (*select_chip)(struct mtd_info *mtd, int chip);
491 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
492 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
493 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
494 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
496 int (*dev_ready)(struct mtd_info *mtd);
497 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
499 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
500 void (*erase_cmd)(struct mtd_info *mtd, int page);
501 int (*scan_bbt)(struct mtd_info *mtd);
502 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
503 int status, int page);
504 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
505 const uint8_t *buf, int page, int cached, int raw);
508 unsigned int options;
511 int phys_erase_shift;
524 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
525 struct nand_onfi_params onfi_params;
531 struct nand_hw_control *controller;
532 struct nand_ecclayout *ecclayout;
534 struct nand_ecc_ctrl ecc;
535 struct nand_buffers *buffers;
536 struct nand_hw_control hwcontrol;
538 struct mtd_oob_ops ops;
541 struct nand_bbt_descr *bbt_td;
542 struct nand_bbt_descr *bbt_md;
544 struct nand_bbt_descr *badblock_pattern;
550 * NAND Flash Manufacturer ID Codes
552 #define NAND_MFR_TOSHIBA 0x98
553 #define NAND_MFR_SAMSUNG 0xec
554 #define NAND_MFR_FUJITSU 0x04
555 #define NAND_MFR_NATIONAL 0x8f
556 #define NAND_MFR_RENESAS 0x07
557 #define NAND_MFR_STMICRO 0x20
558 #define NAND_MFR_HYNIX 0xad
559 #define NAND_MFR_MICRON 0x2c
560 #define NAND_MFR_AMD 0x01
563 * struct nand_flash_dev - NAND Flash Device ID Structure
564 * @name: Identify the device type
565 * @id: device ID code
566 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
567 * If the pagesize is 0, then the real pagesize
568 * and the eraseize are determined from the
569 * extended id bytes in the chip
570 * @erasesize: Size of an erase block in the flash device.
571 * @chipsize: Total chipsize in Mega Bytes
572 * @options: Bitfield to store chip relevant options
574 struct nand_flash_dev {
577 unsigned long pagesize;
578 unsigned long chipsize;
579 unsigned long erasesize;
580 unsigned long options;
584 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
585 * @name: Manufacturer name
586 * @id: manufacturer ID code of device.
588 struct nand_manufacturers {
593 extern const struct nand_flash_dev nand_flash_ids[];
594 extern const struct nand_manufacturers nand_manuf_ids[];
596 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
597 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
598 extern int nand_default_bbt(struct mtd_info *mtd);
599 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
600 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
602 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
603 size_t *retlen, uint8_t *buf);
606 * Constants for oob configuration
608 #define NAND_SMALL_BADBLOCK_POS 5
609 #define NAND_LARGE_BADBLOCK_POS 0
612 * struct platform_nand_chip - chip level device structure
613 * @nr_chips: max. number of chips to scan for
614 * @chip_offset: chip number offset
615 * @nr_partitions: number of partitions pointed to by partitions (or zero)
616 * @partitions: mtd partition list
617 * @chip_delay: R/B delay value in us
618 * @options: Option flags, e.g. 16bit buswidth
619 * @ecclayout: ecc layout info structure
620 * @part_probe_types: NULL-terminated array of probe types
621 * @priv: hardware controller specific settings
623 struct platform_nand_chip {
627 struct mtd_partition *partitions;
628 struct nand_ecclayout *ecclayout;
630 unsigned int options;
631 const char **part_probe_types;
636 struct platform_device;
639 * struct platform_nand_ctrl - controller level device structure
640 * @hwcontrol: platform specific hardware control structure
641 * @dev_ready: platform specific function to read ready/busy pin
642 * @select_chip: platform specific chip select function
643 * @cmd_ctrl: platform specific function for controlling
644 * ALE/CLE/nCE. Also used to write command and address
645 * @priv: private data to transport driver specific settings
647 * All fields are optional and depend on the hardware driver requirements
649 struct platform_nand_ctrl {
650 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
651 int (*dev_ready)(struct mtd_info *mtd);
652 void (*select_chip)(struct mtd_info *mtd, int chip);
653 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
658 * struct platform_nand_data - container structure for platform-specific data
659 * @chip: chip level chip structure
660 * @ctrl: controller level device structure
662 struct platform_nand_data {
663 struct platform_nand_chip chip;
664 struct platform_nand_ctrl ctrl;
667 /* Some helpers to access the data structures */
669 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
671 struct nand_chip *chip = mtd->priv;
676 /* Standard NAND functions from nand_base.c */
677 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
678 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
679 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
680 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
681 uint8_t nand_read_byte(struct mtd_info *mtd);
683 #endif /* __LINUX_MTD_NAND_H */