1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #ifndef __LINUX_CLK_PROVIDER_H
10 #define __LINUX_CLK_PROVIDER_H
12 static inline void clk_dm(ulong id, struct clk *clk)
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
23 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
25 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
27 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
28 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
30 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
31 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
32 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
33 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
35 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
36 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
37 /* parents need enable during gate/ungate, set rate and re-parent */
38 #define CLK_OPS_PARENT_ENABLE BIT(12)
39 /* duty cycle call may be forwarded to the parent clock */
40 #define CLK_DUTY_CYCLE_PARENT BIT(13)
42 #define CLK_MUX_INDEX_ONE BIT(0)
43 #define CLK_MUX_INDEX_BIT BIT(1)
44 #define CLK_MUX_HIWORD_MASK BIT(2)
45 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
46 #define CLK_MUX_ROUND_CLOSEST BIT(4)
57 * Fields from struct clk_init_data - this struct has been
58 * omitted to avoid too deep level of CCF for bootloader
60 const char * const *parent_names;
64 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
66 struct clk_div_table {
77 const struct clk_div_table *table;
78 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
83 #define clk_div_mask(width) ((1 << (width)) - 1)
84 #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
86 #define CLK_DIVIDER_ONE_BASED BIT(0)
87 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
88 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
89 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
90 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
91 #define CLK_DIVIDER_READ_ONLY BIT(5)
92 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
94 struct clk_fixed_factor {
100 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
103 int clk_register(struct clk *clk, const char *drv_name, const char *name,
104 const char *parent_name);
106 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
107 const char *parent_name, unsigned long flags,
108 unsigned int mult, unsigned int div);
110 struct clk *clk_register_divider(struct device *dev, const char *name,
111 const char *parent_name, unsigned long flags,
112 void __iomem *reg, u8 shift, u8 width,
113 u8 clk_divider_flags);
115 struct clk *clk_register_mux(struct device *dev, const char *name,
116 const char * const *parent_names, u8 num_parents,
118 void __iomem *reg, u8 shift, u8 width,
121 const char *clk_hw_get_name(const struct clk *hw);
122 ulong clk_generic_get_rate(struct clk *clk);
124 static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
126 return (struct clk *)dev_get_uclass_priv(dev);
128 #endif /* __LINUX_CLK_PROVIDER_H */