1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #ifndef __LINUX_CLK_PROVIDER_H
10 #define __LINUX_CLK_PROVIDER_H
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <clk-uclass.h>
16 #include <linux/err.h>
18 static inline void clk_dm(ulong id, struct clk *clk)
25 * flags used across common struct clk. these flags should only affect the
26 * top-level framework. custom flags for dealing with hardware specifics
27 * belong in struct clk_foo
29 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
31 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
32 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
33 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
34 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
36 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
37 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
38 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
39 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
40 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
41 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
42 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
43 /* parents need enable during gate/ungate, set rate and re-parent */
44 #define CLK_OPS_PARENT_ENABLE BIT(12)
45 /* duty cycle call may be forwarded to the parent clock */
46 #define CLK_DUTY_CYCLE_PARENT BIT(13)
48 #define CLK_MUX_INDEX_ONE BIT(0)
49 #define CLK_MUX_INDEX_BIT BIT(1)
50 #define CLK_MUX_HIWORD_MASK BIT(2)
51 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
52 #define CLK_MUX_ROUND_CLOSEST BIT(4)
63 * Fields from struct clk_init_data - this struct has been
64 * omitted to avoid too deep level of CCF for bootloader
66 const char * const *parent_names;
68 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
74 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
75 extern const struct clk_ops clk_mux_ops;
76 u8 clk_mux_get_parent(struct clk *clk);
83 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
88 #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
90 #define CLK_GATE_SET_TO_DISABLE BIT(0)
91 #define CLK_GATE_HIWORD_MASK BIT(1)
93 extern const struct clk_ops clk_gate_ops;
94 struct clk *clk_register_gate(struct device *dev, const char *name,
95 const char *parent_name, unsigned long flags,
96 void __iomem *reg, u8 bit_idx,
97 u8 clk_gate_flags, spinlock_t *lock);
99 struct clk_div_table {
110 const struct clk_div_table *table;
111 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
116 #define clk_div_mask(width) ((1 << (width)) - 1)
117 #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
119 #define CLK_DIVIDER_ONE_BASED BIT(0)
120 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
121 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
122 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
123 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
124 #define CLK_DIVIDER_READ_ONLY BIT(5)
125 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
126 extern const struct clk_ops clk_divider_ops;
127 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
129 const struct clk_div_table *table,
130 unsigned long flags, unsigned long width);
132 struct clk_fixed_factor {
138 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
141 struct clk_fixed_rate {
143 unsigned long fixed_rate;
146 #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
148 struct clk_composite {
156 const struct clk_ops *mux_ops;
157 const struct clk_ops *rate_ops;
158 const struct clk_ops *gate_ops;
161 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
163 struct clk *clk_register_composite(struct device *dev, const char *name,
164 const char * const *parent_names, int num_parents,
165 struct clk *mux_clk, const struct clk_ops *mux_ops,
166 struct clk *rate_clk, const struct clk_ops *rate_ops,
167 struct clk *gate_clk, const struct clk_ops *gate_ops,
168 unsigned long flags);
170 int clk_register(struct clk *clk, const char *drv_name, const char *name,
171 const char *parent_name);
173 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
174 const char *parent_name, unsigned long flags,
175 unsigned int mult, unsigned int div);
177 struct clk *clk_register_divider(struct device *dev, const char *name,
178 const char *parent_name, unsigned long flags,
179 void __iomem *reg, u8 shift, u8 width,
180 u8 clk_divider_flags);
182 struct clk *clk_register_mux(struct device *dev, const char *name,
183 const char * const *parent_names, u8 num_parents,
185 void __iomem *reg, u8 shift, u8 width,
188 const char *clk_hw_get_name(const struct clk *hw);
189 ulong clk_generic_get_rate(struct clk *clk);
191 static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
193 return (struct clk *)dev_get_uclass_priv(dev);
195 #endif /* __LINUX_CLK_PROVIDER_H */