1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
10 int init_func_fpga(void);
13 FPGA_STATE_DONE_FAILED = 1 << 0,
14 FPGA_STATE_REFLECTION_FAILED = 1 << 1,
15 FPGA_STATE_PLATFORM = 1 << 2,
18 int get_fpga_state(unsigned dev);
20 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
21 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
23 extern struct ihs_fpga *fpga_ptr[];
25 #define FPGA_SET_REG(ix, fld, val) \
28 offsetof(struct ihs_fpga, fld), \
31 #define FPGA_GET_REG(ix, fld, val) \
34 offsetof(struct ihs_fpga, fld), \
46 u16 write_mailbox_ext;
80 u16 reflection_low; /* 0x0000 */
81 u16 versions; /* 0x0002 */
82 u16 fpga_features; /* 0x0004 */
83 u16 fpga_version; /* 0x0006 */
84 u16 reserved_0[8187]; /* 0x0008 */
85 u16 reflection_high; /* 0x3ffe */
89 #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
91 u16 reflection_low; /* 0x0000 */
92 u16 versions; /* 0x0002 */
93 u16 fpga_version; /* 0x0004 */
94 u16 fpga_features; /* 0x0006 */
95 u16 reserved_0[1]; /* 0x0008 */
96 u16 top_interrupt; /* 0x000a */
97 u16 reserved_1[2]; /* 0x000c */
98 u16 control; /* 0x0010 */
99 u16 extended_control; /* 0x0012 */
100 struct ihs_gpio gpio; /* 0x0014 */
101 u16 mpc3w_control; /* 0x001a */
102 u16 reserved_2[2]; /* 0x001c */
103 struct ihs_io_ep ep; /* 0x0020 */
104 u16 reserved_3[9]; /* 0x002e */
105 struct ihs_i2c i2c0; /* 0x0040 */
106 u16 reserved_4[10]; /* 0x004c */
107 u16 mc_int; /* 0x0060 */
108 u16 mc_int_en; /* 0x0062 */
109 u16 mc_status; /* 0x0064 */
110 u16 mc_control; /* 0x0066 */
111 u16 mc_tx_data; /* 0x0068 */
112 u16 mc_tx_address; /* 0x006a */
113 u16 mc_tx_cmd; /* 0x006c */
114 u16 mc_res; /* 0x006e */
115 u16 mc_rx_cmd_status; /* 0x0070 */
116 u16 mc_rx_data; /* 0x0072 */
117 u16 reserved_5[69]; /* 0x0074 */
118 u16 reflection_high; /* 0x00fe */
119 struct ihs_osd osd0; /* 0x0100 */
120 #ifdef CONFIG_SYS_OSD_DH
121 u16 reserved_6[57]; /* 0x010e */
122 struct ihs_osd osd1; /* 0x0180 */
123 u16 reserved_7[9]; /* 0x018e */
124 struct ihs_i2c i2c1; /* 0x01a0 */
125 u16 reserved_8[1834]; /* 0x01ac */
126 u16 videomem0[2048]; /* 0x1000 */
127 u16 videomem1[2048]; /* 0x2000 */
129 u16 reserved_6[889]; /* 0x010e */
130 u16 videomem0[2048]; /* 0x0800 */
135 #ifdef CONFIG_STRIDER_CPU
137 u16 reflection_low; /* 0x0000 */
138 u16 versions; /* 0x0002 */
139 u16 fpga_version; /* 0x0004 */
140 u16 fpga_features; /* 0x0006 */
141 u16 reserved_0[1]; /* 0x0008 */
142 u16 top_interrupt; /* 0x000a */
143 u16 reserved_1[3]; /* 0x000c */
144 u16 extended_control; /* 0x0012 */
145 struct ihs_gpio gpio; /* 0x0014 */
146 u16 mpc3w_control; /* 0x001a */
147 u16 reserved_2[2]; /* 0x001c */
148 struct ihs_io_ep ep; /* 0x0020 */
149 u16 reserved_3[9]; /* 0x002e */
150 u16 mc_int; /* 0x0040 */
151 u16 mc_int_en; /* 0x0042 */
152 u16 mc_status; /* 0x0044 */
153 u16 mc_control; /* 0x0046 */
154 u16 mc_tx_data; /* 0x0048 */
155 u16 mc_tx_address; /* 0x004a */
156 u16 mc_tx_cmd; /* 0x004c */
157 u16 mc_res; /* 0x004e */
158 u16 mc_rx_cmd_status; /* 0x0050 */
159 u16 mc_rx_data; /* 0x0052 */
160 u16 reserved_4[62]; /* 0x0054 */
161 struct ihs_i2c i2c0; /* 0x00d0 */
165 #ifdef CONFIG_STRIDER_CON
167 u16 reflection_low; /* 0x0000 */
168 u16 versions; /* 0x0002 */
169 u16 fpga_version; /* 0x0004 */
170 u16 fpga_features; /* 0x0006 */
171 u16 reserved_0[1]; /* 0x0008 */
172 u16 top_interrupt; /* 0x000a */
173 u16 reserved_1[4]; /* 0x000c */
174 struct ihs_gpio gpio; /* 0x0014 */
175 u16 mpc3w_control; /* 0x001a */
176 u16 reserved_2[2]; /* 0x001c */
177 struct ihs_io_ep ep; /* 0x0020 */
178 u16 reserved_3[9]; /* 0x002e */
179 struct ihs_i2c i2c0; /* 0x0040 */
180 u16 reserved_4[10]; /* 0x004c */
181 u16 mc_int; /* 0x0060 */
182 u16 mc_int_en; /* 0x0062 */
183 u16 mc_status; /* 0x0064 */
184 u16 mc_control; /* 0x0066 */
185 u16 mc_tx_data; /* 0x0068 */
186 u16 mc_tx_address; /* 0x006a */
187 u16 mc_tx_cmd; /* 0x006c */
188 u16 mc_res; /* 0x006e */
189 u16 mc_rx_cmd_status; /* 0x0070 */
190 u16 mc_rx_data; /* 0x0072 */
191 u16 reserved_5[70]; /* 0x0074 */
192 struct ihs_osd osd0; /* 0x0100 */
193 u16 reserved_6[889]; /* 0x010e */
194 u16 videomem0[2048]; /* 0x0800 */