2 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Register map and bit definitions for the Freescale NAND Flash Controller
28 * present in various i.MX devices.
30 * MX31 and MX27 have version 1, which has:
31 * 4 512-byte main buffers and
32 * 4 16-byte spare buffers
33 * to support up to 2K byte pagesize nand.
34 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
36 * MX25 and MX35 have version 1.1, which has:
37 * 8 512-byte main buffers and
38 * 8 64-byte spare buffers
39 * to support up to 4K byte pagesize nand.
40 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
41 * Also some of registers are moved and/or changed meaning as seen below.
43 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
45 #define is_mxc_nfc_11() 0
46 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
48 #define is_mxc_nfc_11() 1
50 #error "MXC NFC implementation not supported"
53 #if defined(MXC_NFC_V1)
54 #define NAND_MXC_NR_BUFS 4
55 #define NAND_MXC_SPARE_BUF_SIZE 16
56 #define NAND_MXC_REG_OFFSET 0xe00
57 #define NAND_MXC_2K_MULTI_CYCLE
58 #elif defined(MXC_NFC_V1_1)
59 #define NAND_MXC_NR_BUFS 8
60 #define NAND_MXC_SPARE_BUF_SIZE 64
61 #define NAND_MXC_REG_OFFSET 0x1e00
65 u8 main_area[NAND_MXC_NR_BUFS][0x200];
66 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
68 * reserved size is offset of nfc registers
69 * minus total main and spare sizes
71 u8 reserved1[NAND_MXC_REG_OFFSET
72 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
73 #if defined(MXC_NFC_V1)
80 u16 ecc_status_result;
84 u16 unlockstart_blkaddr;
85 u16 unlockend_blkaddr;
89 #elif defined(MXC_NFC_V1_1)
95 u32 ecc_status_result;
103 u16 unlockstart_blkaddr;
104 u16 unlockend_blkaddr;
105 u16 unlockstart_blkaddr1;
106 u16 unlockend_blkaddr1;
107 u16 unlockstart_blkaddr2;
108 u16 unlockend_blkaddr2;
109 u16 unlockstart_blkaddr3;
110 u16 unlockend_blkaddr3;
115 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
121 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
127 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
130 #define NFC_INPUT 0x4
133 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
136 #define NFC_OUTPUT 0x8
139 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
145 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
148 #define NFC_STATUS 0x20
151 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
154 #define NFC_INT 0x8000
157 #define NFC_4_8N_ECC (1 << 0)
159 #define NFC_SP_EN (1 << 2)
160 #define NFC_ECC_EN (1 << 3)
161 #define NFC_INT_MSK (1 << 4)
162 #define NFC_BIG (1 << 5)
163 #define NFC_RST (1 << 6)
164 #define NFC_CE (1 << 7)
165 #define NFC_ONE_CYCLE (1 << 8)
166 #define NFC_FP_INT (1 << 11)
168 #endif /* __FSL_NFC_H */