2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
13 * Pick a basic DDR Technology.
16 #include <fsl_ddrc_version.h>
18 #define SDRAM_TYPE_DDR1 2
19 #define SDRAM_TYPE_DDR2 3
20 #define SDRAM_TYPE_LPDDR1 6
21 #define SDRAM_TYPE_DDR3 7
22 #define SDRAM_TYPE_DDR4 5
24 #define DDR_BL4 4 /* burst length 4 */
25 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
26 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
27 #define DDR_BL8 8 /* burst length 8 */
29 #define DDR3_RTT_OFF 0
30 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
31 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
32 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
33 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
34 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
36 #define DDR2_RTT_OFF 0
37 #define DDR2_RTT_75_OHM 1
38 #define DDR2_RTT_150_OHM 2
39 #define DDR2_RTT_50_OHM 3
41 #if defined(CONFIG_SYS_FSL_DDR1)
42 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
43 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
44 #ifndef CONFIG_FSL_SDRAM_TYPE
45 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
47 #elif defined(CONFIG_SYS_FSL_DDR2)
48 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
49 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
50 #ifndef CONFIG_FSL_SDRAM_TYPE
51 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
53 #elif defined(CONFIG_SYS_FSL_DDR3)
54 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
55 #ifndef CONFIG_FSL_SDRAM_TYPE
56 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58 #elif defined(CONFIG_SYS_FSL_DDR4)
59 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
60 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
61 #ifndef CONFIG_FSL_SDRAM_TYPE
62 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
64 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
66 #define FSL_DDR_ODT_NEVER 0x0
67 #define FSL_DDR_ODT_CS 0x1
68 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
69 #define FSL_DDR_ODT_OTHER_DIMM 0x3
70 #define FSL_DDR_ODT_ALL 0x4
71 #define FSL_DDR_ODT_SAME_DIMM 0x5
72 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
73 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
75 /* define bank(chip select) interleaving mode */
76 #define FSL_DDR_CS0_CS1 0x40
77 #define FSL_DDR_CS2_CS3 0x20
78 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
79 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
81 /* define memory controller interleaving mode */
82 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
83 #define FSL_DDR_PAGE_INTERLEAVING 0x1
84 #define FSL_DDR_BANK_INTERLEAVING 0x2
85 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
86 #define FSL_DDR_256B_INTERLEAVING 0x8
87 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
88 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
89 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
90 /* placeholder for 4-way interleaving */
91 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
92 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
93 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
95 #define SDRAM_CS_CONFIG_EN 0x80000000
97 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
99 #define SDRAM_CFG_MEM_EN 0x80000000
100 #define SDRAM_CFG_SREN 0x40000000
101 #define SDRAM_CFG_ECC_EN 0x20000000
102 #define SDRAM_CFG_RD_EN 0x10000000
103 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
104 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
105 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
106 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
107 #define SDRAM_CFG_DYN_PWR 0x00200000
108 #define SDRAM_CFG_DBW_MASK 0x00180000
109 #define SDRAM_CFG_DBW_SHIFT 19
110 #define SDRAM_CFG_32_BE 0x00080000
111 #define SDRAM_CFG_16_BE 0x00100000
112 #define SDRAM_CFG_8_BE 0x00040000
113 #define SDRAM_CFG_NCAP 0x00020000
114 #define SDRAM_CFG_2T_EN 0x00008000
115 #define SDRAM_CFG_BI 0x00000001
117 #define SDRAM_CFG2_FRC_SR 0x80000000
118 #define SDRAM_CFG2_D_INIT 0x00000010
119 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
120 #define SDRAM_CFG2_ODT_NEVER 0
121 #define SDRAM_CFG2_ODT_ONLY_WRITE 1
122 #define SDRAM_CFG2_ODT_ONLY_READ 2
123 #define SDRAM_CFG2_ODT_ALWAYS 3
125 #define TIMING_CFG_2_CPO_MASK 0x0F800000
127 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
128 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
129 #define RD_TO_PRE_MASK 0xf
130 #define RD_TO_PRE_SHIFT 13
131 #define WR_DATA_DELAY_MASK 0xf
132 #define WR_DATA_DELAY_SHIFT 9
134 #define RD_TO_PRE_MASK 0x7
135 #define RD_TO_PRE_SHIFT 13
136 #define WR_DATA_DELAY_MASK 0x7
137 #define WR_DATA_DELAY_SHIFT 10
141 #define MD_CNTL_MD_EN 0x80000000
142 #define MD_CNTL_CS_SEL_CS0 0x00000000
143 #define MD_CNTL_CS_SEL_CS1 0x10000000
144 #define MD_CNTL_CS_SEL_CS2 0x20000000
145 #define MD_CNTL_CS_SEL_CS3 0x30000000
146 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
147 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
148 #define MD_CNTL_MD_SEL_MR 0x00000000
149 #define MD_CNTL_MD_SEL_EMR 0x01000000
150 #define MD_CNTL_MD_SEL_EMR2 0x02000000
151 #define MD_CNTL_MD_SEL_EMR3 0x03000000
152 #define MD_CNTL_SET_REF 0x00800000
153 #define MD_CNTL_SET_PRE 0x00400000
154 #define MD_CNTL_CKE_CNTL_LOW 0x00100000
155 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
156 #define MD_CNTL_WRCW 0x00080000
157 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
158 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
159 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
162 #define DDR_CDR1_DHC_EN 0x80000000
163 #define DDR_CDR1_ODT_SHIFT 17
164 #define DDR_CDR1_ODT_MASK 0x6
165 #define DDR_CDR2_ODT_MASK 0x1
166 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
167 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
168 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
169 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
171 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
172 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
173 #ifdef CONFIG_SYS_FSL_DDR3L
174 #define DDR_CDR_ODT_OFF 0x0
175 #define DDR_CDR_ODT_120ohm 0x1
176 #define DDR_CDR_ODT_200ohm 0x2
177 #define DDR_CDR_ODT_75ohm 0x3
178 #define DDR_CDR_ODT_60ohm 0x5
179 #define DDR_CDR_ODT_46ohm 0x7
180 #elif defined(CONFIG_SYS_FSL_DDR4)
181 #define DDR_CDR_ODT_OFF 0x0
182 #define DDR_CDR_ODT_100ohm 0x1
183 #define DDR_CDR_ODT_120OHM 0x2
184 #define DDR_CDR_ODT_80ohm 0x3
185 #define DDR_CDR_ODT_60ohm 0x4
186 #define DDR_CDR_ODT_40ohm 0x5
187 #define DDR_CDR_ODT_50ohm 0x6
188 #define DDR_CDR_ODT_30ohm 0x7
190 #define DDR_CDR_ODT_OFF 0x0
191 #define DDR_CDR_ODT_120ohm 0x1
192 #define DDR_CDR_ODT_180ohm 0x2
193 #define DDR_CDR_ODT_75ohm 0x3
194 #define DDR_CDR_ODT_110ohm 0x4
195 #define DDR_CDR_ODT_60hm 0x5
196 #define DDR_CDR_ODT_70ohm 0x6
197 #define DDR_CDR_ODT_47ohm 0x7
200 #define DDR_CDR_ODT_75ohm 0x0
201 #define DDR_CDR_ODT_55ohm 0x1
202 #define DDR_CDR_ODT_60ohm 0x2
203 #define DDR_CDR_ODT_50ohm 0x3
204 #define DDR_CDR_ODT_150ohm 0x4
205 #define DDR_CDR_ODT_43ohm 0x5
206 #define DDR_CDR_ODT_120ohm 0x6
209 #define DDR_INIT_ADDR_EXT_UIA (1 << 31)
211 /* Record of register values computed */
212 typedef struct fsl_ddr_cfg_regs_s {
216 unsigned int config_2;
217 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
218 unsigned int timing_cfg_3;
219 unsigned int timing_cfg_0;
220 unsigned int timing_cfg_1;
221 unsigned int timing_cfg_2;
222 unsigned int ddr_sdram_cfg;
223 unsigned int ddr_sdram_cfg_2;
224 unsigned int ddr_sdram_cfg_3;
225 unsigned int ddr_sdram_mode;
226 unsigned int ddr_sdram_mode_2;
227 unsigned int ddr_sdram_mode_3;
228 unsigned int ddr_sdram_mode_4;
229 unsigned int ddr_sdram_mode_5;
230 unsigned int ddr_sdram_mode_6;
231 unsigned int ddr_sdram_mode_7;
232 unsigned int ddr_sdram_mode_8;
233 unsigned int ddr_sdram_mode_9;
234 unsigned int ddr_sdram_mode_10;
235 unsigned int ddr_sdram_mode_11;
236 unsigned int ddr_sdram_mode_12;
237 unsigned int ddr_sdram_mode_13;
238 unsigned int ddr_sdram_mode_14;
239 unsigned int ddr_sdram_mode_15;
240 unsigned int ddr_sdram_mode_16;
241 unsigned int ddr_sdram_md_cntl;
242 unsigned int ddr_sdram_interval;
243 unsigned int ddr_data_init;
244 unsigned int ddr_sdram_clk_cntl;
245 unsigned int ddr_init_addr;
246 unsigned int ddr_init_ext_addr;
247 unsigned int timing_cfg_4;
248 unsigned int timing_cfg_5;
249 unsigned int timing_cfg_6;
250 unsigned int timing_cfg_7;
251 unsigned int timing_cfg_8;
252 unsigned int timing_cfg_9;
253 unsigned int ddr_zq_cntl;
254 unsigned int ddr_wrlvl_cntl;
255 unsigned int ddr_wrlvl_cntl_2;
256 unsigned int ddr_wrlvl_cntl_3;
257 unsigned int ddr_sr_cntr;
258 unsigned int ddr_sdram_rcw_1;
259 unsigned int ddr_sdram_rcw_2;
260 unsigned int ddr_sdram_rcw_3;
261 unsigned int ddr_sdram_rcw_4;
262 unsigned int ddr_sdram_rcw_5;
263 unsigned int ddr_sdram_rcw_6;
264 unsigned int dq_map_0;
265 unsigned int dq_map_1;
266 unsigned int dq_map_2;
267 unsigned int dq_map_3;
268 unsigned int ddr_eor;
269 unsigned int ddr_cdr1;
270 unsigned int ddr_cdr2;
271 unsigned int err_disable;
272 unsigned int err_int_en;
273 unsigned int debug[32];
274 } fsl_ddr_cfg_regs_t;
276 typedef struct memctl_options_partial_s {
277 unsigned int all_dimms_ecc_capable;
278 unsigned int all_dimms_tckmax_ps;
279 unsigned int all_dimms_burst_lengths_bitmask;
280 unsigned int all_dimms_registered;
281 unsigned int all_dimms_unbuffered;
282 /* unsigned int lowest_common_spd_caslat; */
283 unsigned int all_dimms_minimum_trcd_ps;
284 } memctl_options_partial_t;
286 #define DDR_DATA_BUS_WIDTH_64 0
287 #define DDR_DATA_BUS_WIDTH_32 1
288 #define DDR_DATA_BUS_WIDTH_16 2
289 #define DDR_CSWL_CS0 0x04000001
291 * Generalized parameters for memory controller configuration,
292 * might be a little specific to the FSL memory controller
294 typedef struct memctl_options_s {
296 * Memory organization parameters
298 * if DIMM is present in the system
299 * where DIMMs are with respect to chip select
300 * where chip selects are with respect to memory boundaries
302 unsigned int registered_dimm_en; /* use registered DIMM support */
304 /* Options local to a Chip Select */
305 struct cs_local_opts_s {
306 unsigned int auto_precharge;
307 unsigned int odt_rd_cfg;
308 unsigned int odt_wr_cfg;
309 unsigned int odt_rtt_norm;
310 unsigned int odt_rtt_wr;
311 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
313 /* Special configurations for chip select */
314 unsigned int memctl_interleaving;
315 unsigned int memctl_interleaving_mode;
316 unsigned int ba_intlv_ctl;
317 unsigned int addr_hash;
319 /* Operational mode parameters */
320 unsigned int ecc_mode; /* Use ECC? */
321 /* Initialize ECC using memory controller? */
322 unsigned int ecc_init_using_memctl;
323 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
324 /* SREN - self-refresh during sleep */
325 unsigned int self_refresh_in_sleep;
326 unsigned int dynamic_power; /* DYN_PWR */
327 /* memory data width to use (16-bit, 32-bit, 64-bit) */
328 unsigned int data_bus_width;
329 unsigned int burst_length; /* BL4, OTF and BL8 */
330 /* On-The-Fly Burst Chop enable */
331 unsigned int otf_burst_chop_en;
332 /* mirrior DIMMs for DDR3 */
333 unsigned int mirrored_dimm;
334 unsigned int quad_rank_present;
335 unsigned int ap_en; /* address parity enable for RDIMM */
336 unsigned int x4_en; /* enable x4 devices */
338 /* Global Timing Parameters */
339 unsigned int cas_latency_override;
340 unsigned int cas_latency_override_value;
341 unsigned int use_derated_caslat;
342 unsigned int additive_latency_override;
343 unsigned int additive_latency_override_value;
345 unsigned int clk_adjust; /* */
346 unsigned int cpo_override;
347 unsigned int write_data_delay; /* DQS adjust */
349 unsigned int cswl_override;
350 unsigned int wrlvl_override;
351 unsigned int wrlvl_sample; /* Write leveling */
352 unsigned int wrlvl_start;
353 unsigned int wrlvl_ctl_2;
354 unsigned int wrlvl_ctl_3;
356 unsigned int half_strength_driver_enable;
357 unsigned int twot_en;
358 unsigned int threet_en;
359 unsigned int bstopre;
360 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
363 unsigned int rtt_override; /* rtt_override enable */
364 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
365 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
367 /* Automatic self refresh */
368 unsigned int auto_self_refresh_en;
373 unsigned int wrlvl_en;
374 /* RCW override for RDIMM */
375 unsigned int rcw_override;
378 /* control register 1 */
379 unsigned int ddr_cdr1;
380 unsigned int ddr_cdr2;
382 unsigned int trwt_override;
383 unsigned int trwt; /* read-to-write turnaround */
386 phys_size_t fsl_ddr_sdram(void);
387 phys_size_t fsl_ddr_sdram_size(void);
388 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
389 unsigned int first_ctrl,
390 unsigned int num_ctrls,
391 unsigned int dimm_slots_per_ctrl,
392 int (*board_need_reset)(void),
393 void (*board_reset)(void),
394 void (*board_de_reset)(void));
395 extern int fsl_use_spd(void);
396 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
397 unsigned int ctrl_num, int step);
398 u32 fsl_ddr_get_intl3r(void);
399 void print_ddr_info(unsigned int start_ctrl);
401 static void __board_assert_mem_reset(void)
405 static void __board_deassert_mem_reset(void)
409 void board_assert_mem_reset(void)
410 __attribute__((weak, alias("__board_assert_mem_reset")));
412 void board_deassert_mem_reset(void)
413 __attribute__((weak, alias("__board_deassert_mem_reset")));
415 static int __board_need_mem_reset(void)
420 int board_need_mem_reset(void)
421 __attribute__((weak, alias("__board_need_mem_reset")));
423 #if defined(CONFIG_DEEP_SLEEP)
424 void board_mem_sleep_setup(void);
425 bool is_warm_boot(void);
426 int fsl_dp_resume(void);
430 * The 85xx boards have a common prototype for fixed_sdram so put the
433 #ifdef CONFIG_MPC85xx
434 extern phys_size_t fixed_sdram(void);
437 #if defined(CONFIG_DDR_ECC)
438 extern void ddr_enable_ecc(unsigned int dram_size);
442 typedef struct fixed_ddr_parm{
445 fsl_ddr_cfg_regs_t *ddr_settings;