2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
12 #define MC_CCSR_BASE_ADDR \
13 ((struct mc_ccsr_registers __iomem *)0x8340000)
15 #define BIT(x) (1 << (x))
16 #define GCR1_P1_STOP BIT(31)
17 #define GCR1_P2_STOP BIT(30)
18 #define GCR1_P1_DE_RST BIT(23)
19 #define GCR1_P2_DE_RST BIT(22)
20 #define GCR1_M1_DE_RST BIT(15)
21 #define GCR1_M2_DE_RST BIT(14)
22 #define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
23 #define GSR_FS_MASK 0x3fffffff
25 #define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
26 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
27 #define SOC_MC_PORTAL_STRIDE 0x10000
29 #define SOC_MC_PORTAL_ADDR(_portal_id) \
30 ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
31 (_portal_id) * SOC_MC_PORTAL_STRIDE))
33 struct mc_ccsr_registers {
53 int get_mc_boot_status(void);
54 unsigned long mc_get_dram_block_size(void);
55 int fsl_mc_ldpaa_init(bd_t *bis);
56 void fsl_mc_ldpaa_exit(bd_t *bis);