dm: core: Allow parents to pass data to children during probe
[oweals/u-boot.git] / include / fm_eth.h
1 /*
2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __FM_ETH_H__
8 #define __FM_ETH_H__
9
10 #include <common.h>
11 #include <phy.h>
12 #include <asm/types.h>
13
14 enum fm_port {
15         FM1_DTSEC1,
16         FM1_DTSEC2,
17         FM1_DTSEC3,
18         FM1_DTSEC4,
19         FM1_DTSEC5,
20         FM1_DTSEC6,
21         FM1_DTSEC9,
22         FM1_DTSEC10,
23         FM1_10GEC1,
24         FM1_10GEC2,
25         FM1_10GEC3,
26         FM1_10GEC4,
27         FM2_DTSEC1,
28         FM2_DTSEC2,
29         FM2_DTSEC3,
30         FM2_DTSEC4,
31         FM2_DTSEC5,
32         FM2_DTSEC6,
33         FM2_DTSEC9,
34         FM2_DTSEC10,
35         FM2_10GEC1,
36         FM2_10GEC2,
37         NUM_FM_PORTS,
38 };
39
40 enum fm_eth_type {
41         FM_ETH_1G_E,
42         FM_ETH_10G_E,
43 };
44
45 #ifdef CONFIG_SYS_FMAN_V3
46 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
47 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
48 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
49 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
50 #else
51 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
52 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
53 #endif
54
55 #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
56 #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
57
58 /* Fman ethernet info struct */
59 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
60         .fm             = idx,                                          \
61         .phy_regs       = (void *)pregs,                                \
62         .enet_if        = PHY_INTERFACE_MODE_NONE,                      \
63
64 #ifdef CONFIG_SYS_FMAN_V3
65 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
66 {                                                                       \
67         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)    \
68         .index          = idx,                                          \
69         .num            = n - 1,                                        \
70         .type           = FM_ETH_1G_E,                                  \
71         .port           = FM##idx##_DTSEC##n,                           \
72         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
73         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
74         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
75                                 offsetof(struct ccsr_fman, memac[n-1]),\
76 }
77
78 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
79 {                                                                       \
80         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
81         .index          = idx,                                          \
82         .num            = n - 1,                                        \
83         .type           = FM_ETH_10G_E,                                 \
84         .port           = FM##idx##_10GEC##n,                           \
85         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
86         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
87         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
88                                 offsetof(struct ccsr_fman, memac[n-1+8]),\
89 }
90
91 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
92 #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
93 {                                                                       \
94         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
95         .index          = idx,                                          \
96         .num            = n - 1,                                        \
97         .type           = FM_ETH_10G_E,                                 \
98         .port           = FM##idx##_10GEC##n,                           \
99         .rx_port_id     = RX_PORT_10G_BASE2 + n - 3,                    \
100         .tx_port_id     = TX_PORT_10G_BASE2 + n - 3,                    \
101         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
102                                 offsetof(struct ccsr_fman, memac[n-1-2]),\
103 }
104 #endif
105
106 #else
107 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
108 {                                                                       \
109         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)   \
110         .index          = idx,                                          \
111         .num            = n - 1,                                        \
112         .type           = FM_ETH_1G_E,                                  \
113         .port           = FM##idx##_DTSEC##n,                           \
114         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
115         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
116         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
117                                 offsetof(struct ccsr_fman, mac_1g[n-1]),\
118 }
119
120 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
121 {                                                                       \
122         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
123         .index          = idx,                                          \
124         .num            = n - 1,                                        \
125         .type           = FM_ETH_10G_E,                                 \
126         .port           = FM##idx##_10GEC##n,                           \
127         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
128         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
129         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
130                                 offsetof(struct ccsr_fman, mac_10g[n-1]),\
131 }
132 #endif
133 struct fm_eth_info {
134         u8 enabled;
135         u8 fm;
136         u8 num;
137         u8 phy_addr;
138         int index;
139         u16 rx_port_id;
140         u16 tx_port_id;
141         enum fm_port port;
142         enum fm_eth_type type;
143         void *phy_regs;
144         phy_interface_t enet_if;
145         u32 compat_offset;
146         struct mii_dev *bus;
147 };
148
149 struct tgec_mdio_info {
150         struct tgec_mdio_controller *regs;
151         char *name;
152 };
153
154 struct memac_mdio_info {
155         struct memac_mdio_controller *regs;
156         char *name;
157 };
158
159 int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
160 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
161
162 int fm_standard_init(bd_t *bis);
163 void fman_enet_init(void);
164 void fdt_fixup_fman_ethernet(void *fdt);
165 phy_interface_t fm_info_get_enet_if(enum fm_port port);
166 void fm_info_set_phy_address(enum fm_port port, int address);
167 int fm_info_get_phy_address(enum fm_port port);
168 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
169 void fm_disable_port(enum fm_port port);
170 void fm_enable_port(enum fm_port port);
171 void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
172                 unsigned int port_num, int phy_base_addr);
173 int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
174                 unsigned int port_num, unsigned regnum);
175
176 #endif