1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 MediaTek Inc.
6 #ifndef _DT_BINDINGS_MTK_RESET_H_
7 #define _DT_BINDINGS_MTK_RESET_H_
9 /* PCIe Subsystem resets */
10 #define PCIE1_CORE_RST 19
11 #define PCIE1_MMIO_RST 20
13 #define PCIE1_USER_RST 22
14 #define PCIE1_PIPE_RST 23
15 #define PCIE0_CORE_RST 27
16 #define PCIE0_MMIO_RST 28
18 #define PCIE0_USER_RST 30
19 #define PCIE0_PIPE_RST 31
21 /* SSUSB Subsystem resets */
22 #define SSUSB_PHY_PWR_RST 3
23 #define SSUSB_MAC_PWR_RST 4
25 /* ETH Subsystem resets */
26 #define ETHSYS_SYS_RST 0
27 #define ETHSYS_MCM_RST 2
28 #define ETHSYS_HSDMA_RST 5
29 #define ETHSYS_FE_RST 6
30 #define ETHSYS_ESW_RST 16
31 #define ETHSYS_GMAC_RST 23
32 #define ETHSYS_EPHY_RST 24
33 #define ETHSYS_CRYPTO_RST 29
34 #define ETHSYS_PPE_RST 31
36 #endif /* _DT_BINDINGS_MTK_RESET_H_ */