1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
20 /* sclk gates (special clocks) */
36 #define SCLK_SARADC 80
41 #define SCLK_SPDIF_8CH 85
42 #define SCLK_I2S0_8CH 86
43 #define SCLK_I2S1_8CH 87
44 #define SCLK_I2S2_8CH 88
45 #define SCLK_I2S_8CH_OUT 89
46 #define SCLK_TIMER00 90
47 #define SCLK_TIMER01 91
48 #define SCLK_TIMER02 92
49 #define SCLK_TIMER03 93
50 #define SCLK_TIMER04 94
51 #define SCLK_TIMER05 95
52 #define SCLK_TIMER06 96
53 #define SCLK_TIMER07 97
54 #define SCLK_TIMER08 98
55 #define SCLK_TIMER09 99
56 #define SCLK_TIMER10 100
57 #define SCLK_TIMER11 101
58 #define SCLK_MACREF 102
59 #define SCLK_MAC_RX 103
60 #define SCLK_MAC_TX 104
62 #define SCLK_MACREF_OUT 106
63 #define SCLK_VOP0_PWM 107
64 #define SCLK_VOP1_PWM 108
65 #define SCLK_RGA_CORE 109
68 #define SCLK_HDMI_CEC 112
69 #define SCLK_HDMI_SFR 113
70 #define SCLK_DP_CORE 114
71 #define SCLK_PVTM_CORE_L 115
72 #define SCLK_PVTM_CORE_B 116
73 #define SCLK_PVTM_GPU 117
74 #define SCLK_PVTM_DDR 118
75 #define SCLK_MIPIDPHY_REF 119
76 #define SCLK_MIPIDPHY_CFG 120
77 #define SCLK_HSICPHY 121
78 #define SCLK_USBPHY480M 122
79 #define SCLK_USB2PHY0_REF 123
80 #define SCLK_USB2PHY1_REF 124
81 #define SCLK_UPHY0_TCPDPHY_REF 125
82 #define SCLK_UPHY0_TCPDCORE 126
83 #define SCLK_UPHY1_TCPDPHY_REF 127
84 #define SCLK_UPHY1_TCPDCORE 128
85 #define SCLK_USB3OTG0_REF 129
86 #define SCLK_USB3OTG1_REF 130
87 #define SCLK_USB3OTG0_SUSPEND 131
88 #define SCLK_USB3OTG1_SUSPEND 132
89 #define SCLK_CRYPTO0 133
90 #define SCLK_CRYPTO1 134
91 #define SCLK_CCI_TRACE 135
93 #define SCLK_CIF_OUT 137
94 #define SCLK_PCIEPHY_REF 138
95 #define SCLK_PCIE_CORE 139
96 #define SCLK_M0_PERILP 140
97 #define SCLK_M0_PERILP_DEC 141
99 #define SCLK_DBG_NOC 143
100 #define SCLK_DBG_PD_CORE_B 144
101 #define SCLK_DBG_PD_CORE_L 145
102 #define SCLK_DFIMON0_TIMER 146
103 #define SCLK_DFIMON1_TIMER 147
104 #define SCLK_INTMEM0 148
105 #define SCLK_INTMEM1 149
106 #define SCLK_INTMEM2 150
107 #define SCLK_INTMEM3 151
108 #define SCLK_INTMEM4 152
109 #define SCLK_INTMEM5 153
110 #define SCLK_SDMMC_DRV 154
111 #define SCLK_SDMMC_SAMPLE 155
112 #define SCLK_SDIO_DRV 156
113 #define SCLK_SDIO_SAMPLE 157
114 #define SCLK_VDU_CORE 158
115 #define SCLK_VDU_CA 159
116 #define SCLK_PCIE_PM 160
117 #define SCLK_SPDIF_REC_DPTX 161
118 #define SCLK_DPHY_PLL 162
119 #define SCLK_DPHY_TX0_CFG 163
120 #define SCLK_DPHY_TX1RX1_CFG 164
121 #define SCLK_DPHY_RX0_CFG 165
122 #define SCLK_RMII_SRC 166
123 #define SCLK_PCIEPHY_REF100M 167
124 #define SCLK_USBPHY0_480M_SRC 168
125 #define SCLK_USBPHY1_480M_SRC 169
126 #define SCLK_DDRCLK 170
127 #define SCLK_TESTOUT2 171
129 #define DCLK_VOP0 180
130 #define DCLK_VOP1 181
131 #define DCLK_VOP0_DIV 182
132 #define DCLK_VOP1_DIV 183
133 #define DCLK_M0_PERILP 184
135 #define FCLK_CM0S 190
138 #define ACLK_PERIHP 192
139 #define ACLK_PERIHP_NOC 193
140 #define ACLK_PERILP0 194
141 #define ACLK_PERILP0_NOC 195
142 #define ACLK_PERF_PCIE 196
143 #define ACLK_PCIE 197
144 #define ACLK_INTMEM 198
145 #define ACLK_TZMA 199
148 #define ACLK_CCI_NOC0 202
149 #define ACLK_CCI_NOC1 203
150 #define ACLK_CCI_GRF 204
151 #define ACLK_CENTER 205
152 #define ACLK_CENTER_MAIN_NOC 206
153 #define ACLK_CENTER_PERI_NOC 207
155 #define ACLK_PERF_GPU 209
156 #define ACLK_GPU_GRF 210
157 #define ACLK_DMAC0_PERILP 211
158 #define ACLK_DMAC1_PERILP 212
159 #define ACLK_GMAC 213
160 #define ACLK_GMAC_NOC 214
161 #define ACLK_PERF_GMAC 215
162 #define ACLK_VOP0_NOC 216
163 #define ACLK_VOP0 217
164 #define ACLK_VOP1_NOC 218
165 #define ACLK_VOP1 219
167 #define ACLK_RGA_NOC 221
168 #define ACLK_HDCP 222
169 #define ACLK_HDCP_NOC 223
170 #define ACLK_HDCP22 224
172 #define ACLK_IEP_NOC 226
174 #define ACLK_VIO_NOC 228
175 #define ACLK_ISP0 229
176 #define ACLK_ISP1 230
177 #define ACLK_ISP0_NOC 231
178 #define ACLK_ISP1_NOC 232
179 #define ACLK_ISP0_WRAPPER 233
180 #define ACLK_ISP1_WRAPPER 234
181 #define ACLK_VCODEC 235
182 #define ACLK_VCODEC_NOC 236
184 #define ACLK_VDU_NOC 238
185 #define ACLK_PERI 239
186 #define ACLK_EMMC 240
187 #define ACLK_EMMC_CORE 241
188 #define ACLK_EMMC_NOC 242
189 #define ACLK_EMMC_GRF 243
190 #define ACLK_USB3 244
191 #define ACLK_USB3_NOC 245
192 #define ACLK_USB3OTG0 246
193 #define ACLK_USB3OTG1 247
194 #define ACLK_USB3_RKSOC_AXI_PERF 248
195 #define ACLK_USB3_GRF 249
197 #define ACLK_GIC_NOC 251
198 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
199 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
200 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
201 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
202 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
203 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
204 #define ACLK_ADB400M_PD_CORE_L 258
205 #define ACLK_ADB400M_PD_CORE_B 259
206 #define ACLK_PERF_CORE_L 260
207 #define ACLK_PERF_CORE_B 261
208 #define ACLK_GIC_PRE 262
209 #define ACLK_VOP0_PRE 263
210 #define ACLK_VOP1_PRE 264
213 #define PCLK_PERIHP 320
214 #define PCLK_PERIHP_NOC 321
215 #define PCLK_PERILP0 322
216 #define PCLK_PERILP1 323
217 #define PCLK_PERILP1_NOC 324
218 #define PCLK_PERILP_SGRF 325
219 #define PCLK_PERIHP_GRF 326
220 #define PCLK_PCIE 327
221 #define PCLK_SGRF 328
222 #define PCLK_INTR_ARB 329
223 #define PCLK_CENTER_MAIN_NOC 330
225 #define PCLK_COREDBG_B 332
226 #define PCLK_COREDBG_L 333
227 #define PCLK_DBG_CXCS_PD_CORE_B 334
229 #define PCLK_GPIO2 336
230 #define PCLK_GPIO3 337
231 #define PCLK_GPIO4 338
233 #define PCLK_HSICPHY 340
234 #define PCLK_I2C1 341
235 #define PCLK_I2C2 342
236 #define PCLK_I2C3 343
237 #define PCLK_I2C5 344
238 #define PCLK_I2C6 345
239 #define PCLK_I2C7 346
240 #define PCLK_SPI0 347
241 #define PCLK_SPI1 348
242 #define PCLK_SPI2 349
243 #define PCLK_SPI4 350
244 #define PCLK_SPI5 351
245 #define PCLK_UART0 352
246 #define PCLK_UART1 353
247 #define PCLK_UART2 354
248 #define PCLK_UART3 355
249 #define PCLK_TSADC 356
250 #define PCLK_SARADC 357
251 #define PCLK_GMAC 358
252 #define PCLK_GMAC_NOC 359
253 #define PCLK_TIMER0 360
254 #define PCLK_TIMER1 361
256 #define PCLK_EDP_NOC 363
257 #define PCLK_EDP_CTRL 364
259 #define PCLK_VIO_NOC 366
260 #define PCLK_VIO_GRF 367
261 #define PCLK_MIPI_DSI0 368
262 #define PCLK_MIPI_DSI1 369
263 #define PCLK_HDCP 370
264 #define PCLK_HDCP_NOC 371
265 #define PCLK_HDMI_CTRL 372
266 #define PCLK_DP_CTRL 373
267 #define PCLK_HDCP22 374
268 #define PCLK_GASKET 375
270 #define PCLK_DDR_MON 377
271 #define PCLK_DDR_SGRF 378
272 #define PCLK_ISP1_WRAPPER 379
274 #define PCLK_EFUSE1024NS 381
275 #define PCLK_EFUSE1024S 382
276 #define PCLK_PMU_INTR_ARB 383
277 #define PCLK_MAILBOX0 384
278 #define PCLK_USBPHY_MUX_G 385
279 #define PCLK_UPHY0_TCPHY_G 386
280 #define PCLK_UPHY0_TCPD_G 387
281 #define PCLK_UPHY1_TCPHY_G 388
282 #define PCLK_UPHY1_TCPD_G 389
283 #define PCLK_ALIVE 390
286 #define HCLK_PERIHP 448
287 #define HCLK_PERILP0 449
288 #define HCLK_PERILP1 450
289 #define HCLK_PERILP0_NOC 451
290 #define HCLK_PERILP1_NOC 452
291 #define HCLK_M0_PERILP 453
292 #define HCLK_M0_PERILP_NOC 454
293 #define HCLK_AHB1TOM 455
294 #define HCLK_HOST0 456
295 #define HCLK_HOST0_ARB 457
296 #define HCLK_HOST1 458
297 #define HCLK_HOST1_ARB 459
298 #define HCLK_HSIC 460
300 #define HCLK_SDMMC 462
301 #define HCLK_SDMMC_NOC 463
302 #define HCLK_M_CRYPTO0 464
303 #define HCLK_M_CRYPTO1 465
304 #define HCLK_S_CRYPTO0 466
305 #define HCLK_S_CRYPTO1 467
306 #define HCLK_I2S0_8CH 468
307 #define HCLK_I2S1_8CH 469
308 #define HCLK_I2S2_8CH 470
309 #define HCLK_SPDIF 471
310 #define HCLK_VOP0_NOC 472
311 #define HCLK_VOP0 473
312 #define HCLK_VOP1_NOC 474
313 #define HCLK_VOP1 475
316 #define HCLK_IEP_NOC 478
317 #define HCLK_ISP0 479
318 #define HCLK_ISP1 480
319 #define HCLK_ISP0_NOC 481
320 #define HCLK_ISP1_NOC 482
321 #define HCLK_ISP0_WRAPPER 483
322 #define HCLK_ISP1_WRAPPER 484
324 #define HCLK_RGA_NOC 486
325 #define HCLK_HDCP 487
326 #define HCLK_HDCP_NOC 488
327 #define HCLK_HDCP22 489
328 #define HCLK_VCODEC 490
329 #define HCLK_VCODEC_NOC 491
331 #define HCLK_VDU_NOC 493
332 #define HCLK_SDIO 494
333 #define HCLK_SDIO_NOC 495
334 #define HCLK_SDIOAUDIO_NOC 496
336 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
338 /* pmu-clocks indices */
342 #define SCLK_32K_SUSPEND_PMU 2
343 #define SCLK_SPI3_PMU 3
344 #define SCLK_TIMER12_PMU 4
345 #define SCLK_TIMER13_PMU 5
346 #define SCLK_UART4_PMU 6
347 #define SCLK_PVTM_PMU 7
348 #define SCLK_WIFI_PMU 8
349 #define SCLK_I2C0_PMU 9
350 #define SCLK_I2C4_PMU 10
351 #define SCLK_I2C8_PMU 11
353 #define PCLK_SRC_PMU 19
355 #define PCLK_PMUGRF_PMU 21
356 #define PCLK_INTMEM1_PMU 22
357 #define PCLK_GPIO0_PMU 23
358 #define PCLK_GPIO1_PMU 24
359 #define PCLK_SGRF_PMU 25
360 #define PCLK_NOC_PMU 26
361 #define PCLK_I2C0_PMU 27
362 #define PCLK_I2C4_PMU 28
363 #define PCLK_I2C8_PMU 29
364 #define PCLK_RKPWM_PMU 30
365 #define PCLK_SPI3_PMU 31
366 #define PCLK_TIMER_PMU 32
367 #define PCLK_MAILBOX_PMU 33
368 #define PCLK_UART4_PMU 34
369 #define PCLK_WDT_M0_PMU 35
371 #define FCLK_CM0S_SRC_PMU 44
372 #define FCLK_CM0S_PMU 45
373 #define SCLK_CM0S_PMU 46
374 #define HCLK_CM0S_PMU 47
375 #define DCLK_CM0S_PMU 48
376 #define PCLK_INTR_ARB_PMU 49
377 #define HCLK_NOC_PMU 50
379 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
381 /* soft-reset indices */
383 /* cru_softrst_con0 */
384 #define SRST_CORE_L0 0
385 #define SRST_CORE_B0 1
386 #define SRST_CORE_PO_L0 2
387 #define SRST_CORE_PO_B0 3
393 #define SRST_A_CCIM0_NOC 9
394 #define SRST_A_CCIM1_NOC 10
395 #define SRST_DBG_NOC 11
397 /* cru_softrst_con1 */
398 #define SRST_CORE_L0_T 16
399 #define SRST_CORE_L1 17
400 #define SRST_CORE_L2 18
401 #define SRST_CORE_L3 19
402 #define SRST_CORE_PO_L0_T 20
403 #define SRST_CORE_PO_L1 21
404 #define SRST_CORE_PO_L2 22
405 #define SRST_CORE_PO_L3 23
406 #define SRST_A_ADB400_GIC2COREL 24
407 #define SRST_A_ADB400_COREL2GIC 25
408 #define SRST_P_DBG_L 26
409 #define SRST_L2_L_T 28
410 #define SRST_ADB_L_T 29
411 #define SRST_A_RKPERF_L 30
412 #define SRST_PVTM_CORE_L 31
414 /* cru_softrst_con2 */
415 #define SRST_CORE_B0_T 32
416 #define SRST_CORE_B1 33
417 #define SRST_CORE_PO_B0_T 36
418 #define SRST_CORE_PO_B1 37
419 #define SRST_A_ADB400_GIC2COREB 40
420 #define SRST_A_ADB400_COREB2GIC 41
421 #define SRST_P_DBG_B 42
422 #define SRST_L2_B_T 43
423 #define SRST_ADB_B_T 45
424 #define SRST_A_RKPERF_B 46
425 #define SRST_PVTM_CORE_B 47
427 /* cru_softrst_con3 */
428 #define SRST_A_CCI_T 50
429 #define SRST_A_CCIM0_NOC_T 51
430 #define SRST_A_CCIM1_NOC_T 52
431 #define SRST_A_ADB400M_PD_CORE_B_T 53
432 #define SRST_A_ADB400M_PD_CORE_L_T 54
433 #define SRST_DBG_NOC_T 55
434 #define SRST_DBG_CXCS 56
435 #define SRST_CCI_TRACE 57
436 #define SRST_P_CCI_GRF 58
438 /* cru_softrst_con4 */
439 #define SRST_A_CENTER_MAIN_NOC 64
440 #define SRST_A_CENTER_PERI_NOC 65
441 #define SRST_P_CENTER_MAIN 66
442 #define SRST_P_DDRMON 67
443 #define SRST_P_CIC 68
444 #define SRST_P_CENTER_SGRF 69
445 #define SRST_DDR0_MSCH 70
446 #define SRST_DDRCFG0_MSCH 71
448 #define SRST_DDRPHY0 73
449 #define SRST_DDR1_MSCH 74
450 #define SRST_DDRCFG1_MSCH 75
452 #define SRST_DDRPHY1 77
453 #define SRST_DDR_CIC 78
454 #define SRST_PVTM_DDR 79
456 /* cru_softrst_con5 */
457 #define SRST_A_VCODEC_NOC 80
458 #define SRST_A_VCODEC 81
459 #define SRST_H_VCODEC_NOC 82
460 #define SRST_H_VCODEC 83
461 #define SRST_A_VDU_NOC 88
462 #define SRST_A_VDU 89
463 #define SRST_H_VDU_NOC 90
464 #define SRST_H_VDU 91
465 #define SRST_VDU_CORE 92
466 #define SRST_VDU_CA 93
468 /* cru_softrst_con6 */
469 #define SRST_A_IEP_NOC 96
470 #define SRST_A_VOP_IEP 97
471 #define SRST_A_IEP 98
472 #define SRST_H_IEP_NOC 99
473 #define SRST_H_IEP 100
474 #define SRST_A_RGA_NOC 102
475 #define SRST_A_RGA 103
476 #define SRST_H_RGA_NOC 104
477 #define SRST_H_RGA 105
478 #define SRST_RGA_CORE 106
479 #define SRST_EMMC_NOC 108
480 #define SRST_EMMC 109
481 #define SRST_EMMC_GRF 110
483 /* cru_softrst_con7 */
484 #define SRST_A_PERIHP_NOC 112
485 #define SRST_P_PERIHP_GRF 113
486 #define SRST_H_PERIHP_NOC 114
487 #define SRST_USBHOST0 115
488 #define SRST_HOSTC0_AUX 116
489 #define SRST_HOST0_ARB 117
490 #define SRST_USBHOST1 118
491 #define SRST_HOSTC1_AUX 119
492 #define SRST_HOST1_ARB 120
493 #define SRST_SDIO0 121
494 #define SRST_SDMMC 122
495 #define SRST_HSIC 123
496 #define SRST_HSIC_AUX 124
497 #define SRST_AHB1TOM 125
498 #define SRST_P_PERIHP_NOC 126
499 #define SRST_HSICPHY 127
501 /* cru_softrst_con8 */
502 #define SRST_A_PCIE 128
503 #define SRST_P_PCIE 129
504 #define SRST_PCIE_CORE 130
505 #define SRST_PCIE_MGMT 131
506 #define SRST_PCIE_MGMT_STICKY 132
507 #define SRST_PCIE_PIPE 133
508 #define SRST_PCIE_PM 134
509 #define SRST_PCIEPHY 135
510 #define SRST_A_GMAC_NOC 136
511 #define SRST_A_GMAC 137
512 #define SRST_P_GMAC_NOC 138
513 #define SRST_P_GMAC_GRF 140
514 #define SRST_HSICPHY_POR 142
515 #define SRST_HSICPHY_UTMI 143
517 /* cru_softrst_con9 */
518 #define SRST_USB2PHY0_POR 144
519 #define SRST_USB2PHY0_UTMI_PORT0 145
520 #define SRST_USB2PHY0_UTMI_PORT1 146
521 #define SRST_USB2PHY0_EHCIPHY 147
522 #define SRST_UPHY0_PIPE_L00 148
523 #define SRST_UPHY0 149
524 #define SRST_UPHY0_TCPDPWRUP 150
525 #define SRST_USB2PHY1_POR 152
526 #define SRST_USB2PHY1_UTMI_PORT0 153
527 #define SRST_USB2PHY1_UTMI_PORT1 154
528 #define SRST_USB2PHY1_EHCIPHY 155
529 #define SRST_UPHY1_PIPE_L00 156
530 #define SRST_UPHY1 157
531 #define SRST_UPHY1_TCPDPWRUP 158
533 /* cru_softrst_con10 */
534 #define SRST_A_PERILP0_NOC 160
535 #define SRST_A_DCF 161
536 #define SRST_GIC500 162
537 #define SRST_DMAC0_PERILP0 163
538 #define SRST_DMAC1_PERILP0 164
539 #define SRST_TZMA 165
540 #define SRST_INTMEM 166
541 #define SRST_ADB400_MST0 167
542 #define SRST_ADB400_MST1 168
543 #define SRST_ADB400_SLV0 169
544 #define SRST_ADB400_SLV1 170
545 #define SRST_H_PERILP0 171
546 #define SRST_H_PERILP0_NOC 172
548 #define SRST_CRYPTO_S 174
549 #define SRST_CRYPTO_M 175
551 /* cru_softrst_con11 */
552 #define SRST_P_DCF 176
553 #define SRST_CM0S_NOC 177
554 #define SRST_CM0S 178
555 #define SRST_CM0S_DBG 179
556 #define SRST_CM0S_PO 180
557 #define SRST_CRYPTO 181
558 #define SRST_P_PERILP1_SGRF 182
559 #define SRST_P_PERILP1_GRF 183
560 #define SRST_CRYPTO1_S 184
561 #define SRST_CRYPTO1_M 185
562 #define SRST_CRYPTO1 186
563 #define SRST_GIC_NOC 188
564 #define SRST_SD_NOC 189
565 #define SRST_SDIOAUDIO_BRG 190
567 /* cru_softrst_con12 */
568 #define SRST_H_PERILP1 192
569 #define SRST_H_PERILP1_NOC 193
570 #define SRST_H_I2S0_8CH 194
571 #define SRST_H_I2S1_8CH 195
572 #define SRST_H_I2S2_8CH 196
573 #define SRST_H_SPDIF_8CH 197
574 #define SRST_P_PERILP1_NOC 198
575 #define SRST_P_EFUSE_1024 199
576 #define SRST_P_EFUSE_1024S 200
577 #define SRST_P_I2C0 201
578 #define SRST_P_I2C1 202
579 #define SRST_P_I2C2 203
580 #define SRST_P_I2C3 204
581 #define SRST_P_I2C4 205
582 #define SRST_P_I2C5 206
583 #define SRST_P_MAILBOX0 207
585 /* cru_softrst_con13 */
586 #define SRST_P_UART0 208
587 #define SRST_P_UART1 209
588 #define SRST_P_UART2 210
589 #define SRST_P_UART3 211
590 #define SRST_P_SARADC 212
591 #define SRST_P_TSADC 213
592 #define SRST_P_SPI0 214
593 #define SRST_P_SPI1 215
594 #define SRST_P_SPI2 216
595 #define SRST_P_SPI4 217
596 #define SRST_P_SPI5 218
597 #define SRST_SPI0 219
598 #define SRST_SPI1 220
599 #define SRST_SPI2 221
600 #define SRST_SPI4 222
601 #define SRST_SPI5 223
603 /* cru_softrst_con14 */
604 #define SRST_I2S0_8CH 224
605 #define SRST_I2S1_8CH 225
606 #define SRST_I2S2_8CH 226
607 #define SRST_SPDIF_8CH 227
608 #define SRST_UART0 228
609 #define SRST_UART1 229
610 #define SRST_UART2 230
611 #define SRST_UART3 231
612 #define SRST_TSADC 232
613 #define SRST_I2C0 233
614 #define SRST_I2C1 234
615 #define SRST_I2C2 235
616 #define SRST_I2C3 236
617 #define SRST_I2C4 237
618 #define SRST_I2C5 238
619 #define SRST_SDIOAUDIO_NOC 239
621 /* cru_softrst_con15 */
622 #define SRST_A_VIO_NOC 240
623 #define SRST_A_HDCP_NOC 241
624 #define SRST_A_HDCP 242
625 #define SRST_H_HDCP_NOC 243
626 #define SRST_H_HDCP 244
627 #define SRST_P_HDCP_NOC 245
628 #define SRST_P_HDCP 246
629 #define SRST_P_HDMI_CTRL 247
630 #define SRST_P_DP_CTRL 248
631 #define SRST_S_DP_CTRL 249
632 #define SRST_C_DP_CTRL 250
633 #define SRST_P_MIPI_DSI0 251
634 #define SRST_P_MIPI_DSI1 252
635 #define SRST_DP_CORE 253
636 #define SRST_DP_I2S 254
638 /* cru_softrst_con16 */
639 #define SRST_GASKET 256
640 #define SRST_VIO_GRF 258
641 #define SRST_DPTX_SPDIF_REC 259
642 #define SRST_HDMI_CTRL 260
643 #define SRST_HDCP_CTRL 261
644 #define SRST_A_ISP0_NOC 262
645 #define SRST_A_ISP1_NOC 263
646 #define SRST_H_ISP0_NOC 266
647 #define SRST_H_ISP1_NOC 267
648 #define SRST_H_ISP0 268
649 #define SRST_H_ISP1 269
650 #define SRST_ISP0 270
651 #define SRST_ISP1 271
653 /* cru_softrst_con17 */
654 #define SRST_A_VOP0_NOC 272
655 #define SRST_A_VOP1_NOC 273
656 #define SRST_A_VOP0 274
657 #define SRST_A_VOP1 275
658 #define SRST_H_VOP0_NOC 276
659 #define SRST_H_VOP1_NOC 277
660 #define SRST_H_VOP0 278
661 #define SRST_H_VOP1 279
662 #define SRST_D_VOP0 280
663 #define SRST_D_VOP1 281
664 #define SRST_VOP0_PWM 282
665 #define SRST_VOP1_PWM 283
666 #define SRST_P_EDP_NOC 284
667 #define SRST_P_EDP_CTRL 285
669 /* cru_softrst_con18 */
670 #define SRST_A_GPU 288
671 #define SRST_A_GPU_NOC 289
672 #define SRST_A_GPU_GRF 290
673 #define SRST_PVTM_GPU 291
674 #define SRST_A_USB3_NOC 292
675 #define SRST_A_USB3_OTG0 293
676 #define SRST_A_USB3_OTG1 294
677 #define SRST_A_USB3_GRF 295
680 /* cru_softrst_con19 */
681 #define SRST_P_TIMER0_5 304
682 #define SRST_TIMER0 305
683 #define SRST_TIMER1 306
684 #define SRST_TIMER2 307
685 #define SRST_TIMER3 308
686 #define SRST_TIMER4 309
687 #define SRST_TIMER5 310
688 #define SRST_P_TIMER6_11 311
689 #define SRST_TIMER6 312
690 #define SRST_TIMER7 313
691 #define SRST_TIMER8 314
692 #define SRST_TIMER9 315
693 #define SRST_TIMER10 316
694 #define SRST_TIMER11 317
695 #define SRST_P_INTR_ARB_PMU 318
696 #define SRST_P_ALIVE_SGRF 319
698 /* cru_softrst_con20 */
699 #define SRST_P_GPIO2 320
700 #define SRST_P_GPIO3 321
701 #define SRST_P_GPIO4 322
702 #define SRST_P_GRF 323
703 #define SRST_P_ALIVE_NOC 324
704 #define SRST_P_WDT0 325
705 #define SRST_P_WDT1 326
706 #define SRST_P_INTR_ARB 327
707 #define SRST_P_UPHY0_DPTX 328
708 #define SRST_P_UPHY0_APB 330
709 #define SRST_P_UPHY0_TCPHY 332
710 #define SRST_P_UPHY1_TCPHY 333
711 #define SRST_P_UPHY0_TCPDCTRL 334
712 #define SRST_P_UPHY1_TCPDCTRL 335
714 /* pmu soft-reset indices */
716 /* pmu_cru_softrst_con0 */
718 #define SRST_P_INTMEM 1
719 #define SRST_H_CM0S 2
720 #define SRST_H_CM0S_NOC 3
721 #define SRST_DBG_CM0S 4
722 #define SRST_PO_CM0S 5
723 #define SRST_P_SPI3 6
725 #define SRST_P_TIMER_0_1 8
726 #define SRST_P_TIMER_0 9
727 #define SRST_P_TIMER_1 10
728 #define SRST_P_UART4 11
729 #define SRST_UART4 12
730 #define SRST_P_WDT 13
732 /* pmu_cru_softrst_con1 */
733 #define SRST_P_I2C6 16
734 #define SRST_P_I2C7 17
735 #define SRST_P_I2C8 18
736 #define SRST_P_MAILBOX 19
737 #define SRST_P_RKPWM 20
738 #define SRST_P_PMUGRF 21
739 #define SRST_P_SGRF 22
740 #define SRST_P_GPIO0 23
741 #define SRST_P_GPIO1 24
742 #define SRST_P_CRU 25
743 #define SRST_P_INTR 26