2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * SPDX-License-Identifier: GPL-2.0+
16 /* sclk gates (special clocks) */
26 #define SCLK_SARADC 73
28 #define SCLK_NANDC0 75
29 #define SCLK_NANDC1 76
37 #define SCLK_SPDIF8CH 84
38 #define SCLK_TIMER0 85
39 #define SCLK_TIMER1 86
40 #define SCLK_TIMER2 87
41 #define SCLK_TIMER3 88
42 #define SCLK_TIMER4 89
43 #define SCLK_TIMER5 90
44 #define SCLK_TIMER6 91
46 #define SCLK_OTGPHY0 93
47 #define SCLK_OTGPHY1 94
48 #define SCLK_OTGPHY2 95
49 #define SCLK_OTG_ADP 96
50 #define SCLK_HSICPHY480M 97
51 #define SCLK_HSICPHY12M 98
52 #define SCLK_MACREF 99
53 #define SCLK_LCDC_PWM0 100
54 #define SCLK_LCDC_PWM1 101
55 #define SCLK_MAC_RX 102
56 #define SCLK_MAC_TX 103
57 #define SCLK_EDP_24M 104
61 #define SCLK_ISP_JPE 108
62 #define SCLK_HDMI_HDCP 109
63 #define SCLK_HDMI_CEC 110
64 #define SCLK_HEVC_CABAC 111
65 #define SCLK_HEVC_CORE 112
66 #define SCLK_I2S0_OUT 113
67 #define SCLK_SDMMC_DRV 114
68 #define SCLK_SDIO0_DRV 115
69 #define SCLK_SDIO1_DRV 116
70 #define SCLK_EMMC_DRV 117
71 #define SCLK_SDMMC_SAMPLE 118
72 #define SCLK_SDIO0_SAMPLE 119
73 #define SCLK_SDIO1_SAMPLE 120
74 #define SCLK_EMMC_SAMPLE 121
75 #define SCLK_USBPHY480M_SRC 122
76 #define SCLK_PVTM_CORE 123
77 #define SCLK_PVTM_GPU 124
79 #define SCLK_MAC_PLL 150
81 #define SCLK_MACREF_OUT 152
88 #define ACLK_DMAC1 193
89 #define ACLK_DMAC2 194
94 #define ACLK_CRYPTO 199
96 #define ACLK_RGA_NIU 201
98 #define ACLK_VIO0_NIU 203
101 #define ACLK_VIO1_NIU 206
102 #define ACLK_HEVC 207
103 #define ACLK_VCODEC 208
105 #define ACLK_PERI 210
108 #define PCLK_GPIO0 320
109 #define PCLK_GPIO1 321
110 #define PCLK_GPIO2 322
111 #define PCLK_GPIO3 323
112 #define PCLK_GPIO4 324
113 #define PCLK_GPIO5 325
114 #define PCLK_GPIO6 326
115 #define PCLK_GPIO7 327
116 #define PCLK_GPIO8 328
118 #define PCLK_SGRF 330
120 #define PCLK_I2C0 332
121 #define PCLK_I2C1 333
122 #define PCLK_I2C2 334
123 #define PCLK_I2C3 335
124 #define PCLK_I2C4 336
125 #define PCLK_I2C5 337
126 #define PCLK_SPI0 338
127 #define PCLK_SPI1 339
128 #define PCLK_SPI2 340
129 #define PCLK_UART0 341
130 #define PCLK_UART1 342
131 #define PCLK_UART2 343
132 #define PCLK_UART3 344
133 #define PCLK_UART4 345
134 #define PCLK_TSADC 346
135 #define PCLK_SARADC 347
137 #define PCLK_GMAC 349
139 #define PCLK_RKPWM 351
140 #define PCLK_PS2C 352
141 #define PCLK_TIMER 353
142 #define PCLK_TZPC 354
143 #define PCLK_EDP_CTRL 355
144 #define PCLK_MIPI_DSI0 356
145 #define PCLK_MIPI_DSI1 357
146 #define PCLK_MIPI_CSI 358
147 #define PCLK_LVDS_PHY 359
148 #define PCLK_HDMI_CTRL 360
149 #define PCLK_VIO2_H2P 361
151 #define PCLK_PERI 363
152 #define PCLK_DDRUPCTL0 364
153 #define PCLK_PUBL0 365
154 #define PCLK_DDRUPCTL1 366
155 #define PCLK_PUBL1 367
160 #define HCLK_OTG0 449
161 #define HCLK_USBHOST0 450
162 #define HCLK_USBHOST1 451
163 #define HCLK_HSIC 452
164 #define HCLK_NANDC0 453
165 #define HCLK_NANDC1 454
167 #define HCLK_SDMMC 456
168 #define HCLK_SDIO0 457
169 #define HCLK_SDIO1 458
170 #define HCLK_EMMC 459
171 #define HCLK_HSADC 460
172 #define HCLK_CRYPTO 461
173 #define HCLK_I2S0 462
174 #define HCLK_SPDIF 463
175 #define HCLK_SPDIF8CH 464
176 #define HCLK_VOP0 465
177 #define HCLK_VOP1 466
182 #define HCLK_VIO_AHB_ARBI 471
183 #define HCLK_VIO_NIU 472
185 #define HCLK_VIO2_H2P 474
186 #define HCLK_HEVC 475
187 #define HCLK_VCODEC 476
189 #define HCLK_PERI 478
191 #define CLK_NR_CLKS (HCLK_PERI + 1)
193 /* soft-reset indices */
198 #define SRST_CORE0_PO 4
199 #define SRST_CORE1_PO 5
200 #define SRST_CORE2_PO 6
201 #define SRST_CORE3_PO 7
202 #define SRST_PDCORE_STRSYS 8
203 #define SRST_PDBUS_STRSYS 9
205 #define SRST_TOPDBG 11
206 #define SRST_CORE0_DBG 12
207 #define SRST_CORE1_DBG 13
208 #define SRST_CORE2_DBG 14
209 #define SRST_CORE3_DBG 15
211 #define SRST_PDBUG_AHB_ARBITOR 16
212 #define SRST_EFUSE256 17
213 #define SRST_DMAC1 18
214 #define SRST_INTMEM 19
216 #define SRST_SPDIF8CH 21
217 #define SRST_TIMER 22
219 #define SRST_SPDIF 24
220 #define SRST_TIMER0 25
221 #define SRST_TIMER1 26
222 #define SRST_TIMER2 27
223 #define SRST_TIMER3 28
224 #define SRST_TIMER4 29
225 #define SRST_TIMER5 30
226 #define SRST_EFUSE 31
228 #define SRST_GPIO0 32
229 #define SRST_GPIO1 33
230 #define SRST_GPIO2 34
231 #define SRST_GPIO3 35
232 #define SRST_GPIO4 36
233 #define SRST_GPIO5 37
234 #define SRST_GPIO6 38
235 #define SRST_GPIO7 39
236 #define SRST_GPIO8 40
244 #define SRST_DWPWM 48
245 #define SRST_MMC_PERI 49
246 #define SRST_PERIPH_MMU 50
248 #define SRST_DAP_SYS 52
250 #define SRST_PMU_APB 54
253 #define SRST_PERIPH_AXI 57
254 #define SRST_PERIPH_AHB 58
255 #define SRST_PERIPH_APB 59
256 #define SRST_PERIPH_NIU 60
257 #define SRST_PDPERI_AHB_ARBI 61
259 #define SRST_USB_PERI 63
261 #define SRST_DMAC2 64
264 #define SRST_RKPWM 69
266 #define SRST_USBHOST0 72
268 #define SRST_HSIC_AUX 74
269 #define SRST_HSIC_PHY 75
270 #define SRST_HSADC 76
271 #define SRST_NANDC0 77
272 #define SRST_NANDC1 78
278 #define SRST_SARADC 87
279 #define SRST_PDALIVE_NIU 88
280 #define SRST_PDPMU_INTMEM 89
281 #define SRST_PDPMU_NIU 90
284 #define SRST_VIO_ARBI 96
285 #define SRST_RGA_NIU 97
286 #define SRST_VIO0_NIU_AXI 98
287 #define SRST_VIO_NIU_AHB 99
288 #define SRST_LCDC0_AXI 100
289 #define SRST_LCDC0_AHB 101
290 #define SRST_LCDC0_DCLK 102
291 #define SRST_VIO1_NIU_AXI 103
293 #define SRST_RGA_CORE 105
294 #define SRST_IEP_AXI 106
295 #define SRST_IEP_AHB 107
296 #define SRST_RGA_AXI 108
297 #define SRST_RGA_AHB 109
301 #define SRST_VCODEC_AXI 112
302 #define SRST_VCODEC_AHB 113
303 #define SRST_VIO_H2P 114
304 #define SRST_MIPIDSI0 115
305 #define SRST_MIPIDSI1 116
306 #define SRST_MIPICSI 117
307 #define SRST_LVDS_PHY 118
308 #define SRST_LVDS_CON 119
310 #define SRST_HDMI 121
311 #define SRST_CORE_PVTM 124
312 #define SRST_GPU_PVTM 125
314 #define SRST_MMC0 128
315 #define SRST_SDIO0 129
316 #define SRST_SDIO1 130
317 #define SRST_EMMC 131
318 #define SRST_USBOTG_AHB 132
319 #define SRST_USBOTG_PHY 133
320 #define SRST_USBOTG_CON 134
321 #define SRST_USBHOST0_AHB 135
322 #define SRST_USBHOST0_PHY 136
323 #define SRST_USBHOST0_CON 137
324 #define SRST_USBHOST1_AHB 138
325 #define SRST_USBHOST1_PHY 139
326 #define SRST_USBHOST1_CON 140
327 #define SRST_USB_ADP 141
328 #define SRST_ACC_EFUSE 142
330 #define SRST_CORESIGHT 144
331 #define SRST_PD_CORE_AHB_NOC 145
332 #define SRST_PD_CORE_APB_NOC 146
333 #define SRST_PD_CORE_MP_AXI 147
335 #define SRST_LCDC_PWM0 149
336 #define SRST_LCDC_PWM1 150
337 #define SRST_VIO0_H2P_BRG 151
338 #define SRST_VIO1_H2P_BRG 152
339 #define SRST_RGA_H2P_BRG 153
340 #define SRST_HEVC 154
341 #define SRST_TSADC 159
343 #define SRST_DDRPHY0 160
344 #define SRST_DDRPHY0_APB 161
345 #define SRST_DDRCTRL0 162
346 #define SRST_DDRCTRL0_APB 163
347 #define SRST_DDRPHY0_CTRL 164
348 #define SRST_DDRPHY1 165
349 #define SRST_DDRPHY1_APB 166
350 #define SRST_DDRCTRL1 167
351 #define SRST_DDRCTRL1_APB 168
352 #define SRST_DDRPHY1_CTRL 169
353 #define SRST_DDRMSCH0 170
354 #define SRST_DDRMSCH1 171
355 #define SRST_CRYPTO 174
356 #define SRST_C2C_HOST 175
358 #define SRST_LCDC1_AXI 176
359 #define SRST_LCDC1_AHB 177
360 #define SRST_LCDC1_DCLK 178
361 #define SRST_UART0 179
362 #define SRST_UART1 180
363 #define SRST_UART2 181
364 #define SRST_UART3 182
365 #define SRST_UART4 183
366 #define SRST_SIMC 186
367 #define SRST_PS2C 187
369 #define SRST_TSP_CLKIN0 189
370 #define SRST_TSP_CLKIN1 190
371 #define SRST_TSP_27M 191