2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 /* sclk gates (special clocks) */
31 #define SCLK_TIMER0 85
32 #define SCLK_TIMER1 86
33 #define SCLK_TIMER2 87
34 #define SCLK_TIMER3 88
35 #define SCLK_TIMER4 89
36 #define SCLK_TIMER5 90
37 #define SCLK_I2S_OUT 113
38 #define SCLK_SDMMC_DRV 114
39 #define SCLK_SDIO_DRV 115
40 #define SCLK_EMMC_DRV 117
41 #define SCLK_SDMMC_SAMPLE 118
42 #define SCLK_SDIO_SAMPLE 119
43 #define SCLK_EMMC_SAMPLE 121
45 #define SCLK_HDMI_HDCP 123
46 #define SCLK_MAC_SRC 124
47 #define SCLK_MAC_EXTCLK 125
49 #define SCLK_MAC_REFOUT 127
50 #define SCLK_MAC_REF 128
51 #define SCLK_MAC_RX 129
52 #define SCLK_MAC_TX 130
53 #define SCLK_MAC_PHY 131
54 #define SCLK_MAC_OUT 132
58 #define DCLK_HDMI_PHY 191
67 #define PCLK_GPIO0 320
68 #define PCLK_GPIO1 321
69 #define PCLK_GPIO2 322
70 #define PCLK_GPIO3 323
77 #define PCLK_UART0 341
78 #define PCLK_UART1 342
79 #define PCLK_UART2 343
80 #define PCLK_TSADC 344
82 #define PCLK_TIMER 353
84 #define PCLK_HDMI_CTRL 364
85 #define PCLK_HDMI_PHY 365
89 #define HCLK_I2S0_8CH 442
90 #define HCLK_I2S1_8CH 443
91 #define HCLK_I2S2_2CH 444
92 #define HCLK_SPDIF_8CH 445
94 #define HCLK_NANDC 453
95 #define HCLK_SDMMC 456
100 #define CLK_NR_CLKS (HCLK_PERI + 1)
102 /* soft-reset indices */
103 #define SRST_CORE0_PO 0
104 #define SRST_CORE1_PO 1
105 #define SRST_CORE2_PO 2
106 #define SRST_CORE3_PO 3
111 #define SRST_CORE0_DBG 8
112 #define SRST_CORE1_DBG 9
113 #define SRST_CORE2_DBG 10
114 #define SRST_CORE3_DBG 11
115 #define SRST_TOPDBG 12
116 #define SRST_ACLK_CORE 13
120 #define SRST_CPUSYS_H 18
121 #define SRST_BUSSYS_H 19
122 #define SRST_SPDIF 20
123 #define SRST_INTMEM 21
125 #define SRST_OTG_ADP 23
129 #define SRST_ACODEC_P 27
130 #define SRST_DFIMON 28
132 #define SRST_EFUSE1024 30
133 #define SRST_EFUSE256 31
135 #define SRST_GPIO0 32
136 #define SRST_GPIO1 33
137 #define SRST_GPIO2 34
138 #define SRST_GPIO3 35
139 #define SRST_PERIPH_NOC_A 36
140 #define SRST_PERIPH_NOC_BUS_H 37
141 #define SRST_PERIPH_NOC_P 38
142 #define SRST_UART0 39
143 #define SRST_UART1 40
144 #define SRST_UART2 41
145 #define SRST_PHYNOC 42
152 #define SRST_A53_GIC 49
154 #define SRST_DAP_NOC 52
155 #define SRST_CRYPTO 53
159 #define SRST_PERIPH_NOC_H 58
160 #define SRST_MACPHY 63
163 #define SRST_NANDC 68
164 #define SRST_USBOTG 69
166 #define SRST_USBHOST0 71
167 #define SRST_HOST_CTRL0 72
168 #define SRST_USBHOST1 73
169 #define SRST_HOST_CTRL1 74
170 #define SRST_USBHOST2 75
171 #define SRST_HOST_CTRL2 76
172 #define SRST_USBPOR0 77
173 #define SRST_USBPOR1 78
174 #define SRST_DDRMSCH 79
176 #define SRST_SMART_CARD 80
177 #define SRST_SDMMC 81
181 #define SRST_TSP_H 85
183 #define SRST_TSADC 87
184 #define SRST_DDRPHY 88
185 #define SRST_DDRPHY_P 89
186 #define SRST_DDRCTRL 90
187 #define SRST_DDRCTRL_P 91
188 #define SRST_HOST0_ECHI 92
189 #define SRST_HOST1_ECHI 93
190 #define SRST_HOST2_ECHI 94
191 #define SRST_VOP_NOC_A 95
193 #define SRST_HDMI_P 96
194 #define SRST_VIO_ARBI_H 97
195 #define SRST_IEP_NOC_A 98
196 #define SRST_VIO_NOC_H 99
197 #define SRST_VOP_A 100
198 #define SRST_VOP_H 101
199 #define SRST_VOP_D 102
200 #define SRST_UTMI0 103
201 #define SRST_UTMI1 104
202 #define SRST_UTMI2 105
203 #define SRST_UTMI3 106
205 #define SRST_RGA_NOC_A 108
206 #define SRST_RGA_A 109
207 #define SRST_RGA_H 110
208 #define SRST_HDCP_A 111
210 #define SRST_VPU_A 112
211 #define SRST_VPU_H 113
212 #define SRST_VPU_NOC_A 116
213 #define SRST_VPU_NOC_H 117
214 #define SRST_RKVDEC_A 118
215 #define SRST_RKVDEC_NOC_A 119
216 #define SRST_RKVDEC_H 120
217 #define SRST_RKVDEC_NOC_H 121
218 #define SRST_RKVDEC_CORE 122
219 #define SRST_RKVDEC_CABAC 123
220 #define SRST_IEP_A 124
221 #define SRST_IEP_H 125
222 #define SRST_GPU_A 126
223 #define SRST_GPU_NOC_A 127
225 #define SRST_CORE_DBG 128
226 #define SRST_DBG_P 129
227 #define SRST_TIMER0 130
228 #define SRST_TIMER1 131
229 #define SRST_TIMER2 132
230 #define SRST_TIMER3 133
231 #define SRST_TIMER4 134
232 #define SRST_TIMER5 135
233 #define SRST_VIO_H2P 136
234 #define SRST_HDMIPHY 139
235 #define SRST_VDAC 140
236 #define SRST_TIMER_6CH_P 141