1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
16 /* sclk gates (special clocks) */
30 #define SCLK_TIMER0 85
31 #define SCLK_TIMER1 86
32 #define SCLK_TIMER2 87
33 #define SCLK_TIMER3 88
34 #define SCLK_TIMER4 89
35 #define SCLK_TIMER5 90
36 #define SCLK_I2S_OUT 113
37 #define SCLK_SDMMC_DRV 114
38 #define SCLK_SDIO_DRV 115
39 #define SCLK_EMMC_DRV 117
40 #define SCLK_SDMMC_SAMPLE 118
41 #define SCLK_SDIO_SAMPLE 119
42 #define SCLK_EMMC_SAMPLE 121
44 #define SCLK_HDMI_HDCP 123
45 #define SCLK_MAC_SRC 124
46 #define SCLK_MAC_EXTCLK 125
48 #define SCLK_MAC_REFOUT 127
49 #define SCLK_MAC_REF 128
50 #define SCLK_MAC_RX 129
51 #define SCLK_MAC_TX 130
52 #define SCLK_MAC_PHY 131
53 #define SCLK_MAC_OUT 132
57 #define DCLK_HDMI_PHY 191
66 #define PCLK_GPIO0 320
67 #define PCLK_GPIO1 321
68 #define PCLK_GPIO2 322
69 #define PCLK_GPIO3 323
76 #define PCLK_UART0 341
77 #define PCLK_UART1 342
78 #define PCLK_UART2 343
79 #define PCLK_TSADC 344
81 #define PCLK_TIMER 353
83 #define PCLK_HDMI_CTRL 364
84 #define PCLK_HDMI_PHY 365
88 #define HCLK_I2S0_8CH 442
89 #define HCLK_I2S1_8CH 443
90 #define HCLK_I2S2_2CH 444
91 #define HCLK_SPDIF_8CH 445
93 #define HCLK_NANDC 453
94 #define HCLK_SDMMC 456
99 #define CLK_NR_CLKS (HCLK_PERI + 1)
101 /* soft-reset indices */
102 #define SRST_CORE0_PO 0
103 #define SRST_CORE1_PO 1
104 #define SRST_CORE2_PO 2
105 #define SRST_CORE3_PO 3
110 #define SRST_CORE0_DBG 8
111 #define SRST_CORE1_DBG 9
112 #define SRST_CORE2_DBG 10
113 #define SRST_CORE3_DBG 11
114 #define SRST_TOPDBG 12
115 #define SRST_ACLK_CORE 13
119 #define SRST_CPUSYS_H 18
120 #define SRST_BUSSYS_H 19
121 #define SRST_SPDIF 20
122 #define SRST_INTMEM 21
124 #define SRST_OTG_ADP 23
128 #define SRST_ACODEC_P 27
129 #define SRST_DFIMON 28
131 #define SRST_EFUSE1024 30
132 #define SRST_EFUSE256 31
134 #define SRST_GPIO0 32
135 #define SRST_GPIO1 33
136 #define SRST_GPIO2 34
137 #define SRST_GPIO3 35
138 #define SRST_PERIPH_NOC_A 36
139 #define SRST_PERIPH_NOC_BUS_H 37
140 #define SRST_PERIPH_NOC_P 38
141 #define SRST_UART0 39
142 #define SRST_UART1 40
143 #define SRST_UART2 41
144 #define SRST_PHYNOC 42
151 #define SRST_A53_GIC 49
153 #define SRST_DAP_NOC 52
154 #define SRST_CRYPTO 53
158 #define SRST_PERIPH_NOC_H 58
159 #define SRST_MACPHY 63
162 #define SRST_NANDC 68
163 #define SRST_USBOTG 69
165 #define SRST_USBHOST0 71
166 #define SRST_HOST_CTRL0 72
167 #define SRST_USBHOST1 73
168 #define SRST_HOST_CTRL1 74
169 #define SRST_USBHOST2 75
170 #define SRST_HOST_CTRL2 76
171 #define SRST_USBPOR0 77
172 #define SRST_USBPOR1 78
173 #define SRST_DDRMSCH 79
175 #define SRST_SMART_CARD 80
176 #define SRST_SDMMC 81
180 #define SRST_TSP_H 85
182 #define SRST_TSADC 87
183 #define SRST_DDRPHY 88
184 #define SRST_DDRPHY_P 89
185 #define SRST_DDRCTRL 90
186 #define SRST_DDRCTRL_P 91
187 #define SRST_HOST0_ECHI 92
188 #define SRST_HOST1_ECHI 93
189 #define SRST_HOST2_ECHI 94
190 #define SRST_VOP_NOC_A 95
192 #define SRST_HDMI_P 96
193 #define SRST_VIO_ARBI_H 97
194 #define SRST_IEP_NOC_A 98
195 #define SRST_VIO_NOC_H 99
196 #define SRST_VOP_A 100
197 #define SRST_VOP_H 101
198 #define SRST_VOP_D 102
199 #define SRST_UTMI0 103
200 #define SRST_UTMI1 104
201 #define SRST_UTMI2 105
202 #define SRST_UTMI3 106
204 #define SRST_RGA_NOC_A 108
205 #define SRST_RGA_A 109
206 #define SRST_RGA_H 110
207 #define SRST_HDCP_A 111
209 #define SRST_VPU_A 112
210 #define SRST_VPU_H 113
211 #define SRST_VPU_NOC_A 116
212 #define SRST_VPU_NOC_H 117
213 #define SRST_RKVDEC_A 118
214 #define SRST_RKVDEC_NOC_A 119
215 #define SRST_RKVDEC_H 120
216 #define SRST_RKVDEC_NOC_H 121
217 #define SRST_RKVDEC_CORE 122
218 #define SRST_RKVDEC_CABAC 123
219 #define SRST_IEP_A 124
220 #define SRST_IEP_H 125
221 #define SRST_GPU_A 126
222 #define SRST_GPU_NOC_A 127
224 #define SRST_CORE_DBG 128
225 #define SRST_DBG_P 129
226 #define SRST_TIMER0 130
227 #define SRST_TIMER1 131
228 #define SRST_TIMER2 132
229 #define SRST_TIMER3 133
230 #define SRST_TIMER4 134
231 #define SRST_TIMER5 135
232 #define SRST_VIO_H2P 136
233 #define SRST_HDMIPHY 139
234 #define SRST_VDAC 140
235 #define SRST_TIMER_6CH_P 141