2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
9 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
11 /* core clocks from */
20 /* sclk gates (special clocks) */
28 #define SCLK_SARADC 71
38 #define SCLK_OTGPHY0 81
39 #define SCLK_OTGPHY1 82
41 #define SCLK_TIMER0 84
42 #define SCLK_TIMER1 85
43 #define SCLK_TIMER2 86
44 #define SCLK_TIMER3 87
45 #define SCLK_TIMER4 88
46 #define SCLK_TIMER5 89
47 #define SCLK_TIMER6 90
52 #define DCLK_LCDC0 190
53 #define DCLK_LCDC1 191
59 #define ACLK_LCDC0 195
60 #define ACLK_LCDC1 196
73 #define PCLK_TIMER0 322
74 #define PCLK_TIMER1 323
75 #define PCLK_TIMER2 324
76 #define PCLK_TIMER3 325
77 #define PCLK_PWM01 326
78 #define PCLK_PWM23 327
81 #define PCLK_SARADC 330
83 #define PCLK_UART0 332
84 #define PCLK_UART1 333
85 #define PCLK_UART2 334
86 #define PCLK_UART3 335
92 #define PCLK_GPIO0 341
93 #define PCLK_GPIO1 342
94 #define PCLK_GPIO2 343
95 #define PCLK_GPIO3 344
96 #define PCLK_GPIO4 345
97 #define PCLK_GPIO6 346
98 #define PCLK_EFUSE 347
100 #define PCLK_TSADC 349
102 #define PCLK_PERI 351
103 #define PCLK_DDRUPCTL 352
104 #define PCLK_PUBL 353
107 #define HCLK_SDMMC 448
108 #define HCLK_SDIO 449
109 #define HCLK_EMMC 450
110 #define HCLK_OTG0 451
111 #define HCLK_EMAC 452
112 #define HCLK_SPDIF 453
113 #define HCLK_I2S0 454
114 #define HCLK_I2S1 455
115 #define HCLK_I2S2 456
116 #define HCLK_OTG1 457
117 #define HCLK_HSIC 458
118 #define HCLK_HSADC 459
119 #define HCLK_PIDF 460
120 #define HCLK_LCDC0 461
121 #define HCLK_LCDC1 462
123 #define HCLK_CIF0 464
126 #define HCLK_NANDC0 467
128 #define HCLK_PERI 469
130 #define CLK_NR_CLKS (HCLK_PERI + 1)
132 /* soft-reset indices */
136 #define SRST_MCORE_DBG 7
137 #define SRST_CORE0_DBG 8
138 #define SRST_CORE1_DBG 9
139 #define SRST_CORE0_WDT 12
140 #define SRST_CORE1_WDT 13
141 #define SRST_STRC_SYS 14
144 #define SRST_CPU_AHB 17
145 #define SRST_AHB2APB 19
147 #define SRST_INTMEM 21
149 #define SRST_SPDIF 26
150 #define SRST_TIMER0 27
151 #define SRST_TIMER1 28
152 #define SRST_EFUSE 30
154 #define SRST_GPIO0 32
155 #define SRST_GPIO1 33
156 #define SRST_GPIO2 34
157 #define SRST_GPIO3 35
159 #define SRST_UART0 39
160 #define SRST_UART1 40
161 #define SRST_UART2 41
162 #define SRST_UART3 42
171 #define SRST_DAP_PO 50
173 #define SRST_DAP_SYS 52
174 #define SRST_TPIU_ATB 53
175 #define SRST_PMU_APB 54
178 #define SRST_PERI_AXI 57
179 #define SRST_PERI_AHB 58
180 #define SRST_PERI_APB 59
181 #define SRST_PERI_NIU 60
182 #define SRST_CPU_PERI 61
183 #define SRST_EMEM_PERI 62
184 #define SRST_USB_PERI 63
189 #define SRST_NANC0 68
190 #define SRST_USBOTG0 69
191 #define SRST_USBPHY0 70
192 #define SRST_OTGC0 71
193 #define SRST_USBOTG1 72
194 #define SRST_USBPHY1 73
195 #define SRST_OTGC1 74
196 #define SRST_HSADC 76
197 #define SRST_PIDFILTER 77
198 #define SRST_DDR_MSCH 79
201 #define SRST_SDMMC 81
207 #define SRST_SARADC 87
208 #define SRST_DDRPHY 88
209 #define SRST_DDRPHY_APB 89
210 #define SRST_DDRCTL 90
211 #define SRST_DDRCTL_APB 91
212 #define SRST_DDRPUB 93
214 #define SRST_VIO0_AXI 98
215 #define SRST_VIO0_AHB 99
216 #define SRST_LCDC0_AXI 100
217 #define SRST_LCDC0_AHB 101
218 #define SRST_LCDC0_DCLK 102
219 #define SRST_LCDC1_AXI 103
220 #define SRST_LCDC1_AHB 104
221 #define SRST_LCDC1_DCLK 105
222 #define SRST_IPP_AXI 106
223 #define SRST_IPP_AHB 107
224 #define SRST_RGA_AXI 108
225 #define SRST_RGA_AHB 109
226 #define SRST_CIF0 110
228 #define SRST_VCODEC_AXI 112
229 #define SRST_VCODEC_AHB 113
230 #define SRST_VIO1_AXI 114
231 #define SRST_VCODEC_CPU 115
232 #define SRST_VCODEC_NIU 116
234 #define SRST_GPU_NIU 122
235 #define SRST_TFUN_ATB 125
236 #define SRST_TFUN_APB 126
237 #define SRST_CTI4_APB 127
239 #define SRST_TPIU_APB 128
240 #define SRST_TRACE 129
241 #define SRST_CORE_DBG 130
242 #define SRST_DBG_APB 131
243 #define SRST_CTI0 132
244 #define SRST_CTI0_APB 133
245 #define SRST_CTI1 134
246 #define SRST_CTI1_APB 135
247 #define SRST_PTM_CORE0 136
248 #define SRST_PTM_CORE1 137
249 #define SRST_PTM0 138
250 #define SRST_PTM0_ATB 139
251 #define SRST_PTM1 140
252 #define SRST_PTM1_ATB 141