1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
15 /* sclk gates (special clocks) */
27 #define SCLK_TIMER0 85
28 #define SCLK_TIMER1 86
29 #define SCLK_TIMER2 87
30 #define SCLK_TIMER3 88
31 #define SCLK_SARADC 91
32 #define SCLK_OTGPHY0 93
36 #define SCLK_I2S_OUT 113
37 #define SCLK_SDMMC_DRV 114
38 #define SCLK_SDIO_DRV 115
39 #define SCLK_EMMC_DRV 117
40 #define SCLK_SDMMC_SAMPLE 118
41 #define SCLK_SDIO_SAMPLE 119
42 #define SCLK_EMMC_SAMPLE 121
43 #define SCLK_PVTM_CORE 123
44 #define SCLK_PVTM_GPU 124
45 #define SCLK_PVTM_VIDEO 125
47 #define SCLK_MACREF 152
53 #define ACLK_DMAC2 194
56 #define ACLK_VCODEC 208
61 #define PCLK_SARADC 318
62 #define PCLK_GPIO0 320
63 #define PCLK_GPIO1 321
64 #define PCLK_GPIO2 322
65 #define PCLK_GPIO3 323
72 #define PCLK_UART0 341
73 #define PCLK_UART1 342
74 #define PCLK_UART2 343
76 #define PCLK_TIMER 353
80 #define PCLK_DDRUPCTL 364
86 #define HCLK_NANDC 453
87 #define HCLK_SDMMC 456
93 #define HCLK_VIO_BUS 472
94 #define HCLK_VCODEC 476
98 #define CLK_NR_CLKS (HCLK_PERI + 1)
100 /* soft-reset indices */
103 #define SRST_CORE0_DBG 4
104 #define SRST_CORE1_DBG 5
105 #define SRST_CORE0_POR 8
106 #define SRST_CORE1_POR 9
108 #define SRST_TOPDBG 13
109 #define SRST_STRC_SYS_A 14
110 #define SRST_PD_CORE_NIU 15
112 #define SRST_TIMER2 16
113 #define SRST_CPUSYS_H 17
114 #define SRST_AHB2APB_H 19
115 #define SRST_TIMER3 20
116 #define SRST_INTMEM 21
118 #define SRST_PERI_NIU 23
120 #define SRST_DDR_PLL 25
121 #define SRST_GPU_DLL 26
122 #define SRST_TIMER0 27
123 #define SRST_TIMER1 28
124 #define SRST_CORE_DLL 29
125 #define SRST_EFUSE_P 30
126 #define SRST_ACODEC_P 31
128 #define SRST_GPIO0 32
129 #define SRST_GPIO1 33
130 #define SRST_GPIO2 34
131 #define SRST_UART0 39
132 #define SRST_UART1 40
133 #define SRST_UART2 41
141 #define SRST_DAP_SYS 52
143 #define SRST_PERIPHSYS_A 57
144 #define SRST_PERIPHSYS_H 58
145 #define SRST_PERIPHSYS_P 59
146 #define SRST_CPU_PERI 61
147 #define SRST_EMEM_PERI 62
148 #define SRST_USB_PERI 63
152 #define SRST_NANDC 68
153 #define SRST_USBOTG0 69
154 #define SRST_OTGC0 71
155 #define SRST_USBOTG1 72
156 #define SRST_OTGC1 74
157 #define SRST_DDRMSCH 79
164 #define SRST_SARADC 87
165 #define SRST_DDRPHY 88
166 #define SRST_DDRPHY_P 89
167 #define SRST_DDRCTRL 90
168 #define SRST_DDRCTRL_P 91
170 #define SRST_HDMI_P 96
171 #define SRST_VIO_BUS_H 99
172 #define SRST_UTMI0 103
173 #define SRST_UTMI1 104
174 #define SRST_USBPOR 105
176 #define SRST_VCODEC_A 112
177 #define SRST_VCODEC_H 113
178 #define SRST_VIO1_A 114
179 #define SRST_HEVC 115
180 #define SRST_VCODEC_NIU_A 116
181 #define SRST_LCDC1_A 117
182 #define SRST_LCDC1_H 118
183 #define SRST_LCDC1_D 119
185 #define SRST_GPU_NIU_A 122
187 #define SRST_DBG_P 131