2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
16 /* sclk gates (special clocks) */
28 #define SCLK_TIMER0 85
29 #define SCLK_TIMER1 86
30 #define SCLK_TIMER2 87
31 #define SCLK_TIMER3 88
32 #define SCLK_SARADC 91
33 #define SCLK_OTGPHY0 93
37 #define SCLK_I2S_OUT 113
38 #define SCLK_SDMMC_DRV 114
39 #define SCLK_SDIO_DRV 115
40 #define SCLK_EMMC_DRV 117
41 #define SCLK_SDMMC_SAMPLE 118
42 #define SCLK_SDIO_SAMPLE 119
43 #define SCLK_EMMC_SAMPLE 121
44 #define SCLK_PVTM_CORE 123
45 #define SCLK_PVTM_GPU 124
46 #define SCLK_PVTM_VIDEO 125
48 #define SCLK_MACREF 152
54 #define ACLK_DMAC2 194
57 #define ACLK_VCODEC 208
62 #define PCLK_SARADC 318
63 #define PCLK_GPIO0 320
64 #define PCLK_GPIO1 321
65 #define PCLK_GPIO2 322
66 #define PCLK_GPIO3 323
73 #define PCLK_UART0 341
74 #define PCLK_UART1 342
75 #define PCLK_UART2 343
77 #define PCLK_TIMER 353
81 #define PCLK_DDRUPCTL 364
87 #define HCLK_NANDC 453
88 #define HCLK_SDMMC 456
94 #define HCLK_VIO_BUS 472
95 #define HCLK_VCODEC 476
99 #define CLK_NR_CLKS (HCLK_PERI + 1)
101 /* soft-reset indices */
104 #define SRST_CORE0_DBG 4
105 #define SRST_CORE1_DBG 5
106 #define SRST_CORE0_POR 8
107 #define SRST_CORE1_POR 9
109 #define SRST_TOPDBG 13
110 #define SRST_STRC_SYS_A 14
111 #define SRST_PD_CORE_NIU 15
113 #define SRST_TIMER2 16
114 #define SRST_CPUSYS_H 17
115 #define SRST_AHB2APB_H 19
116 #define SRST_TIMER3 20
117 #define SRST_INTMEM 21
119 #define SRST_PERI_NIU 23
121 #define SRST_DDR_PLL 25
122 #define SRST_GPU_DLL 26
123 #define SRST_TIMER0 27
124 #define SRST_TIMER1 28
125 #define SRST_CORE_DLL 29
126 #define SRST_EFUSE_P 30
127 #define SRST_ACODEC_P 31
129 #define SRST_GPIO0 32
130 #define SRST_GPIO1 33
131 #define SRST_GPIO2 34
132 #define SRST_UART0 39
133 #define SRST_UART1 40
134 #define SRST_UART2 41
142 #define SRST_DAP_SYS 52
144 #define SRST_PERIPHSYS_A 57
145 #define SRST_PERIPHSYS_H 58
146 #define SRST_PERIPHSYS_P 59
147 #define SRST_CPU_PERI 61
148 #define SRST_EMEM_PERI 62
149 #define SRST_USB_PERI 63
153 #define SRST_NANDC 68
154 #define SRST_USBOTG0 69
155 #define SRST_OTGC0 71
156 #define SRST_USBOTG1 72
157 #define SRST_OTGC1 74
158 #define SRST_DDRMSCH 79
165 #define SRST_SARADC 87
166 #define SRST_DDRPHY 88
167 #define SRST_DDRPHY_P 89
168 #define SRST_DDRCTRL 90
169 #define SRST_DDRCTRL_P 91
171 #define SRST_HDMI_P 96
172 #define SRST_VIO_BUS_H 99
173 #define SRST_UTMI0 103
174 #define SRST_UTMI1 104
175 #define SRST_USBPOR 105
177 #define SRST_VCODEC_A 112
178 #define SRST_VCODEC_H 113
179 #define SRST_VIO1_A 114
180 #define SRST_HEVC 115
181 #define SRST_VCODEC_NIU_A 116
182 #define SRST_LCDC1_A 117
183 #define SRST_LCDC1_H 118
184 #define SRST_LCDC1_D 119
186 #define SRST_GPU_NIU_A 122
188 #define SRST_DBG_P 131