1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
16 /* sclk gates (special clocks) */
28 #define SCLK_TIMER0 85
29 #define SCLK_TIMER1 86
30 #define SCLK_TIMER2 87
31 #define SCLK_TIMER3 88
32 #define SCLK_OTGPHY0 93
36 #define SCLK_I2S_OUT 113
37 #define SCLK_SDMMC_DRV 114
38 #define SCLK_SDIO_DRV 115
39 #define SCLK_EMMC_DRV 117
40 #define SCLK_SDMMC_SAMPLE 118
41 #define SCLK_SDIO_SAMPLE 119
42 #define SCLK_EMMC_SAMPLE 121
43 #define SCLK_PVTM_CORE 123
44 #define SCLK_PVTM_GPU 124
45 #define SCLK_PVTM_VIDEO 125
47 #define SCLK_MACREF 152
53 #define ACLK_DMAC2 194
56 #define ACLK_VCODEC 208
61 #define PCLK_GPIO0 320
62 #define PCLK_GPIO1 321
63 #define PCLK_GPIO2 322
69 #define PCLK_UART0 341
70 #define PCLK_UART1 342
71 #define PCLK_UART2 343
73 #define PCLK_TIMER 353
77 #define PCLK_DDRUPCTL 364
83 #define HCLK_NANDC 453
84 #define HCLK_SDMMC 456
90 #define HCLK_VIO_BUS 472
91 #define HCLK_VCODEC 476
95 #define CLK_NR_CLKS (HCLK_PERI + 1)
97 /* soft-reset indices */
100 #define SRST_CORE0_DBG 4
101 #define SRST_CORE1_DBG 5
102 #define SRST_CORE0_POR 8
103 #define SRST_CORE1_POR 9
105 #define SRST_TOPDBG 13
106 #define SRST_STRC_SYS_A 14
107 #define SRST_PD_CORE_NIU 15
109 #define SRST_TIMER2 16
110 #define SRST_CPUSYS_H 17
111 #define SRST_AHB2APB_H 19
112 #define SRST_TIMER3 20
113 #define SRST_INTMEM 21
115 #define SRST_PERI_NIU 23
117 #define SRST_DDR_PLL 25
118 #define SRST_GPU_DLL 26
119 #define SRST_TIMER0 27
120 #define SRST_TIMER1 28
121 #define SRST_CORE_DLL 29
122 #define SRST_EFUSE_P 30
123 #define SRST_ACODEC_P 31
125 #define SRST_GPIO0 32
126 #define SRST_GPIO1 33
127 #define SRST_GPIO2 34
128 #define SRST_UART0 39
129 #define SRST_UART1 40
130 #define SRST_UART2 41
138 #define SRST_DAP_SYS 52
140 #define SRST_PERIPHSYS_A 57
141 #define SRST_PERIPHSYS_H 58
142 #define SRST_PERIPHSYS_P 59
143 #define SRST_CPU_PERI 61
144 #define SRST_EMEM_PERI 62
145 #define SRST_USB_PERI 63
149 #define SRST_NANDC 68
150 #define SRST_USBOTG0 69
151 #define SRST_OTGC0 71
152 #define SRST_USBOTG1 72
153 #define SRST_OTGC1 74
154 #define SRST_DDRMSCH 79
161 #define SRST_DDRPHY 88
162 #define SRST_DDRPHY_P 89
163 #define SRST_DDRCTRL 90
164 #define SRST_DDRCTRL_P 91
166 #define SRST_HDMI_P 96
167 #define SRST_VIO_BUS_H 99
168 #define SRST_UTMI0 103
169 #define SRST_UTMI1 104
170 #define SRST_USBPOR 105
172 #define SRST_VCODEC_A 112
173 #define SRST_VCODEC_H 113
174 #define SRST_VIO1_A 114
175 #define SRST_HEVC 115
176 #define SRST_VCODEC_NIU_A 116
177 #define SRST_LCDC1_A 117
178 #define SRST_LCDC1_H 118
179 #define SRST_LCDC1_D 119
181 #define SRST_GPU_NIU_A 122
183 #define SRST_DBG_P 131