1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018 BayLibre, SAS
4 * Copyright (c) 2018 MediaTek Inc.
5 * Author: Fabien Parent <fparent@baylibre.com>
8 #ifndef _DT_BINDINGS_CLK_MT8516_H
9 #define _DT_BINDINGS_CLK_MT8516_H
14 #define CLK_APMIXED_ARMPLL 0
15 #define CLK_APMIXED_MAINPLL 1
16 #define CLK_APMIXED_UNIVPLL 2
17 #define CLK_APMIXED_MMPLL 3
18 #define CLK_APMIXED_APLL1 4
19 #define CLK_APMIXED_APLL2 5
20 #define CLK_APMIXED_NR_CLK 6
24 #define CLK_TOP_CLK_NULL 0
25 #define CLK_TOP_I2S_INFRA_BCK 1
26 #define CLK_TOP_MEMPLL 2
27 #define CLK_TOP_DMPLL 3
28 #define CLK_TOP_MAINPLL_D2 4
29 #define CLK_TOP_MAINPLL_D4 5
30 #define CLK_TOP_MAINPLL_D8 6
31 #define CLK_TOP_MAINPLL_D16 7
32 #define CLK_TOP_MAINPLL_D11 8
33 #define CLK_TOP_MAINPLL_D22 9
34 #define CLK_TOP_MAINPLL_D3 10
35 #define CLK_TOP_MAINPLL_D6 11
36 #define CLK_TOP_MAINPLL_D12 12
37 #define CLK_TOP_MAINPLL_D5 13
38 #define CLK_TOP_MAINPLL_D10 14
39 #define CLK_TOP_MAINPLL_D20 15
40 #define CLK_TOP_MAINPLL_D40 16
41 #define CLK_TOP_MAINPLL_D7 17
42 #define CLK_TOP_MAINPLL_D14 18
43 #define CLK_TOP_UNIVPLL_D2 19
44 #define CLK_TOP_UNIVPLL_D4 20
45 #define CLK_TOP_UNIVPLL_D8 21
46 #define CLK_TOP_UNIVPLL_D16 22
47 #define CLK_TOP_UNIVPLL_D3 23
48 #define CLK_TOP_UNIVPLL_D6 24
49 #define CLK_TOP_UNIVPLL_D12 25
50 #define CLK_TOP_UNIVPLL_D24 26
51 #define CLK_TOP_UNIVPLL_D5 27
52 #define CLK_TOP_UNIVPLL_D20 28
53 #define CLK_TOP_MMPLL380M 29
54 #define CLK_TOP_MMPLL_D2 30
55 #define CLK_TOP_MMPLL_200M 31
56 #define CLK_TOP_USB_PHY48M 32
57 #define CLK_TOP_APLL1 33
58 #define CLK_TOP_APLL1_D2 34
59 #define CLK_TOP_APLL1_D4 35
60 #define CLK_TOP_APLL1_D8 36
61 #define CLK_TOP_APLL2 37
62 #define CLK_TOP_APLL2_D2 38
63 #define CLK_TOP_APLL2_D4 39
64 #define CLK_TOP_APLL2_D8 40
65 #define CLK_TOP_CLK26M 41
66 #define CLK_TOP_CLK26M_D2 42
67 #define CLK_TOP_AHB_INFRA_D2 43
68 #define CLK_TOP_NFI1X 44
69 #define CLK_TOP_ETH_D2 45
70 #define CLK_TOP_UART0_SEL 46
71 #define CLK_TOP_GFMUX_EMI1X_SEL 47
72 #define CLK_TOP_EMI_DDRPHY_SEL 48
73 #define CLK_TOP_AHB_INFRA_SEL 49
74 #define CLK_TOP_CSW_MUX_MFG_SEL 50
75 #define CLK_TOP_MSDC0_SEL 51
76 #define CLK_TOP_PWM_MM_SEL 52
77 #define CLK_TOP_UART1_SEL 53
78 #define CLK_TOP_MSDC1_SEL 54
79 #define CLK_TOP_SPM_52M_SEL 55
80 #define CLK_TOP_PMICSPI_SEL 56
81 #define CLK_TOP_QAXI_AUD26M_SEL 57
82 #define CLK_TOP_AUD_INTBUS_SEL 58
83 #define CLK_TOP_NFI2X_PAD_SEL 59
84 #define CLK_TOP_NFI1X_PAD_SEL 60
85 #define CLK_TOP_MFG_MM_SEL 61
86 #define CLK_TOP_DDRPHYCFG_SEL 62
87 #define CLK_TOP_USB_78M_SEL 63
88 #define CLK_TOP_SPINOR_SEL 64
89 #define CLK_TOP_MSDC2_SEL 65
90 #define CLK_TOP_ETH_SEL 66
91 #define CLK_TOP_AXI_MFG_IN_SEL 67
92 #define CLK_TOP_SLOW_MFG_SEL 68
93 #define CLK_TOP_AUD1_SEL 69
94 #define CLK_TOP_AUD2_SEL 70
95 #define CLK_TOP_AUD_ENGEN1_SEL 71
96 #define CLK_TOP_AUD_ENGEN2_SEL 72
97 #define CLK_TOP_I2C_SEL 73
98 #define CLK_TOP_AUD_I2S0_M_SEL 74
99 #define CLK_TOP_AUD_I2S1_M_SEL 75
100 #define CLK_TOP_AUD_I2S2_M_SEL 76
101 #define CLK_TOP_AUD_I2S3_M_SEL 77
102 #define CLK_TOP_AUD_I2S4_M_SEL 78
103 #define CLK_TOP_AUD_I2S5_M_SEL 79
104 #define CLK_TOP_AUD_SPDIF_B_SEL 80
105 #define CLK_TOP_PWM_SEL 81
106 #define CLK_TOP_SPI_SEL 82
107 #define CLK_TOP_AUD_SPDIFIN_SEL 83
108 #define CLK_TOP_UART2_SEL 84
109 #define CLK_TOP_BSI_SEL 85
110 #define CLK_TOP_DBG_ATCLK_SEL 86
111 #define CLK_TOP_CSW_NFIECC_SEL 87
112 #define CLK_TOP_NFIECC_SEL 88
113 #define CLK_TOP_APLL12_CK_DIV0 89
114 #define CLK_TOP_APLL12_CK_DIV1 90
115 #define CLK_TOP_APLL12_CK_DIV2 91
116 #define CLK_TOP_APLL12_CK_DIV3 92
117 #define CLK_TOP_APLL12_CK_DIV4 93
118 #define CLK_TOP_APLL12_CK_DIV4B 94
119 #define CLK_TOP_APLL12_CK_DIV5 95
120 #define CLK_TOP_APLL12_CK_DIV5B 96
121 #define CLK_TOP_APLL12_CK_DIV6 97
122 #define CLK_TOP_NR_CLK 98
125 #define CLK_TOP_PWM_MM 0
126 #define CLK_TOP_MFG_MM 1
127 #define CLK_TOP_SPM_52M 2
128 #define CLK_TOP_THEM 3
129 #define CLK_TOP_APDMA 4
130 #define CLK_TOP_I2C0 5
131 #define CLK_TOP_I2C1 6
132 #define CLK_TOP_AUXADC1 7
133 #define CLK_TOP_NFI 8
134 #define CLK_TOP_NFIECC 9
135 #define CLK_TOP_DEBUGSYS 10
136 #define CLK_TOP_PWM 11
137 #define CLK_TOP_UART0 12
138 #define CLK_TOP_UART1 13
139 #define CLK_TOP_BTIF 14
140 #define CLK_TOP_USB 15
141 #define CLK_TOP_FLASHIF_26M 16
142 #define CLK_TOP_AUXADC2 17
143 #define CLK_TOP_I2C2 18
144 #define CLK_TOP_MSDC0 19
145 #define CLK_TOP_MSDC1 20
146 #define CLK_TOP_NFI2X 21
147 #define CLK_TOP_PMICWRAP_AP 22
148 #define CLK_TOP_SEJ 23
149 #define CLK_TOP_MEMSLP_DLYER 24
150 #define CLK_TOP_SPI 25
151 #define CLK_TOP_APXGPT 26
152 #define CLK_TOP_AUDIO 27
153 #define CLK_TOP_PMICWRAP_MD 28
154 #define CLK_TOP_PMICWRAP_CONN 29
155 #define CLK_TOP_PMICWRAP_26M 30
156 #define CLK_TOP_AUX_ADC 31
157 #define CLK_TOP_AUX_TP 32
158 #define CLK_TOP_MSDC2 33
159 #define CLK_TOP_RBIST 34
160 #define CLK_TOP_NFI_BUS 35
161 #define CLK_TOP_GCE 36
162 #define CLK_TOP_TRNG 37
163 #define CLK_TOP_SEJ_13M 38
164 #define CLK_TOP_AES 39
165 #define CLK_TOP_PWM_B 40
166 #define CLK_TOP_PWM1_FB 41
167 #define CLK_TOP_PWM2_FB 42
168 #define CLK_TOP_PWM3_FB 43
169 #define CLK_TOP_PWM4_FB 44
170 #define CLK_TOP_PWM5_FB 45
171 #define CLK_TOP_USB_1P 46
172 #define CLK_TOP_FLASHIF_FREERUN 47
173 #define CLK_TOP_66M_ETH 48
174 #define CLK_TOP_133M_ETH 49
175 #define CLK_TOP_FETH_25M 50
176 #define CLK_TOP_FETH_50M 51
177 #define CLK_TOP_FLASHIF_AXI 52
178 #define CLK_TOP_USBIF 53
179 #define CLK_TOP_UART2 54
180 #define CLK_TOP_BSI 55
181 #define CLK_TOP_MSDC0_INFRA 56
182 #define CLK_TOP_MSDC1_INFRA 57
183 #define CLK_TOP_MSDC2_INFRA 58
184 #define CLK_TOP_USB_78M 59
185 #define CLK_TOP_RG_SPINOR 60
186 #define CLK_TOP_RG_MSDC2 61
187 #define CLK_TOP_RG_ETH 62
188 #define CLK_TOP_RG_AXI_MFG 63
189 #define CLK_TOP_RG_SLOW_MFG 64
190 #define CLK_TOP_RG_AUD1 65
191 #define CLK_TOP_RG_AUD2 66
192 #define CLK_TOP_RG_AUD_ENGEN1 67
193 #define CLK_TOP_RG_AUD_ENGEN2 68
194 #define CLK_TOP_RG_I2C 69
195 #define CLK_TOP_RG_PWM_INFRA 70
196 #define CLK_TOP_RG_AUD_SPDIF_IN 71
197 #define CLK_TOP_RG_UART2 72
198 #define CLK_TOP_RG_BSI 73
199 #define CLK_TOP_RG_DBG_ATCLK 74
200 #define CLK_TOP_RG_NFIECC 75
201 #define CLK_TOP_RG_APLL1_D2_EN 76
202 #define CLK_TOP_RG_APLL1_D4_EN 77
203 #define CLK_TOP_RG_APLL1_D8_EN 78
204 #define CLK_TOP_RG_APLL2_D2_EN 79
205 #define CLK_TOP_RG_APLL2_D4_EN 80
206 #define CLK_TOP_RG_APLL2_D8_EN 81
207 #define CLK_TOP_APLL12_DIV0 82
208 #define CLK_TOP_APLL12_DIV1 83
209 #define CLK_TOP_APLL12_DIV2 84
210 #define CLK_TOP_APLL12_DIV3 85
211 #define CLK_TOP_APLL12_DIV4 86
212 #define CLK_TOP_APLL12_DIV4B 87
213 #define CLK_TOP_APLL12_DIV5 88
214 #define CLK_TOP_APLL12_DIV5B 89
215 #define CLK_TOP_APLL12_DIV6 90
219 #define CLK_IFR_MUX1_SEL 0
220 #define CLK_IFR_ETH_25M_SEL 1
221 #define CLK_IFR_I2C0_SEL 2
222 #define CLK_IFR_I2C1_SEL 3
223 #define CLK_IFR_I2C2_SEL 4
224 #define CLK_IFR_NR_CLK 5
228 #define CLK_AUD_AFE 0
229 #define CLK_AUD_I2S 1
230 #define CLK_AUD_22M 2
231 #define CLK_AUD_24M 3
232 #define CLK_AUD_INTDIR 4
233 #define CLK_AUD_APLL2_TUNER 5
234 #define CLK_AUD_APLL_TUNER 6
235 #define CLK_AUD_HDMI 7
236 #define CLK_AUD_SPDF 8
237 #define CLK_AUD_ADC 9
238 #define CLK_AUD_DAC 10
239 #define CLK_AUD_DAC_PREDIS 11
240 #define CLK_AUD_TML 12
241 #define CLK_AUD_NR_CLK 13
245 #define CLK_MFG_BAXI 0
246 #define CLK_MFG_BMEM 1
247 #define CLK_MFG_BG3D 2
248 #define CLK_MFG_B26M 3
249 #define CLK_MFG_NR_CLK 4
251 #endif /* _DT_BINDINGS_CLK_MT8516_H */