1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
7 #define __DT_BINDINGS_CLOCK_IMX8QM_H
9 #define IMX8QM_CLK_DUMMY 0
11 #define IMX8QM_A53_DIV 1
12 #define IMX8QM_A53_CLK 2
13 #define IMX8QM_A72_DIV 3
14 #define IMX8QM_A72_CLK 4
17 #define IMX8QM_SC_I2C_DIV 5
18 #define IMX8QM_SC_I2C_CLK 6
19 #define IMX8QM_SC_PID0_DIV 7
20 #define IMX8QM_SC_PID0_CLK 8
21 #define IMX8QM_SC_PIT_DIV 9
22 #define IMX8QM_SC_PIT_CLK 10
23 #define IMX8QM_SC_TPM_DIV 11
24 #define IMX8QM_SC_TPM_CLK 12
25 #define IMX8QM_SC_UART_DIV 13
26 #define IMX8QM_SC_UART_CLK 14
29 #define IMX8QM_PWM0_DIV 15
30 #define IMX8QM_PWM0_CLK 16
31 #define IMX8QM_PWM1_DIV 17
32 #define IMX8QM_PWM1_CLK 18
33 #define IMX8QM_PWM2_DIV 19
34 #define IMX8QM_PWM2_CLK 20
35 #define IMX8QM_PWM3_DIV 21
36 #define IMX8QM_PWM3_CLK 22
37 #define IMX8QM_PWM4_DIV 23
38 #define IMX8QM_PWM4_CLK 24
39 #define IMX8QM_PWM5_DIV 26
40 #define IMX8QM_PWM5_CLK 27
41 #define IMX8QM_PWM6_DIV 28
42 #define IMX8QM_PWM6_CLK 29
43 #define IMX8QM_PWM7_DIV 30
44 #define IMX8QM_PWM7_CLK 31
45 #define IMX8QM_FSPI0_DIV 32
46 #define IMX8QM_FSPI0_CLK 33
47 #define IMX8QM_FSPI1_DIV 34
48 #define IMX8QM_FSPI1_CLK 35
49 #define IMX8QM_GPT0_DIV 36
50 #define IMX8QM_GPT0_CLK 37
51 #define IMX8QM_GPT1_DIV 38
52 #define IMX8QM_GPT1_CLK 39
53 #define IMX8QM_GPT2_DIV 40
54 #define IMX8QM_GPT2_CLK 41
55 #define IMX8QM_GPT3_DIV 42
56 #define IMX8QM_GPT3_CLK 43
57 #define IMX8QM_GPT4_DIV 44
58 #define IMX8QM_GPT4_CLK 45
61 #define IMX8QM_APBHDMA_CLK 46
62 #define IMX8QM_GPMI_APB_CLK 47
63 #define IMX8QM_GPMI_APB_BCH_CLK 48
64 #define IMX8QM_GPMI_BCH_IO_DIV 49
65 #define IMX8QM_GPMI_BCH_IO_CLK 50
66 #define IMX8QM_GPMI_BCH_DIV 51
67 #define IMX8QM_GPMI_BCH_CLK 52
68 #define IMX8QM_SDHC0_IPG_CLK 53
69 #define IMX8QM_SDHC0_DIV 54
70 #define IMX8QM_SDHC0_CLK 55
71 #define IMX8QM_SDHC1_IPG_CLK 56
72 #define IMX8QM_SDHC1_DIV 57
73 #define IMX8QM_SDHC1_CLK 58
74 #define IMX8QM_SDHC2_IPG_CLK 59
75 #define IMX8QM_SDHC2_DIV 60
76 #define IMX8QM_SDHC2_CLK 61
77 #define IMX8QM_USB2_OH_AHB_CLK 62
78 #define IMX8QM_USB2_OH_IPG_S_CLK 63
79 #define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64
80 #define IMX8QM_USB2_PHY_IPG_CLK 65
81 #define IMX8QM_USB3_IPG_CLK 66
82 #define IMX8QM_USB3_CORE_PCLK 67
83 #define IMX8QM_USB3_PHY_CLK 68
84 #define IMX8QM_USB3_ACLK_DIV 69
85 #define IMX8QM_USB3_ACLK 70
86 #define IMX8QM_USB3_BUS_DIV 71
87 #define IMX8QM_USB3_BUS_CLK 72
88 #define IMX8QM_USB3_LPM_DIV 73
89 #define IMX8QM_USB3_LPM_CLK 74
90 #define IMX8QM_ENET0_AHB_CLK 75
91 #define IMX8QM_ENET0_IPG_S_CLK 76
92 #define IMX8QM_ENET0_IPG_CLK 77
93 #define IMX8QM_ENET0_RGMII_DIV 78
94 #define IMX8QM_ENET0_RGMII_TX_CLK 79
95 #define IMX8QM_ENET0_ROOT_DIV 80
96 #define IMX8QM_ENET0_TX_CLK 81
97 #define IMX8QM_ENET0_ROOT_CLK 82
98 #define IMX8QM_ENET0_PTP_CLK 83
99 #define IMX8QM_ENET0_BYPASS_DIV 84
100 #define IMX8QM_ENET1_AHB_CLK 85
101 #define IMX8QM_ENET1_IPG_S_CLK 86
102 #define IMX8QM_ENET1_IPG_CLK 87
103 #define IMX8QM_ENET1_RGMII_DIV 88
104 #define IMX8QM_ENET1_RGMII_TX_CLK 89
105 #define IMX8QM_ENET1_ROOT_DIV 90
106 #define IMX8QM_ENET1_TX_CLK 91
107 #define IMX8QM_ENET1_ROOT_CLK 92
108 #define IMX8QM_ENET1_PTP_CLK 93
109 #define IMX8QM_ENET1_BYPASS_DIV 94
110 #define IMX8QM_MLB_CLK 95
111 #define IMX8QM_MLB_HCLK 96
112 #define IMX8QM_MLB_IPG_CLK 97
113 #define IMX8QM_EDMA_CLK 98
114 #define IMX8QM_EDMA_IPG_CLK 99
117 #define IMX8QM_SPI0_IPG_CLK 100
118 #define IMX8QM_SPI0_DIV 101
119 #define IMX8QM_SPI0_CLK 102
120 #define IMX8QM_SPI1_IPG_CLK 103
121 #define IMX8QM_SPI1_DIV 104
122 #define IMX8QM_SPI1_CLK 105
123 #define IMX8QM_SPI2_IPG_CLK 106
124 #define IMX8QM_SPI2_DIV 107
125 #define IMX8QM_SPI2_CLK 108
126 #define IMX8QM_SPI3_IPG_CLK 109
127 #define IMX8QM_SPI3_DIV 110
128 #define IMX8QM_SPI3_CLK 111
129 #define IMX8QM_UART0_IPG_CLK 112
130 #define IMX8QM_UART0_DIV 113
131 #define IMX8QM_UART0_CLK 114
132 #define IMX8QM_UART1_IPG_CLK 115
133 #define IMX8QM_UART1_DIV 116
134 #define IMX8QM_UART1_CLK 117
135 #define IMX8QM_UART2_IPG_CLK 118
136 #define IMX8QM_UART2_DIV 119
137 #define IMX8QM_UART2_CLK 120
138 #define IMX8QM_UART3_IPG_CLK 121
139 #define IMX8QM_UART3_DIV 122
140 #define IMX8QM_UART3_CLK 123
141 #define IMX8QM_UART4_IPG_CLK 124
142 #define IMX8QM_UART4_DIV 125
143 #define IMX8QM_EMVSIM0_IPG_CLK 126
144 #define IMX8QM_UART4_CLK 127
145 #define IMX8QM_EMVSIM0_DIV 128
146 #define IMX8QM_EMVSIM0_CLK 129
147 #define IMX8QM_EMVSIM1_IPG_CLK 130
148 #define IMX8QM_EMVSIM1_DIV 131
149 #define IMX8QM_EMVSIM1_CLK 132
150 #define IMX8QM_CAN0_IPG_CHI_CLK 133
151 #define IMX8QM_CAN0_IPG_CLK 134
152 #define IMX8QM_CAN0_DIV 135
153 #define IMX8QM_CAN0_CLK 136
154 #define IMX8QM_CAN1_IPG_CHI_CLK 137
155 #define IMX8QM_CAN1_IPG_CLK 138
156 #define IMX8QM_CAN1_DIV 139
157 #define IMX8QM_CAN1_CLK 140
158 #define IMX8QM_CAN2_IPG_CHI_CLK 141
159 #define IMX8QM_CAN2_IPG_CLK 142
160 #define IMX8QM_CAN2_DIV 143
161 #define IMX8QM_CAN2_CLK 144
162 #define IMX8QM_I2C0_IPG_CLK 145
163 #define IMX8QM_I2C0_DIV 146
164 #define IMX8QM_I2C0_CLK 147
165 #define IMX8QM_I2C1_IPG_CLK 148
166 #define IMX8QM_I2C1_DIV 149
167 #define IMX8QM_I2C1_CLK 150
168 #define IMX8QM_I2C2_IPG_CLK 151
169 #define IMX8QM_I2C2_DIV 152
170 #define IMX8QM_I2C2_CLK 153
171 #define IMX8QM_I2C3_IPG_CLK 154
172 #define IMX8QM_I2C3_DIV 155
173 #define IMX8QM_I2C3_CLK 156
174 #define IMX8QM_I2C4_IPG_CLK 157
175 #define IMX8QM_I2C4_DIV 158
176 #define IMX8QM_I2C4_CLK 159
177 #define IMX8QM_FTM0_IPG_CLK 160
178 #define IMX8QM_FTM0_DIV 161
179 #define IMX8QM_FTM0_CLK 162
180 #define IMX8QM_FTM1_IPG_CLK 163
181 #define IMX8QM_FTM1_DIV 164
182 #define IMX8QM_FTM1_CLK 165
183 #define IMX8QM_ADC0_IPG_CLK 166
184 #define IMX8QM_ADC0_DIV 167
185 #define IMX8QM_ADC0_CLK 168
186 #define IMX8QM_ADC1_IPG_CLK 169
187 #define IMX8QM_ADC1_DIV 170
188 #define IMX8QM_ADC1_CLK 171
191 #define IMX8QM_AUD_PLL0_DIV 172
192 #define IMX8QM_AUD_PLL0 173
193 #define IMX8QM_AUD_PLL1_DIV 174
194 #define IMX8QM_AUD_PLL1 175
195 #define IMX8QM_AUD_AMIX_IPG 182
196 #define IMX8QM_AUD_ESAI_0_IPG 183
197 #define IMX8QM_AUD_ESAI_1_IPG 184
198 #define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185
199 #define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186
200 #define IMX8QM_AUD_SAI_0_IPG 187
201 #define IMX8QM_AUD_SAI_0_IPG_S 188
202 #define IMX8QM_AUD_SAI_0_MCLK 189
203 #define IMX8QM_AUD_SAI_1_IPG 190
204 #define IMX8QM_AUD_SAI_1_IPG_S 191
205 #define IMX8QM_AUD_SAI_1_MCLK 192
206 #define IMX8QM_AUD_SAI_2_IPG 193
207 #define IMX8QM_AUD_SAI_2_IPG_S 194
208 #define IMX8QM_AUD_SAI_2_MCLK 195
209 #define IMX8QM_AUD_SAI_3_IPG 196
210 #define IMX8QM_AUD_SAI_3_IPG_S 197
211 #define IMX8QM_AUD_SAI_3_MCLK 198
212 #define IMX8QM_AUD_SAI_6_IPG 199
213 #define IMX8QM_AUD_SAI_6_IPG_S 200
214 #define IMX8QM_AUD_SAI_6_MCLK 201
215 #define IMX8QM_AUD_SAI_7_IPG 202
216 #define IMX8QM_AUD_SAI_7_IPG_S 203
217 #define IMX8QM_AUD_SAI_7_MCLK 204
218 #define IMX8QM_AUD_SAI_HDMIRX0_IPG 205
219 #define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206
220 #define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207
221 #define IMX8QM_AUD_SAI_HDMITX0_IPG 208
222 #define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209
223 #define IMX8QM_AUD_SAI_HDMITX0_MCLK 210
224 #define IMX8QM_AUD_MQS_IPG 211
225 #define IMX8QM_AUD_MQS_HMCLK 212
226 #define IMX8QM_AUD_GPT5_IPG_S 213
227 #define IMX8QM_AUD_GPT5_CLKIN 214
228 #define IMX8QM_AUD_GPT5_24M_CLK 215
229 #define IMX8QM_AUD_GPT6_IPG_S 216
230 #define IMX8QM_AUD_GPT6_CLKIN 217
231 #define IMX8QM_AUD_GPT6_24M_CLK 218
232 #define IMX8QM_AUD_GPT7_IPG_S 219
233 #define IMX8QM_AUD_GPT7_CLKIN 220
234 #define IMX8QM_AUD_GPT7_24M_CLK 221
235 #define IMX8QM_AUD_GPT8_IPG_S 222
236 #define IMX8QM_AUD_GPT8_CLKIN 223
237 #define IMX8QM_AUD_GPT8_24M_CLK 224
238 #define IMX8QM_AUD_GPT9_IPG_S 225
239 #define IMX8QM_AUD_GPT9_CLKIN 226
240 #define IMX8QM_AUD_GPT9_24M_CLK 227
241 #define IMX8QM_AUD_GPT10_IPG_S 228
242 #define IMX8QM_AUD_GPT10_CLKIN 229
243 #define IMX8QM_AUD_GPT10_24M_CLK 230
244 #define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232
245 #define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233
246 #define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234
247 #define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235
248 #define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236
249 #define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237
250 #define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238
251 #define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239
252 #define IMX8QM_AUD_MCLKOUT0 240
253 #define IMX8QM_AUD_MCLKOUT1 241
254 #define IMX8QM_AUD_SPDIF_0_TX_CLK 242
255 #define IMX8QM_AUD_SPDIF_0_GCLKW 243
256 #define IMX8QM_AUD_SPDIF_0_IPG_S 244
257 #define IMX8QM_AUD_SPDIF_1_TX_CLK 245
258 #define IMX8QM_AUD_SPDIF_1_GCLKW 246
259 #define IMX8QM_AUD_SPDIF_1_IPG_S 247
260 #define IMX8QM_AUD_ASRC_0_IPG 248
261 #define IMX8QM_AUD_ASRC_0_MEM 249
262 #define IMX8QM_AUD_ASRC_1_IPG 250
263 #define IMX8QM_AUD_ASRC_1_MEM 251
266 #define IMX8QM_VPU_CORE_DIV 252
267 #define IMX8QM_VPU_CORE_CLK 253
268 #define IMX8QM_VPU_UART_DIV 254
269 #define IMX8QM_VPU_UART_CLK 255
270 #define IMX8QM_VPU_DDR_DIV 256
271 #define IMX8QM_VPU_DDR_CLK 257
272 #define IMX8QM_VPU_SYS_DIV 258
273 #define IMX8QM_VPU_SYS_CLK 259
274 #define IMX8QM_VPU_XUVI_DIV 260
275 #define IMX8QM_VPU_XUVI_CLK 261
278 #define IMX8QM_GPU0_CORE_DIV 262
279 #define IMX8QM_GPU0_CORE_CLK 263
280 #define IMX8QM_GPU0_SHADER_DIV 264
281 #define IMX8QM_GPU0_SHADER_CLK 265
282 #define IMX8QM_GPU1_CORE_DIV 266
283 #define IMX8QM_GPU1_CORE_CLK 267
284 #define IMX8QM_GPU1_SHADER_DIV 268
285 #define IMX8QM_GPU1_SHADER_CLK 269
288 #define IMX8QM_CSI0_IPG_CLK_S 270
289 #define IMX8QM_CSI0_LIS_IPG_CLK 271
290 #define IMX8QM_CSI0_APB_CLK 272
291 #define IMX8QM_CSI0_I2C0_DIV 273
292 #define IMX8QM_CSI0_I2C0_CLK 274
293 #define IMX8QM_CSI0_PWM0_DIV 275
294 #define IMX8QM_CSI0_PWM0_CLK 276
295 #define IMX8QM_CSI0_CORE_DIV 277
296 #define IMX8QM_CSI0_CORE_CLK 278
297 #define IMX8QM_CSI0_ESC_DIV 279
298 #define IMX8QM_CSI0_ESC_CLK 280
299 #define IMX8QM_CSI1_IPG_CLK_S 281
300 #define IMX8QM_CSI1_LIS_IPG_CLK 282
301 #define IMX8QM_CSI1_APB_CLK 283
302 #define IMX8QM_CSI1_I2C0_DIV 284
303 #define IMX8QM_CSI1_I2C0_CLK 285
304 #define IMX8QM_CSI1_PWM0_DIV 286
305 #define IMX8QM_CSI1_PWM0_CLK 287
306 #define IMX8QM_CSI1_CORE_DIV 288
307 #define IMX8QM_CSI1_CORE_CLK 289
308 #define IMX8QM_CSI1_ESC_DIV 290
309 #define IMX8QM_CSI1_ESC_CLK 291
312 #define IMX8QM_DC0_PLL0_DIV 292
313 #define IMX8QM_DC0_PLL0_CLK 293
314 #define IMX8QM_DC0_PLL1_DIV 294
315 #define IMX8QM_DC0_PLL1_CLK 295
316 #define IMX8QM_DC0_DISP0_DIV 296
317 #define IMX8QM_DC0_DISP0_CLK 297
318 #define IMX8QM_DC0_DISP1_DIV 298
319 #define IMX8QM_DC0_DISP1_CLK 299
320 #define IMX8QM_DC0_BYPASS_0_DIV 300
321 #define IMX8QM_DC0_BYPASS_1_DIV 301
322 #define IMX8QM_DC0_IRIS_AXI_CLK 302
323 #define IMX8AM_DC0_IRIS_MVPL_CLK 303
324 #define IMX8QM_DC0_DISP0_MSI_CLK 304
325 #define IMX8QM_DC0_LIS_IPG_CLK 305
326 #define IMX8QM_DC0_PXL_CMB_APB_CLK 306
327 #define IMX8QM_DC0_PRG0_RTRAM_CLK 307
328 #define IMX8QM_DC0_PRG1_RTRAM_CLK 308
329 #define IMX8QM_DC0_PRG2_RTRAM_CLK 309
330 #define IMX8QM_DC0_PRG3_RTRAM_CLK 310
331 #define IMX8QM_DC0_PRG4_RTRAM_CLK 311
332 #define IMX8QM_DC0_PRG5_RTRAM_CLK 312
333 #define IMX8QM_DC0_PRG6_RTRAM_CLK 313
334 #define IMX8QM_DC0_PRG7_RTRAM_CLK 314
335 #define IMX8QM_DC0_PRG8_RTRAM_CLK 315
336 #define IMX8QM_DC0_PRG0_APB_CLK 316
337 #define IMX8QM_DC0_PRG1_APB_CLK 317
338 #define IMX8QM_DC0_PRG2_APB_CLK 318
339 #define IMX8QM_DC0_PRG3_APB_CLK 319
340 #define IMX8QM_DC0_PRG4_APB_CLK 320
341 #define IMX8QM_DC0_PRG5_APB_CLK 321
342 #define IMX8QM_DC0_PRG6_APB_CLK 322
343 #define IMX8QM_DC0_PRG7_APB_CLK 323
344 #define IMX8QM_DC0_PRG8_APB_CLK 324
345 #define IMX8QM_DC0_DPR0_APB_CLK 325
346 #define IMX8QM_DC0_DPR1_APB_CLK 326
347 #define IMX8QM_DC0_RTRAM0_CLK 327
348 #define IMX8QM_DC0_RTRAM1_CLK 328
349 #define IMX8QM_DC1_PLL0_DIV 329
350 #define IMX8QM_DC1_PLL0_CLK 330
351 #define IMX8QM_DC1_PLL1_DIV 331
352 #define IMX8QM_DC1_PLL1_CLK 332
353 #define IMX8QM_DC1_DISP0_DIV 333
354 #define IMX8QM_DC1_DISP0_CLK 334
355 #define IMX8QM_DC1_BYPASS_0_DIV 335
356 #define IMX8QM_DC1_BYPASS_1_DIV 336
357 #define IMX8QM_DC1_DISP1_DIV 337
358 #define IMX8QM_DC1_DISP1_CLK 338
359 #define IMX8QM_DC1_IRIS_AXI_CLK 339
360 #define IMX8AM_DC1_IRIS_MVPL_CLK 340
361 #define IMX8QM_DC1_DISP0_MSI_CLK 341
362 #define IMX8QM_DC1_LIS_IPG_CLK 342
363 #define IMX8QM_DC1_PXL_CMB_APB_CLK 343
364 #define IMX8QM_DC1_PRG0_RTRAM_CLK 344
365 #define IMX8QM_DC1_PRG1_RTRAM_CLK 345
366 #define IMX8QM_DC1_PRG2_RTRAM_CLK 346
367 #define IMX8QM_DC1_PRG3_RTRAM_CLK 347
368 #define IMX8QM_DC1_PRG4_RTRAM_CLK 348
369 #define IMX8QM_DC1_PRG5_RTRAM_CLK 349
370 #define IMX8QM_DC1_PRG6_RTRAM_CLK 350
371 #define IMX8QM_DC1_PRG7_RTRAM_CLK 351
372 #define IMX8QM_DC1_PRG8_RTRAM_CLK 352
373 #define IMX8QM_DC1_PRG0_APB_CLK 353
374 #define IMX8QM_DC1_PRG1_APB_CLK 354
375 #define IMX8QM_DC1_PRG2_APB_CLK 355
376 #define IMX8QM_DC1_PRG3_APB_CLK 356
377 #define IMX8QM_DC1_PRG4_APB_CLK 357
378 #define IMX8QM_DC1_PRG5_APB_CLK 358
379 #define IMX8QM_DC1_PRG6_APB_CLK 359
380 #define IMX8QM_DC1_PRG7_APB_CLK 360
381 #define IMX8QM_DC1_PRG8_APB_CLK 361
382 #define IMX8QM_DC1_DPR0_APB_CLK 362
383 #define IMX8QM_DC1_DPR1_APB_CLK 363
384 #define IMX8QM_DC1_RTRAM0_CLK 364
385 #define IMX8QM_DC1_RTRAM1_CLK 365
388 #define IMX8QM_DRC0_PLL0_DIV 366
389 #define IMX8QM_DRC0_PLL0_CLK 367
390 #define IMX8QM_DRC0_DIV 368
391 #define IMX8QM_DRC0_CLK 369
392 #define IMX8QM_DRC1_PLL0_DIV 370
393 #define IMX8QM_DRC1_PLL0_CLK 371
394 #define IMX8QM_DRC1_DIV 372
395 #define IMX8QM_DRC1_CLK 373
398 #define IMX8QM_HDMI_AV_PLL_DIV 374
399 #define IMX8QM_HDMI_AV_PLL_CLK 375
400 #define IMX8QM_HDMI_I2S_BYPASS_CLK 376
401 #define IMX8QM_HDMI_I2C0_DIV 377
402 #define IMX8QM_HDMI_I2C0_CLK 378
403 #define IMX8QM_HDMI_PXL_DIV 379
404 #define IMX8QM_HDMI_PXL_CLK 380
405 #define IMX8QM_HDMI_PXL_LINK_DIV 381
406 #define IMX8QM_HDMI_PXL_LINK_CLK 382
407 #define IMX8QM_HDMI_PXL_MUX_DIV 383
408 #define IMX8QM_HDMI_PXL_MUX_CLK 384
409 #define IMX8QM_HDMI_I2S_DIV 385
410 #define IMX8QM_HDMI_I2S_CLK 386
411 #define IMX8QM_HDMI_HDP_CORE_DIV 387
412 #define IMX8QM_HDMI_HDP_CORE_CLK 388
413 #define IMX8QM_HDMI_I2C_IPG_S_CLK 389
414 #define IMX8QM_HDMI_I2C_IPG_CLK 390
415 #define IMX8QM_HDMI_PWM_IPG_S_CLK 391
416 #define IMX8QM_HDMI_PWM_IPG_CLK 392
417 #define IMX8QM_HDMI_PWM_32K_CLK 393
418 #define IMX8QM_HDMI_GPIO_IPG_CLK 394
419 #define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395
420 #define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396
421 #define IMX8QM_HDMI_LIS_IPG_CLK 397
422 #define IMX8QM_HDMI_MSI_HCLK 398
423 #define IMX8QM_HDMI_PXL_EVEN_CLK 399
424 #define IMX8QM_HDMI_HDP_CLK 400
425 #define IMX8QM_HDMI_PXL_DBL_CLK 401
426 #define IMX8QM_HDMI_APB_CLK 402
427 #define IMX8QM_HDMI_PXL_LPCG_CLK 403
428 #define IMX8QM_HDMI_HDP_PHY_CLK 404
429 #define IMX8QM_HDMI_IPG_DIV 405
430 #define IMX8QM_HDMI_VIF_CLK 406
431 #define IMX8QM_HDMI_DIG_PLL_DIV 407
432 #define IMX8QM_HDMI_DIG_PLL_CLK 408
433 #define IMX8QM_HDMI_APB_MUX_CSR_CLK 409
434 #define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410
437 #define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411
438 #define IMX8QM_HDMI_RX_BYPASS_CLK 412
439 #define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413
440 #define IMX8QM_HDMI_RX_I2C0_DIV 414
441 #define IMX8QM_HDMI_RX_I2C0_CLK 415
442 #define IMX8QM_HDMI_RX_SPDIF_DIV 416
443 #define IMX8QM_HDMI_RX_SPDIF_CLK 417
444 #define IMX8QM_HDMI_RX_HD_REF_DIV 418
445 #define IMX8QM_HDMI_RX_HD_REF_CLK 419
446 #define IMX8QM_HDMI_RX_HD_CORE_DIV 420
447 #define IMX8QM_HDMI_RX_HD_CORE_CLK 421
448 #define IMX8QM_HDMI_RX_PXL_DIV 422
449 #define IMX8QM_HDMI_RX_PXL_CLK 423
450 #define IMX8QM_HDMI_RX_I2S_DIV 424
451 #define IMX8QM_HDMI_RX_I2S_CLK 425
452 #define IMX8QM_HDMI_RX_PWM_DIV 426
453 #define IMX8QM_HDMI_RX_PWM_CLK 427
456 #define IMX8QM_LVDS0_BYPASS_CLK 428
457 #define IMX8QM_LVDS0_PIXEL_DIV 429
458 #define IMX8QM_LVDS0_PIXEL_CLK 430
459 #define IMX8QM_LVDS0_PHY_DIV 431
460 #define IMX8QM_LVDS0_PHY_CLK 432
461 #define IMX8QM_LVDS0_I2C0_IPG_CLK 433
462 #define IMX8QM_LVDS0_I2C0_DIV 434
463 #define IMX8QM_LVDS0_I2C0_CLK 435
464 #define IMX8QM_LVDS0_I2C1_IPG_CLK 436
465 #define IMX8QM_LVDS0_I2C1_DIV 437
466 #define IMX8QM_LVDS0_I2C1_CLK 438
467 #define IMX8QM_LVDS0_PWM0_IPG_CLK 439
468 #define IMX8QM_LVDS0_PWM0_DIV 440
469 #define IMX8QM_LVDS0_PWM0_CLK 441
470 #define IMX8QM_LVDS0_GPIO_IPG_CLK 444
471 #define IMX8QM_LVDS1_BYPASS_DIV 445
472 #define IMX8QM_LVDS1_BYPASS_CLK 446
473 #define IMX8QM_LVDS1_PIXEL_DIV 447
474 #define IMX8QM_LVDS1_PIXEL_CLK 448
475 #define IMX8QM_LVDS1_PHY_DIV 449
476 #define IMX8QM_LVDS1_PHY_CLK 450
477 #define IMX8QM_LVDS1_I2C0_IPG_CLK 451
478 #define IMX8QM_LVDS1_I2C0_DIV 452
479 #define IMX8QM_LVDS1_I2C0_CLK 453
480 #define IMX8QM_LVDS1_I2C1_IPG_CLK 454
481 #define IMX8QM_LVDS1_I2C1_DIV 455
482 #define IMX8QM_LVDS1_I2C1_CLK 456
483 #define IMX8QM_LVDS1_PWM0_IPG_CLK 457
484 #define IMX8QM_LVDS1_PWM0_DIV 458
485 #define IMX8QM_LVDS1_PWM0_CLK 459
486 #define IMX8QM_LVDS1_GPIO_IPG_CLK 462
489 #define IMX8QM_MIPI0_BYPASS_CLK 465
490 #define IMX8QM_MIPI0_I2C0_DIV 466
491 #define IMX8QM_MIPI0_I2C0_CLK 467
492 #define IMX8QM_MIPI0_I2C1_DIV 468
493 #define IMX8QM_MIPI0_I2C1_CLK 469
494 #define IMX8QM_MIPI0_PWM0_DIV 470
495 #define IMX8QM_MIPI0_PWM0_CLK 471
496 #define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472
497 #define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473
498 #define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474
499 #define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475
500 #define IMX8QM_MIPI0_PXL_DIV 476
501 #define IMX8QM_MIPI0_PXL_CLK 477
502 #define IMX8QM_MIPI1_BYPASS_CLK 479
503 #define IMX8QM_MIPI1_I2C0_DIV 480
504 #define IMX8QM_MIPI1_I2C0_CLK 481
505 #define IMX8QM_MIPI1_I2C1_DIV 482
506 #define IMX8QM_MIPI1_I2C1_CLK 483
507 #define IMX8QM_MIPI1_PWM0_DIV 484
508 #define IMX8QM_MIPI1_PWM0_CLK 485
509 #define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486
510 #define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487
511 #define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488
512 #define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489
513 #define IMX8QM_MIPI1_PXL_DIV 490
514 #define IMX8QM_MIPI1_PXL_CLK 491
517 #define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492
518 #define IMX8QM_IMG_JPEG_ENC_CLK 493
519 #define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494
520 #define IMX8QM_IMG_JPEG_DEC_CLK 495
521 #define IMX8QM_IMG_PXL_LINK_DC0_CLK 496
522 #define IMX8QM_IMG_PXL_LINK_DC1_CLK 497
523 #define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498
524 #define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499
525 #define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500
526 #define IMX8QM_IMG_PDMA_0_CLK 501
527 #define IMX8QM_IMG_PDMA_1_CLK 502
528 #define IMX8QM_IMG_PDMA_2_CLK 503
529 #define IMX8QM_IMG_PDMA_3_CLK 504
530 #define IMX8QM_IMG_PDMA_4_CLK 505
531 #define IMX8QM_IMG_PDMA_5_CLK 506
532 #define IMX8QM_IMG_PDMA_6_CLK 507
533 #define IMX8QM_IMG_PDMA_7_CLK 508
536 #define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509
537 #define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510
538 #define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511
539 #define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512
540 #define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513
541 #define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514
542 #define IMX8QM_HSIO_PCIE_X1_PER_CLK 515
543 #define IMX8QM_HSIO_PCIE_X2_PER_CLK 516
544 #define IMX8QM_HSIO_SATA_PER_CLK 517
545 #define IMX8QM_HSIO_PHY_X1_PER_CLK 518
546 #define IMX8QM_HSIO_PHY_X2_PER_CLK 519
547 #define IMX8QM_HSIO_MISC_PER_CLK 520
548 #define IMX8QM_HSIO_PHY_X1_APB_CLK 521
549 #define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522
550 #define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523
551 #define IMX8QM_HSIO_SATA_CLK 524
552 #define IMX8QM_HSIO_GPIO_CLK 525
553 #define IMX8QM_HSIO_PHY_X1_PCLK 526
554 #define IMX8QM_HSIO_PHY_X2_PCLK_0 527
555 #define IMX8QM_HSIO_PHY_X2_PCLK_1 528
556 #define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529
557 #define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530
560 #define IMX8QM_M4_0_CORE_DIV 531
561 #define IMX8QM_M4_0_CORE_CLK 532
562 #define IMX8QM_M4_0_I2C_DIV 533
563 #define IMX8QM_M4_0_I2C_CLK 534
564 #define IMX8QM_M4_0_PIT_DIV 535
565 #define IMX8QM_M4_0_PIT_CLK 536
566 #define IMX8QM_M4_0_TPM_DIV 537
567 #define IMX8QM_M4_0_TPM_CLK 538
568 #define IMX8QM_M4_0_UART_DIV 539
569 #define IMX8QM_M4_0_UART_CLK 540
570 #define IMX8QM_M4_0_WDOG_DIV 541
571 #define IMX8QM_M4_0_WDOG_CLK 542
572 #define IMX8QM_M4_1_CORE_DIV 543
573 #define IMX8QM_M4_1_CORE_CLK 544
574 #define IMX8QM_M4_1_I2C_DIV 545
575 #define IMX8QM_M4_1_I2C_CLK 546
576 #define IMX8QM_M4_1_PIT_DIV 547
577 #define IMX8QM_M4_1_PIT_CLK 548
578 #define IMX8QM_M4_1_TPM_DIV 549
579 #define IMX8QM_M4_1_TPM_CLK 550
580 #define IMX8QM_M4_1_UART_DIV 551
581 #define IMX8QM_M4_1_UART_CLK 552
582 #define IMX8QM_M4_1_WDOG_DIV 553
583 #define IMX8QM_M4_1_WDOG_CLK 554
586 #define IMX8QM_24MHZ 555
587 #define IMX8QM_GPT_3M 556
588 #define IMX8QM_IPG_DMA_CLK_ROOT 557
589 #define IMX8QM_IPG_AUD_CLK_ROOT 558
590 #define IMX8QM_IPG_CONN_CLK_ROOT 559
591 #define IMX8QM_AHB_CONN_CLK_ROOT 560
592 #define IMX8QM_AXI_CONN_CLK_ROOT 561
593 #define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562
594 #define IMX8QM_DC_AXI_EXT_CLK 563
595 #define IMX8QM_DC_AXI_INT_CLK 564
596 #define IMX8QM_DC_CFG_CLK 565
597 #define IMX8QM_HDMI_IPG_CLK 566
598 #define IMX8QM_LVDS_IPG_CLK 567
599 #define IMX8QM_IMG_AXI_CLK 568
600 #define IMX8QM_IMG_IPG_CLK 569
601 #define IMX8QM_IMG_PXL_CLK 570
602 #define IMX8QM_CSI0_I2C0_IPG_CLK 571
603 #define IMX8QM_CSI0_PWM0_IPG_CLK 572
604 #define IMX8QM_CSI1_I2C0_IPG_CLK 573
605 #define IMX8QM_CSI1_PWM0_IPG_CLK 574
606 #define IMX8QM_DC0_DPR0_B_CLK 575
607 #define IMX8QM_DC0_DPR1_B_CLK 576
608 #define IMX8QM_DC1_DPR0_B_CLK 577
609 #define IMX8QM_DC1_DPR1_B_CLK 578
610 #define IMX8QM_32KHZ 579
611 #define IMX8QM_HSIO_AXI_CLK 580
612 #define IMX8QM_HSIO_PER_CLK 581
613 #define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582
614 #define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583
615 #define IMX8QM_HDMI_RX_PWM_IPG_CLK 584
616 #define IMX8QM_HDMI_RX_I2C_DIV_CLK 585
617 #define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586
618 #define IMX8QM_HDMI_RX_I2C_IPG_CLK 587
619 #define IMX8QM_HDMI_RX_SINK_PCLK 588
620 #define IMX8QM_HDMI_RX_SINK_SCLK 589
621 #define IMX8QM_HDMI_RX_PXL_ENC_CLK 590
622 #define IMX8QM_HDMI_RX_IPG_CLK 591
625 #define IMX8QM_HDMI_RX_MCLK 592
626 #define IMX8QM_EXT_AUD_MCLK0 593
627 #define IMX8QM_EXT_AUD_MCLK1 594
628 #define IMX8QM_ESAI0_RX_CLK 595
629 #define IMX8QM_ESAI0_RX_HF_CLK 596
630 #define IMX8QM_ESAI0_TX_CLK 597
631 #define IMX8QM_ESAI0_TX_HF_CLK 598
632 #define IMX8QM_ESAI1_RX_CLK 599
633 #define IMX8QM_ESAI1_RX_HF_CLK 600
634 #define IMX8QM_ESAI1_TX_CLK 601
635 #define IMX8QM_ESAI1_TX_HF_CLK 602
636 #define IMX8QM_SPDIF0_RX 603
637 #define IMX8QM_SPDIF1_RX 604
638 #define IMX8QM_SAI0_RX_BCLK 605
639 #define IMX8QM_SAI0_TX_BCLK 606
640 #define IMX8QM_SAI1_RX_BCLK 607
641 #define IMX8QM_SAI1_TX_BCLK 608
642 #define IMX8QM_SAI2_RX_BCLK 609
643 #define IMX8QM_SAI3_RX_BCLK 610
644 #define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611
645 #define IMX8QM_SAI6_RX_BCLK 612
646 #define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613
648 #define IMX8QM_ACM_AUD_CLK0_SEL 614
649 #define IMX8QM_ACM_AUD_CLK0_CLK 615
650 #define IMX8QM_ACM_AUD_CLK1_SEL 616
651 #define IMX8QM_ACM_AUD_CLK1_CLK 617
652 #define IMX8QM_ACM_MCLKOUT0_SEL 618
653 #define IMX8QM_ACM_MCLKOUT0_CLK 619
654 #define IMX8QM_ACM_MCLKOUT1_SEL 620
655 #define IMX8QM_ACM_MCLKOUT1_CLK 621
656 #define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622
657 #define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623
658 #define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624
659 #define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625
660 #define IMX8QM_ACM_ESAI0_MCLK_SEL 626
661 #define IMX8QM_ACM_ESAI0_MCLK_CLK 627
662 #define IMX8QM_ACM_ESAI1_MCLK_SEL 628
663 #define IMX8QM_ACM_ESAI1_MCLK_CLK 629
664 #define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630
665 #define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631
666 #define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632
667 #define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633
668 #define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634
669 #define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635
670 #define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636
671 #define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637
672 #define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638
673 #define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639
674 #define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640
675 #define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641
676 #define IMX8QM_ACM_SAI0_MCLK_SEL 642
677 #define IMX8QM_ACM_SAI0_MCLK_CLK 643
678 #define IMX8QM_ACM_SAI1_MCLK_SEL 644
679 #define IMX8QM_ACM_SAI1_MCLK_CLK 645
680 #define IMX8QM_ACM_SAI2_MCLK_SEL 646
681 #define IMX8QM_ACM_SAI2_MCLK_CLK 647
682 #define IMX8QM_ACM_SAI3_MCLK_SEL 648
683 #define IMX8QM_ACM_SAI3_MCLK_CLK 649
684 #define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650
685 #define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651
686 #define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652
687 #define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653
688 #define IMX8QM_ACM_SAI6_MCLK_SEL 654
689 #define IMX8QM_ACM_SAI6_MCLK_CLK 655
690 #define IMX8QM_ACM_SAI7_MCLK_SEL 656
691 #define IMX8QM_ACM_SAI7_MCLK_CLK 657
692 #define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658
693 #define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659
694 #define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660
695 #define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661
696 #define IMX8QM_ACM_MQS_TX_CLK_SEL 662
697 #define IMX8QM_ACM_MQS_TX_CLK_CLK 663
699 #define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664
700 #define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665
701 #define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666
702 #define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667
703 #define IMX8QM_ENET0_REF_50MHZ_CLK 668
704 #define IMX8QM_ENET1_REF_50MHZ_CLK 669
705 #define IMX8QM_ENET_25MHZ_CLK 670
706 #define IMX8QM_ENET_125MHZ_CLK 671
707 #define IMX8QM_ENET0_REF_DIV 672
708 #define IMX8QM_ENET0_REF_CLK 673
709 #define IMX8QM_ENET1_REF_DIV 674
710 #define IMX8QM_ENET1_REF_CLK 675
711 #define IMX8QM_ENET0_RMII_TX_CLK 676
712 #define IMX8QM_ENET1_RMII_TX_CLK 677
713 #define IMX8QM_ENET0_RMII_TX_SEL 678
714 #define IMX8QM_ENET1_RMII_TX_SEL 679
715 #define IMX8QM_ENET0_RMII_RX_CLK 680
716 #define IMX8QM_ENET1_RMII_RX_CLK 681
718 #define IMX8QM_KPP_CLK 683
719 #define IMX8QM_GPT0_HF_CLK 684
720 #define IMX8QM_GPT0_IPG_S_CLK 685
721 #define IMX8QM_GPT0_IPG_SLV_CLK 686
722 #define IMX8QM_GPT0_IPG_MSTR_CLK 687
723 #define IMX8QM_GPT1_HF_CLK 688
724 #define IMX8QM_GPT1_IPG_S_CLK 689
725 #define IMX8QM_GPT1_IPG_SLV_CLK 690
726 #define IMX8QM_GPT1_IPG_MSTR_CLK 691
727 #define IMX8QM_GPT2_HF_CLK 692
728 #define IMX8QM_GPT2_IPG_S_CLK 693
729 #define IMX8QM_GPT2_IPG_SLV_CLK 694
730 #define IMX8QM_GPT2_IPG_MSTR_CLK 695
731 #define IMX8QM_GPT3_HF_CLK 696
732 #define IMX8QM_GPT3_IPG_S_CLK 697
733 #define IMX8QM_GPT3_IPG_SLV_CLK 698
734 #define IMX8QM_GPT3_IPG_MSTR_CLK 699
735 #define IMX8QM_GPT4_HF_CLK 700
736 #define IMX8QM_GPT4_IPG_S_CLK 701
737 #define IMX8QM_GPT4_IPG_SLV_CLK 702
738 #define IMX8QM_GPT4_IPG_MSTR_CLK 703
739 #define IMX8QM_PWM0_HF_CLK 704
740 #define IMX8QM_PWM0_IPG_S_CLK 705
741 #define IMX8QM_PWM0_IPG_SLV_CLK 706
742 #define IMX8QM_PWM0_IPG_MSTR_CLK 707
743 #define IMX8QM_PWM1_HF_CLK 708
744 #define IMX8QM_PWM1_IPG_S_CLK 709
745 #define IMX8QM_PWM1_IPG_SLV_CLK 710
746 #define IMX8QM_PWM1_IPG_MSTR_CLK 711
747 #define IMX8QM_PWM2_HF_CLK 712
748 #define IMX8QM_PWM2_IPG_S_CLK 713
749 #define IMX8QM_PWM2_IPG_SLV_CLK 714
750 #define IMX8QM_PWM2_IPG_MSTR_CLK 715
751 #define IMX8QM_PWM3_HF_CLK 716
752 #define IMX8QM_PWM3_IPG_S_CLK 717
753 #define IMX8QM_PWM3_IPG_SLV_CLK 718
754 #define IMX8QM_PWM3_IPG_MSTR_CLK 719
755 #define IMX8QM_PWM4_HF_CLK 720
756 #define IMX8QM_PWM4_IPG_S_CLK 721
757 #define IMX8QM_PWM4_IPG_SLV_CLK 722
758 #define IMX8QM_PWM4_IPG_MSTR_CLK 723
759 #define IMX8QM_PWM5_HF_CLK 724
760 #define IMX8QM_PWM5_IPG_S_CLK 725
761 #define IMX8QM_PWM5_IPG_SLV_CLK 726
762 #define IMX8QM_PWM5_IPG_MSTR_CLK 727
763 #define IMX8QM_PWM6_HF_CLK 728
764 #define IMX8QM_PWM6_IPG_S_CLK 729
765 #define IMX8QM_PWM6_IPG_SLV_CLK 730
766 #define IMX8QM_PWM6_IPG_MSTR_CLK 731
767 #define IMX8QM_PWM7_HF_CLK 732
768 #define IMX8QM_PWM7_IPG_S_CLK 733
769 #define IMX8QM_PWM7_IPG_SLV_CLK 734
770 #define IMX8QM_PWM7_IPG_MSTR_CLK 735
771 #define IMX8QM_FSPI0_HCLK 736
772 #define IMX8QM_FSPI0_IPG_CLK 737
773 #define IMX8QM_FSPI0_IPG_S_CLK 738
774 #define IMX8QM_FSPI1_HCLK 736
775 #define IMX8QM_FSPI1_IPG_CLK 737
776 #define IMX8QM_FSPI1_IPG_S_CLK 738
777 #define IMX8QM_GPIO0_IPG_S_CLK 739
778 #define IMX8QM_GPIO1_IPG_S_CLK 740
779 #define IMX8QM_GPIO2_IPG_S_CLK 741
780 #define IMX8QM_GPIO3_IPG_S_CLK 742
781 #define IMX8QM_GPIO4_IPG_S_CLK 743
782 #define IMX8QM_GPIO5_IPG_S_CLK 744
783 #define IMX8QM_GPIO6_IPG_S_CLK 745
784 #define IMX8QM_GPIO7_IPG_S_CLK 746
785 #define IMX8QM_ROMCP_CLK 747
786 #define IMX8QM_ROMCP_REG_CLK 748
787 #define IMX8QM_96KROM_CLK 749
788 #define IMX8QM_OCRAM_MEM_CLK 750
789 #define IMX8QM_OCRAM_CTRL_CLK 751
790 #define IMX8QM_LSIO_BUS_CLK 752
791 #define IMX8QM_LSIO_MEM_CLK 753
792 #define IMX8QM_LVDS0_LIS_IPG_CLK 754
793 #define IMX8QM_LVDS1_LIS_IPG_CLK 755
794 #define IMX8QM_MIPI0_LIS_IPG_CLK 756
795 #define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757
796 #define IMX8QM_MIPI0_I2C0_IPG_CLK 758
797 #define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759
798 #define IMX8QM_MIPI0_I2C1_IPG_CLK 760
799 #define IMX8QM_MIPI0_CLK_ROOT 761
800 #define IMX8QM_MIPI1_LIS_IPG_CLK 762
801 #define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763
802 #define IMX8QM_MIPI1_I2C0_IPG_CLK 764
803 #define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765
804 #define IMX8QM_MIPI1_I2C1_IPG_CLK 766
805 #define IMX8QM_MIPI1_CLK_ROOT 767
806 #define IMX8QM_DC0_DISP0_SEL 768
807 #define IMX8QM_DC0_DISP1_SEL 769
808 #define IMX8QM_DC1_DISP0_SEL 770
809 #define IMX8QM_DC1_DISP1_SEL 771
812 #define IMX8QM_CM40_IPG_CLK 772
813 #define IMX8QM_CM40_I2C_DIV 773
814 #define IMX8QM_CM40_I2C_CLK 774
815 #define IMX8QM_CM40_I2C_IPG_CLK 775
818 #define IMX8QM_CM41_IPG_CLK 776
819 #define IMX8QM_CM41_I2C_DIV 777
820 #define IMX8QM_CM41_I2C_CLK 778
821 #define IMX8QM_CM41_I2C_IPG_CLK 779
823 #define IMX8QM_HDMI_PXL_SEL 780
824 #define IMX8QM_HDMI_PXL_LINK_SEL 781
825 #define IMX8QM_HDMI_PXL_MUX_SEL 782
826 #define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783
828 #define IMX8QM_HDMI_RX_PXL_SEL 784
829 #define IMX8QM_HDMI_RX_HD_REF_SEL 785
830 #define IMX8QM_HDMI_RX_HD_CORE_SEL 786
831 #define IMX8QM_HDMI_RX_DIG_PLL_CLK 787
833 #define IMX8QM_LSIO_MU5A_IPG_S_CLK 788
834 #define IMX8QM_LSIO_MU5A_IPG_CLK 789
835 #define IMX8QM_LSIO_MU6A_IPG_S_CLK 790
836 #define IMX8QM_LSIO_MU6A_IPG_CLK 791
839 #define IMX8QM_AUD_DSP_ADB_ACLK 792
840 #define IMX8QM_AUD_DSP_IPG 793
841 #define IMX8QM_AUD_DSP_CORE_CLK 794
842 #define IMX8QM_AUD_OCRAM_IPG 795
844 #define IMX8QM_CLK_END 796
846 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */