9 #define CLKID_HDMI_PLL 2
10 #define CLKID_FCLK_DIV2 4
11 #define CLKID_FCLK_DIV3 5
12 #define CLKID_FCLK_DIV4 6
13 #define CLKID_CLK81 12
14 #define CLKID_MPLL2 15
17 #define CLKID_SAR_ADC 23
22 #define CLKID_HDMI_PCLK 63
23 #define CLKID_USB1_DDR_BRIDGE 64
24 #define CLKID_USB0_DDR_BRIDGE 65
26 #define CLKID_GCLK_VENCI_INT0 77
27 #define CLKID_AO_I2C 93
28 #define CLKID_SD_EMMC_A 94
29 #define CLKID_SD_EMMC_B 95
30 #define CLKID_SD_EMMC_C 96
31 #define CLKID_SAR_ADC_CLK 97
32 #define CLKID_SAR_ADC_SEL 98
34 #endif /* __GXBB_CLKC_H */