1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013 - 2017 Xilinx.
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
9 #ifndef __CONFIG_ZYNQ_CSE_H
10 #define __CONFIG_ZYNQ_CSE_H
12 #define CONFIG_SKIP_LOWLEVEL_INIT
13 #define CONFIG_SYS_DCACHE_OFF
14 #define CONFIG_SYS_ICACHE_OFF
16 #include <configs/zynq-common.h>
18 /* Undef unneeded configs */
19 #undef CONFIG_EXTRA_ENV_SETTINGS
20 #undef CONFIG_BOARD_LATE_INIT
24 #undef CONFIG_SYS_CBSIZE
25 #undef CONFIG_BOOTM_VXWORKS
26 #undef CONFIG_BOOTM_LINUX
28 #define CONFIG_SYS_CBSIZE 1024
30 #undef CONFIG_SYS_INIT_RAM_ADDR
31 #undef CONFIG_SYS_INIT_RAM_SIZE
32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
33 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
34 #undef CONFIG_SPL_BSS_START_ADDR
35 #undef CONFIG_SPL_BSS_MAX_SIZE
36 #define CONFIG_SPL_BSS_START_ADDR 0x20000
37 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000
39 #endif /* __CONFIG_ZYNQ_CSE_H */